1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
10 #include "otx2_cryptodev.h"
11 #include "otx2_cryptodev_capabilities.h"
12 #include "otx2_cryptodev_hw_access.h"
13 #include "otx2_cryptodev_mbox.h"
14 #include "otx2_cryptodev_ops.h"
15 #include "otx2_mbox.h"
17 #include "cpt_hw_types.h"
18 #include "cpt_pmd_logs.h"
19 #include "cpt_pmd_ops_helper.h"
20 #include "cpt_ucode.h"
21 #include "cpt_ucode_asym.h"
23 #define METABUF_POOL_CACHE_SIZE 512
25 /* Forward declarations */
28 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
31 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
33 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
37 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
38 struct otx2_cpt_qp *qp, uint8_t qp_id,
41 char mempool_name[RTE_MEMPOOL_NAMESIZE];
42 struct cpt_qp_meta_info *meta_info;
43 struct rte_mempool *pool;
49 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
51 /* Get meta len for scatter gather mode */
52 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
54 /* Extra 32B saved for future considerations */
55 sg_mlen += 4 * sizeof(uint64_t);
57 /* Get meta len for linear buffer (direct) mode */
58 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
60 /* Extra 32B saved for future considerations */
61 lb_mlen += 4 * sizeof(uint64_t);
64 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
66 /* Get meta len required for asymmetric operations */
67 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
71 * Check max requirement for meta buffer to
72 * support crypto op of any type (sym/asym).
74 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
76 /* Allocate mempool */
78 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
79 dev->data->dev_id, qp_id);
81 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
82 METABUF_POOL_CACHE_SIZE, 0,
86 CPT_LOG_ERR("Could not create mempool for metabuf");
90 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
93 CPT_LOG_ERR("Could not set mempool ops");
97 ret = rte_mempool_populate_default(pool);
99 CPT_LOG_ERR("Could not populate metabuf pool");
103 meta_info = &qp->meta_info;
105 meta_info->pool = pool;
106 meta_info->lb_mlen = lb_mlen;
107 meta_info->sg_mlen = sg_mlen;
112 rte_mempool_free(pool);
117 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
119 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
121 rte_mempool_free(meta_info->pool);
123 meta_info->pool = NULL;
124 meta_info->lb_mlen = 0;
125 meta_info->sg_mlen = 0;
128 static struct otx2_cpt_qp *
129 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
132 struct otx2_cpt_vf *vf = dev->data->dev_private;
133 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
134 const struct rte_memzone *lf_mem;
135 uint32_t len, iq_len, size_div40;
136 char name[RTE_MEMZONE_NAMESIZE];
137 uint64_t used_len, iova;
138 struct otx2_cpt_qp *qp;
143 /* Allocate queue pair */
144 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
147 CPT_LOG_ERR("Could not allocate queue pair");
151 iq_len = OTX2_CPT_IQ_LEN;
154 * Queue size must be a multiple of 40 and effective queue size to
155 * software is (size_div40 - 1) * 40
157 size_div40 = (iq_len + 40 - 1) / 40 + 1;
159 /* For pending queue */
160 len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
162 /* Space for instruction group memory */
163 len += size_div40 * 16;
165 /* So that instruction queues start as pg size aligned */
166 len = RTE_ALIGN(len, pg_sz);
168 /* For instruction queues */
169 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
171 /* Wastage after instruction queues */
172 len = RTE_ALIGN(len, pg_sz);
174 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
177 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
178 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
179 RTE_CACHE_LINE_SIZE);
180 if (lf_mem == NULL) {
181 CPT_LOG_ERR("Could not allocate reserved memzone");
190 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
192 CPT_LOG_ERR("Could not create mempool for metabuf");
196 /* Initialize pending queue */
197 qp->pend_q.rid_queue = (struct rid *)va;
198 qp->pend_q.enq_tail = 0;
199 qp->pend_q.deq_head = 0;
200 qp->pend_q.pending_count = 0;
202 used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
203 used_len += size_div40 * 16;
204 used_len = RTE_ALIGN(used_len, pg_sz);
207 qp->iq_dma_addr = iova;
209 qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
211 lmtline = vf->otx2_dev.bar2 +
212 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
213 OTX2_LMT_LF_LMTLINE(0);
215 qp->lmtline = (void *)lmtline;
217 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
219 otx2_cpt_iq_disable(qp);
221 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
224 CPT_LOG_ERR("Could not enable instruction queue");
225 goto mempool_destroy;
231 otx2_cpt_metabuf_mempool_destroy(qp);
233 rte_memzone_free(lf_mem);
240 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
242 const struct rte_memzone *lf_mem;
243 char name[RTE_MEMZONE_NAMESIZE];
246 otx2_cpt_iq_disable(qp);
248 otx2_cpt_metabuf_mempool_destroy(qp);
250 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
253 lf_mem = rte_memzone_lookup(name);
255 ret = rte_memzone_free(lf_mem);
265 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
266 struct rte_cryptodev_sym_session *sess,
267 struct rte_mempool *pool)
269 struct cpt_sess_misc *misc;
273 if (unlikely(cpt_is_algo_supported(xform))) {
274 CPT_LOG_ERR("Crypto xform not supported");
278 if (unlikely(rte_mempool_get(pool, &priv))) {
279 CPT_LOG_ERR("Could not allocate session private data");
285 for ( ; xform != NULL; xform = xform->next) {
286 switch (xform->type) {
287 case RTE_CRYPTO_SYM_XFORM_AEAD:
288 ret = fill_sess_aead(xform, misc);
290 case RTE_CRYPTO_SYM_XFORM_CIPHER:
291 ret = fill_sess_cipher(xform, misc);
293 case RTE_CRYPTO_SYM_XFORM_AUTH:
294 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
295 ret = fill_sess_gmac(xform, misc);
297 ret = fill_sess_auth(xform, misc);
307 set_sym_session_private_data(sess, driver_id, misc);
309 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
310 sizeof(struct cpt_sess_misc);
313 * IE engines support IPsec operations
314 * SE engines support IPsec operations and Air-Crypto operations
317 misc->egrp = OTX2_CPT_EGRP_SE;
319 misc->egrp = OTX2_CPT_EGRP_SE_IE;
324 rte_mempool_put(pool, priv);
326 CPT_LOG_ERR("Crypto xform not supported");
331 sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
333 void *priv = get_sym_session_private_data(sess, driver_id);
334 struct rte_mempool *pool;
339 memset(priv, 0, cpt_get_session_size());
341 pool = rte_mempool_from_obj(priv);
343 set_sym_session_private_data(sess, driver_id, NULL);
345 rte_mempool_put(pool, priv);
348 static __rte_always_inline int32_t __hot
349 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
350 struct pending_queue *pend_q,
351 struct cpt_request_info *req)
353 void *lmtline = qp->lmtline;
354 union cpt_inst_s inst;
357 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
361 inst.s9x.res_addr = req->comp_baddr;
365 inst.s9x.ei0 = req->ist.ei0;
366 inst.s9x.ei1 = req->ist.ei1;
367 inst.s9x.ei2 = req->ist.ei2;
368 inst.s9x.ei3 = req->ist.ei3;
370 req->time_out = rte_get_timer_cycles() +
371 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
374 /* Copy CPT command to LMTLINE */
375 memcpy(lmtline, &inst, sizeof(inst));
378 * Make sure compiler does not reorder memcpy and ldeor.
379 * LMTST transactions are always flushed from the write
380 * buffer immediately, a DMB is not required to push out
384 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
385 } while (lmt_status == 0);
387 pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
389 /* We will use soft queue length here to limit requests */
390 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
391 pend_q->pending_count += 1;
396 static __rte_always_inline int32_t __hot
397 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
398 struct rte_crypto_op *op,
399 struct pending_queue *pend_q)
401 struct cpt_qp_meta_info *minfo = &qp->meta_info;
402 struct rte_crypto_asym_op *asym_op = op->asym;
403 struct asym_op_params params = {0};
404 struct cpt_asym_sess_misc *sess;
410 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
411 CPT_LOG_ERR("Could not allocate meta buffer for request");
415 sess = get_asym_session_private_data(asym_op->session,
416 otx2_cryptodev_driver_id);
418 /* Store IO address of the mdata to meta_buf */
419 params.meta_buf = rte_mempool_virt2iova(mdata);
422 cop[0] = (uintptr_t)mdata;
423 cop[1] = (uintptr_t)op;
424 cop[2] = cop[3] = 0ULL;
426 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
427 params.req->op = cop;
429 /* Adjust meta_buf to point to end of cpt_request_info structure */
430 params.meta_buf += (4 * sizeof(uintptr_t)) +
431 sizeof(struct cpt_request_info);
432 switch (sess->xfrm_type) {
433 case RTE_CRYPTO_ASYM_XFORM_MODEX:
434 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
438 case RTE_CRYPTO_ASYM_XFORM_RSA:
439 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
444 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
449 /* Set engine group of AE */
450 w3 = (vq_cmd_word3_t *)¶ms.req->ist.ei3;
451 w3->s.grp = OTX2_CPT_EGRP_AE;
453 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req);
456 CPT_LOG_DP_ERR("Could not enqueue crypto req");
463 free_op_meta(mdata, minfo->pool);
468 static __rte_always_inline int __hot
469 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
470 struct pending_queue *pend_q)
472 struct rte_crypto_sym_op *sym_op = op->sym;
473 struct cpt_request_info *req;
474 struct cpt_sess_misc *sess;
480 sess = get_sym_session_private_data(sym_op->session,
481 otx2_cryptodev_driver_id);
483 cpt_op = sess->cpt_op;
485 if (cpt_op & CPT_OP_CIPHER_MASK)
486 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
489 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
493 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
494 op, (unsigned int)cpt_op, ret);
498 w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
499 w3->s.grp = sess->egrp;
501 ret = otx2_cpt_enqueue_req(qp, pend_q, req);
504 /* Free buffer allocated by fill params routines */
505 free_op_meta(mdata, qp->meta_info.pool);
511 static __rte_always_inline int __hot
512 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
513 struct pending_queue *pend_q)
515 const int driver_id = otx2_cryptodev_driver_id;
516 struct rte_crypto_sym_op *sym_op = op->sym;
517 struct rte_cryptodev_sym_session *sess;
520 /* Create temporary session */
522 if (rte_mempool_get(qp->sess_mp, (void **)&sess))
525 ret = sym_session_configure(driver_id, sym_op->xform, sess,
530 sym_op->session = sess;
532 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
540 sym_session_clear(driver_id, sess);
542 rte_mempool_put(qp->sess_mp, sess);
547 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
549 uint16_t nb_allowed, count = 0;
550 struct otx2_cpt_qp *qp = qptr;
551 struct pending_queue *pend_q;
552 struct rte_crypto_op *op;
555 pend_q = &qp->pend_q;
557 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
558 if (nb_ops > nb_allowed)
561 for (count = 0; count < nb_ops; count++) {
563 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
564 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
565 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
567 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
569 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
570 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
571 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
584 static __rte_always_inline void
585 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
586 struct rte_crypto_rsa_xform *rsa_ctx)
588 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
590 switch (rsa->op_type) {
591 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
592 rsa->cipher.length = rsa_ctx->n.length;
593 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
595 case RTE_CRYPTO_ASYM_OP_DECRYPT:
596 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
597 rsa->message.length = rsa_ctx->n.length;
598 memcpy(rsa->message.data, req->rptr,
599 rsa->message.length);
601 /* Get length of decrypted output */
602 rsa->message.length = rte_cpu_to_be_16
603 (*((uint16_t *)req->rptr));
605 * Offset output data pointer by length field
606 * (2 bytes) and copy decrypted data.
608 memcpy(rsa->message.data, req->rptr + 2,
609 rsa->message.length);
612 case RTE_CRYPTO_ASYM_OP_SIGN:
613 rsa->sign.length = rsa_ctx->n.length;
614 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
616 case RTE_CRYPTO_ASYM_OP_VERIFY:
617 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
618 rsa->sign.length = rsa_ctx->n.length;
619 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
621 /* Get length of signed output */
622 rsa->sign.length = rte_cpu_to_be_16
623 (*((uint16_t *)req->rptr));
625 * Offset output data pointer by length field
626 * (2 bytes) and copy signed data.
628 memcpy(rsa->sign.data, req->rptr + 2,
631 if (memcmp(rsa->sign.data, rsa->message.data,
632 rsa->message.length)) {
633 CPT_LOG_DP_ERR("RSA verification failed");
634 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
638 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
639 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
645 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
646 struct cpt_request_info *req)
648 struct rte_crypto_asym_op *op = cop->asym;
649 struct cpt_asym_sess_misc *sess;
651 sess = get_asym_session_private_data(op->session,
652 otx2_cryptodev_driver_id);
654 switch (sess->xfrm_type) {
655 case RTE_CRYPTO_ASYM_XFORM_RSA:
656 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
658 case RTE_CRYPTO_ASYM_XFORM_MODEX:
659 op->modex.result.length = sess->mod_ctx.modulus.length;
660 memcpy(op->modex.result.data, req->rptr,
661 op->modex.result.length);
664 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
665 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
671 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
672 uintptr_t *rsp, uint8_t cc)
674 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
675 if (likely(cc == NO_ERR)) {
676 /* Verify authentication data if required */
677 if (unlikely(rsp[2]))
678 compl_auth_verify(cop, (uint8_t *)rsp[2],
681 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
683 if (cc == ERR_GC_ICV_MISCOMPARE)
684 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
686 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
689 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
690 sym_session_clear(otx2_cryptodev_driver_id,
692 rte_mempool_put(qp->sess_mp, cop->sym->session);
693 cop->sym->session = NULL;
697 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
698 if (likely(cc == NO_ERR)) {
699 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
701 * Pass cpt_req_info stored in metabuf during
704 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
705 otx2_cpt_asym_post_process(cop,
706 (struct cpt_request_info *)rsp);
708 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
712 static __rte_always_inline uint8_t
713 otx2_cpt_compcode_get(struct cpt_request_info *req)
715 volatile struct cpt_res_s_9s *res;
718 res = (volatile struct cpt_res_s_9s *)req->completion_addr;
720 if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
721 if (rte_get_timer_cycles() < req->time_out)
722 return ERR_REQ_PENDING;
724 CPT_LOG_DP_ERR("Request timed out");
725 return ERR_REQ_TIMEOUT;
728 if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
730 if (unlikely(res->uc_compcode)) {
731 ret = res->uc_compcode;
732 CPT_LOG_DP_DEBUG("Request failed with microcode error");
733 CPT_LOG_DP_DEBUG("MC completion code 0x%x",
737 CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
740 switch (res->compcode) {
741 case CPT_9X_COMP_E_INSTERR:
742 CPT_LOG_DP_ERR("Request failed with instruction error");
744 case CPT_9X_COMP_E_FAULT:
745 CPT_LOG_DP_ERR("Request failed with DMA fault");
747 case CPT_9X_COMP_E_HWERR:
748 CPT_LOG_DP_ERR("Request failed with hardware error");
751 CPT_LOG_DP_ERR("Request failed with unknown completion code");
759 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
761 int i, nb_pending, nb_completed;
762 struct otx2_cpt_qp *qp = qptr;
763 struct pending_queue *pend_q;
764 struct cpt_request_info *req;
765 struct rte_crypto_op *cop;
771 pend_q = &qp->pend_q;
773 nb_pending = pend_q->pending_count;
775 if (nb_ops > nb_pending)
778 for (i = 0; i < nb_ops; i++) {
779 rid = &pend_q->rid_queue[pend_q->deq_head];
780 req = (struct cpt_request_info *)(rid->rid);
782 cc[i] = otx2_cpt_compcode_get(req);
784 if (unlikely(cc[i] == ERR_REQ_PENDING))
789 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
790 pend_q->pending_count -= 1;
795 for (i = 0; i < nb_completed; i++) {
796 rsp = (void *)ops[i];
798 metabuf = (void *)rsp[0];
799 cop = (void *)rsp[1];
803 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
805 free_op_meta(metabuf, qp->meta_info.pool);
814 otx2_cpt_dev_config(struct rte_cryptodev *dev,
815 struct rte_cryptodev_config *conf)
817 struct otx2_cpt_vf *vf = dev->data->dev_private;
820 if (conf->nb_queue_pairs > vf->max_queues) {
821 CPT_LOG_ERR("Invalid number of queue pairs requested");
825 dev->feature_flags &= ~conf->ff_disable;
827 /* Unregister error interrupts */
828 if (vf->err_intr_registered)
829 otx2_cpt_err_intr_unregister(dev);
833 ret = otx2_cpt_queues_detach(dev);
835 CPT_LOG_ERR("Could not detach CPT queues");
841 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
843 CPT_LOG_ERR("Could not attach CPT queues");
847 ret = otx2_cpt_msix_offsets_get(dev);
849 CPT_LOG_ERR("Could not get MSI-X offsets");
853 /* Register error interrupts */
854 ret = otx2_cpt_err_intr_register(dev);
856 CPT_LOG_ERR("Could not register error interrupts");
860 dev->enqueue_burst = otx2_cpt_enqueue_burst;
861 dev->dequeue_burst = otx2_cpt_dequeue_burst;
867 otx2_cpt_queues_detach(dev);
872 otx2_cpt_dev_start(struct rte_cryptodev *dev)
876 CPT_PMD_INIT_FUNC_TRACE();
882 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
886 CPT_PMD_INIT_FUNC_TRACE();
890 otx2_cpt_dev_close(struct rte_cryptodev *dev)
892 struct otx2_cpt_vf *vf = dev->data->dev_private;
895 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
896 ret = otx2_cpt_queue_pair_release(dev, i);
901 /* Unregister error interrupts */
902 if (vf->err_intr_registered)
903 otx2_cpt_err_intr_unregister(dev);
907 ret = otx2_cpt_queues_detach(dev);
909 CPT_LOG_ERR("Could not detach CPT queues");
916 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
917 struct rte_cryptodev_info *info)
919 struct otx2_cpt_vf *vf = dev->data->dev_private;
922 info->max_nb_queue_pairs = vf->max_queues;
923 info->feature_flags = dev->feature_flags;
924 info->capabilities = otx2_cpt_capabilities_get();
925 info->sym.max_nb_sessions = 0;
926 info->driver_id = otx2_cryptodev_driver_id;
927 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
928 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
933 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
934 const struct rte_cryptodev_qp_conf *conf,
935 int socket_id __rte_unused)
937 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
938 struct rte_pci_device *pci_dev;
939 struct otx2_cpt_qp *qp;
941 CPT_PMD_INIT_FUNC_TRACE();
943 if (dev->data->queue_pairs[qp_id] != NULL)
944 otx2_cpt_queue_pair_release(dev, qp_id);
946 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
947 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
948 conf->nb_descriptors);
952 pci_dev = RTE_DEV_TO_PCI(dev->device);
954 if (pci_dev->mem_resource[2].addr == NULL) {
955 CPT_LOG_ERR("Invalid PCI mem address");
959 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
961 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
965 qp->sess_mp = conf->mp_session;
966 qp->sess_mp_priv = conf->mp_session_private;
967 dev->data->queue_pairs[qp_id] = qp;
973 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
975 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
978 CPT_PMD_INIT_FUNC_TRACE();
983 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
985 ret = otx2_cpt_qp_destroy(dev, qp);
987 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
991 dev->data->queue_pairs[qp_id] = NULL;
997 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
999 return cpt_get_session_size();
1003 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1004 struct rte_crypto_sym_xform *xform,
1005 struct rte_cryptodev_sym_session *sess,
1006 struct rte_mempool *pool)
1008 CPT_PMD_INIT_FUNC_TRACE();
1010 return sym_session_configure(dev->driver_id, xform, sess, pool);
1014 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1015 struct rte_cryptodev_sym_session *sess)
1017 CPT_PMD_INIT_FUNC_TRACE();
1019 return sym_session_clear(dev->driver_id, sess);
1023 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1025 return sizeof(struct cpt_asym_sess_misc);
1029 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1030 struct rte_crypto_asym_xform *xform,
1031 struct rte_cryptodev_asym_session *sess,
1032 struct rte_mempool *pool)
1034 struct cpt_asym_sess_misc *priv;
1037 CPT_PMD_INIT_FUNC_TRACE();
1039 if (rte_mempool_get(pool, (void **)&priv)) {
1040 CPT_LOG_ERR("Could not allocate session_private_data");
1044 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1046 ret = cpt_fill_asym_session_parameters(priv, xform);
1048 CPT_LOG_ERR("Could not configure session parameters");
1050 /* Return session to mempool */
1051 rte_mempool_put(pool, priv);
1055 set_asym_session_private_data(sess, dev->driver_id, priv);
1060 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1061 struct rte_cryptodev_asym_session *sess)
1063 struct cpt_asym_sess_misc *priv;
1064 struct rte_mempool *sess_mp;
1066 CPT_PMD_INIT_FUNC_TRACE();
1068 priv = get_asym_session_private_data(sess, dev->driver_id);
1072 /* Free resources allocated in session_cfg */
1073 cpt_free_asym_session_parameters(priv);
1075 /* Reset and free object back to pool */
1076 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1077 sess_mp = rte_mempool_from_obj(priv);
1078 set_asym_session_private_data(sess, dev->driver_id, NULL);
1079 rte_mempool_put(sess_mp, priv);
1082 struct rte_cryptodev_ops otx2_cpt_ops = {
1083 /* Device control ops */
1084 .dev_configure = otx2_cpt_dev_config,
1085 .dev_start = otx2_cpt_dev_start,
1086 .dev_stop = otx2_cpt_dev_stop,
1087 .dev_close = otx2_cpt_dev_close,
1088 .dev_infos_get = otx2_cpt_dev_info_get,
1091 .stats_reset = NULL,
1092 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1093 .queue_pair_release = otx2_cpt_queue_pair_release,
1094 .queue_pair_count = NULL,
1096 /* Symmetric crypto ops */
1097 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1098 .sym_session_configure = otx2_cpt_sym_session_configure,
1099 .sym_session_clear = otx2_cpt_sym_session_clear,
1101 /* Asymmetric crypto ops */
1102 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1103 .asym_session_configure = otx2_cpt_asym_session_cfg,
1104 .asym_session_clear = otx2_cpt_asym_session_clear,