1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
11 #include "otx2_cryptodev.h"
12 #include "otx2_cryptodev_capabilities.h"
13 #include "otx2_cryptodev_hw_access.h"
14 #include "otx2_cryptodev_mbox.h"
15 #include "otx2_cryptodev_ops.h"
16 #include "otx2_mbox.h"
17 #include "otx2_sec_idev.h"
19 #include "cpt_hw_types.h"
20 #include "cpt_pmd_logs.h"
21 #include "cpt_pmd_ops_helper.h"
22 #include "cpt_ucode.h"
23 #include "cpt_ucode_asym.h"
25 #define METABUF_POOL_CACHE_SIZE 512
27 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
29 /* Forward declarations */
32 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
35 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
37 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
41 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
42 struct otx2_cpt_qp *qp, uint8_t qp_id,
45 char mempool_name[RTE_MEMPOOL_NAMESIZE];
46 struct cpt_qp_meta_info *meta_info;
47 struct rte_mempool *pool;
53 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
55 /* Get meta len for scatter gather mode */
56 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
58 /* Extra 32B saved for future considerations */
59 sg_mlen += 4 * sizeof(uint64_t);
61 /* Get meta len for linear buffer (direct) mode */
62 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
64 /* Extra 32B saved for future considerations */
65 lb_mlen += 4 * sizeof(uint64_t);
68 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
70 /* Get meta len required for asymmetric operations */
71 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
75 * Check max requirement for meta buffer to
76 * support crypto op of any type (sym/asym).
78 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
80 /* Allocate mempool */
82 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
83 dev->data->dev_id, qp_id);
85 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
86 METABUF_POOL_CACHE_SIZE, 0,
90 CPT_LOG_ERR("Could not create mempool for metabuf");
94 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
97 CPT_LOG_ERR("Could not set mempool ops");
101 ret = rte_mempool_populate_default(pool);
103 CPT_LOG_ERR("Could not populate metabuf pool");
107 meta_info = &qp->meta_info;
109 meta_info->pool = pool;
110 meta_info->lb_mlen = lb_mlen;
111 meta_info->sg_mlen = sg_mlen;
116 rte_mempool_free(pool);
121 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
123 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
125 rte_mempool_free(meta_info->pool);
127 meta_info->pool = NULL;
128 meta_info->lb_mlen = 0;
129 meta_info->sg_mlen = 0;
133 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
135 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
136 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
139 for (i = 0; i < nb_ethport; i++) {
140 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
141 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
148 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
152 /* Publish inline Tx QP to eth dev security */
153 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
160 static struct otx2_cpt_qp *
161 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
164 struct otx2_cpt_vf *vf = dev->data->dev_private;
165 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
166 const struct rte_memzone *lf_mem;
167 uint32_t len, iq_len, size_div40;
168 char name[RTE_MEMZONE_NAMESIZE];
169 uint64_t used_len, iova;
170 struct otx2_cpt_qp *qp;
175 /* Allocate queue pair */
176 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
179 CPT_LOG_ERR("Could not allocate queue pair");
183 iq_len = OTX2_CPT_IQ_LEN;
186 * Queue size must be a multiple of 40 and effective queue size to
187 * software is (size_div40 - 1) * 40
189 size_div40 = (iq_len + 40 - 1) / 40 + 1;
191 /* For pending queue */
192 len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
194 /* Space for instruction group memory */
195 len += size_div40 * 16;
197 /* So that instruction queues start as pg size aligned */
198 len = RTE_ALIGN(len, pg_sz);
200 /* For instruction queues */
201 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
203 /* Wastage after instruction queues */
204 len = RTE_ALIGN(len, pg_sz);
206 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
209 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
210 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
211 RTE_CACHE_LINE_SIZE);
212 if (lf_mem == NULL) {
213 CPT_LOG_ERR("Could not allocate reserved memzone");
222 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
224 CPT_LOG_ERR("Could not create mempool for metabuf");
228 /* Initialize pending queue */
229 qp->pend_q.rid_queue = (struct rid *)va;
230 qp->pend_q.enq_tail = 0;
231 qp->pend_q.deq_head = 0;
232 qp->pend_q.pending_count = 0;
234 used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
235 used_len += size_div40 * 16;
236 used_len = RTE_ALIGN(used_len, pg_sz);
239 qp->iq_dma_addr = iova;
241 qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
243 lmtline = vf->otx2_dev.bar2 +
244 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
245 OTX2_LMT_LF_LMTLINE(0);
247 qp->lmtline = (void *)lmtline;
249 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
251 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
252 if (ret && (ret != -ENOENT)) {
253 CPT_LOG_ERR("Could not delete inline configuration");
254 goto mempool_destroy;
257 otx2_cpt_iq_disable(qp);
259 ret = otx2_cpt_qp_inline_cfg(dev, qp);
261 CPT_LOG_ERR("Could not configure queue for inline IPsec");
262 goto mempool_destroy;
265 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
268 CPT_LOG_ERR("Could not enable instruction queue");
269 goto mempool_destroy;
275 otx2_cpt_metabuf_mempool_destroy(qp);
277 rte_memzone_free(lf_mem);
284 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
286 const struct rte_memzone *lf_mem;
287 char name[RTE_MEMZONE_NAMESIZE];
290 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
291 if (ret && (ret != -ENOENT)) {
292 CPT_LOG_ERR("Could not delete inline configuration");
296 otx2_cpt_iq_disable(qp);
298 otx2_cpt_metabuf_mempool_destroy(qp);
300 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
303 lf_mem = rte_memzone_lookup(name);
305 ret = rte_memzone_free(lf_mem);
315 sym_xform_verify(struct rte_crypto_sym_xform *xform)
318 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
319 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
320 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
323 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
324 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
325 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
328 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
329 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
330 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
331 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
334 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
335 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
336 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
337 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
341 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
342 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
343 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
350 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
351 struct rte_cryptodev_sym_session *sess,
352 struct rte_mempool *pool)
354 struct cpt_sess_misc *misc;
358 ret = sym_xform_verify(xform);
362 if (unlikely(rte_mempool_get(pool, &priv))) {
363 CPT_LOG_ERR("Could not allocate session private data");
369 for ( ; xform != NULL; xform = xform->next) {
370 switch (xform->type) {
371 case RTE_CRYPTO_SYM_XFORM_AEAD:
372 ret = fill_sess_aead(xform, misc);
374 case RTE_CRYPTO_SYM_XFORM_CIPHER:
375 ret = fill_sess_cipher(xform, misc);
377 case RTE_CRYPTO_SYM_XFORM_AUTH:
378 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
379 ret = fill_sess_gmac(xform, misc);
381 ret = fill_sess_auth(xform, misc);
391 set_sym_session_private_data(sess, driver_id, misc);
393 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
394 sizeof(struct cpt_sess_misc);
397 * IE engines support IPsec operations
398 * SE engines support IPsec operations and Air-Crypto operations
401 misc->egrp = OTX2_CPT_EGRP_SE;
403 misc->egrp = OTX2_CPT_EGRP_SE_IE;
408 rte_mempool_put(pool, priv);
414 sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
416 void *priv = get_sym_session_private_data(sess, driver_id);
417 struct rte_mempool *pool;
422 memset(priv, 0, cpt_get_session_size());
424 pool = rte_mempool_from_obj(priv);
426 set_sym_session_private_data(sess, driver_id, NULL);
428 rte_mempool_put(pool, priv);
431 static __rte_always_inline int32_t __rte_hot
432 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
433 struct pending_queue *pend_q,
434 struct cpt_request_info *req)
436 void *lmtline = qp->lmtline;
437 union cpt_inst_s inst;
440 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
444 inst.s9x.res_addr = req->comp_baddr;
448 inst.s9x.ei0 = req->ist.ei0;
449 inst.s9x.ei1 = req->ist.ei1;
450 inst.s9x.ei2 = req->ist.ei2;
451 inst.s9x.ei3 = req->ist.ei3;
453 req->time_out = rte_get_timer_cycles() +
454 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
457 /* Copy CPT command to LMTLINE */
458 memcpy(lmtline, &inst, sizeof(inst));
461 * Make sure compiler does not reorder memcpy and ldeor.
462 * LMTST transactions are always flushed from the write
463 * buffer immediately, a DMB is not required to push out
467 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
468 } while (lmt_status == 0);
470 pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
472 /* We will use soft queue length here to limit requests */
473 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
474 pend_q->pending_count += 1;
479 static __rte_always_inline int32_t __rte_hot
480 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
481 struct rte_crypto_op *op,
482 struct pending_queue *pend_q)
484 struct cpt_qp_meta_info *minfo = &qp->meta_info;
485 struct rte_crypto_asym_op *asym_op = op->asym;
486 struct asym_op_params params = {0};
487 struct cpt_asym_sess_misc *sess;
493 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
494 CPT_LOG_ERR("Could not allocate meta buffer for request");
498 sess = get_asym_session_private_data(asym_op->session,
499 otx2_cryptodev_driver_id);
501 /* Store IO address of the mdata to meta_buf */
502 params.meta_buf = rte_mempool_virt2iova(mdata);
505 cop[0] = (uintptr_t)mdata;
506 cop[1] = (uintptr_t)op;
507 cop[2] = cop[3] = 0ULL;
509 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
510 params.req->op = cop;
512 /* Adjust meta_buf to point to end of cpt_request_info structure */
513 params.meta_buf += (4 * sizeof(uintptr_t)) +
514 sizeof(struct cpt_request_info);
515 switch (sess->xfrm_type) {
516 case RTE_CRYPTO_ASYM_XFORM_MODEX:
517 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
521 case RTE_CRYPTO_ASYM_XFORM_RSA:
522 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
526 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
527 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
531 case RTE_CRYPTO_ASYM_XFORM_ECPM:
532 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
533 sess->ec_ctx.curveid);
538 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
543 /* Set engine group of AE */
544 w3 = (vq_cmd_word3_t *)¶ms.req->ist.ei3;
545 w3->s.grp = OTX2_CPT_EGRP_AE;
547 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req);
550 CPT_LOG_DP_ERR("Could not enqueue crypto req");
557 free_op_meta(mdata, minfo->pool);
562 static __rte_always_inline int __rte_hot
563 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
564 struct pending_queue *pend_q)
566 struct rte_crypto_sym_op *sym_op = op->sym;
567 struct cpt_request_info *req;
568 struct cpt_sess_misc *sess;
574 sess = get_sym_session_private_data(sym_op->session,
575 otx2_cryptodev_driver_id);
577 cpt_op = sess->cpt_op;
579 if (cpt_op & CPT_OP_CIPHER_MASK)
580 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
583 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
587 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
588 op, (unsigned int)cpt_op, ret);
592 w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
593 w3->s.grp = sess->egrp;
595 ret = otx2_cpt_enqueue_req(qp, pend_q, req);
598 /* Free buffer allocated by fill params routines */
599 free_op_meta(mdata, qp->meta_info.pool);
605 static __rte_always_inline int __rte_hot
606 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
607 struct pending_queue *pend_q)
609 const int driver_id = otx2_cryptodev_driver_id;
610 struct rte_crypto_sym_op *sym_op = op->sym;
611 struct rte_cryptodev_sym_session *sess;
614 /* Create temporary session */
616 if (rte_mempool_get(qp->sess_mp, (void **)&sess))
619 ret = sym_session_configure(driver_id, sym_op->xform, sess,
624 sym_op->session = sess;
626 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
634 sym_session_clear(driver_id, sess);
636 rte_mempool_put(qp->sess_mp, sess);
641 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
643 uint16_t nb_allowed, count = 0;
644 struct otx2_cpt_qp *qp = qptr;
645 struct pending_queue *pend_q;
646 struct rte_crypto_op *op;
649 pend_q = &qp->pend_q;
651 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
652 if (nb_ops > nb_allowed)
655 for (count = 0; count < nb_ops; count++) {
657 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
658 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
659 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
661 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
663 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
664 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
665 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
678 static __rte_always_inline void
679 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
680 struct rte_crypto_rsa_xform *rsa_ctx)
682 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
684 switch (rsa->op_type) {
685 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
686 rsa->cipher.length = rsa_ctx->n.length;
687 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
689 case RTE_CRYPTO_ASYM_OP_DECRYPT:
690 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
691 rsa->message.length = rsa_ctx->n.length;
692 memcpy(rsa->message.data, req->rptr,
693 rsa->message.length);
695 /* Get length of decrypted output */
696 rsa->message.length = rte_cpu_to_be_16
697 (*((uint16_t *)req->rptr));
699 * Offset output data pointer by length field
700 * (2 bytes) and copy decrypted data.
702 memcpy(rsa->message.data, req->rptr + 2,
703 rsa->message.length);
706 case RTE_CRYPTO_ASYM_OP_SIGN:
707 rsa->sign.length = rsa_ctx->n.length;
708 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
710 case RTE_CRYPTO_ASYM_OP_VERIFY:
711 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
712 rsa->sign.length = rsa_ctx->n.length;
713 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
715 /* Get length of signed output */
716 rsa->sign.length = rte_cpu_to_be_16
717 (*((uint16_t *)req->rptr));
719 * Offset output data pointer by length field
720 * (2 bytes) and copy signed data.
722 memcpy(rsa->sign.data, req->rptr + 2,
725 if (memcmp(rsa->sign.data, rsa->message.data,
726 rsa->message.length)) {
727 CPT_LOG_DP_ERR("RSA verification failed");
728 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
732 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
733 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
738 static __rte_always_inline void
739 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
740 struct cpt_request_info *req,
741 struct cpt_asym_ec_ctx *ec)
743 int prime_len = ec_grp[ec->curveid].prime.length;
745 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
748 /* Separate out sign r and s components */
749 memcpy(ecdsa->r.data, req->rptr, prime_len);
750 memcpy(ecdsa->s.data, req->rptr + ROUNDUP8(prime_len), prime_len);
751 ecdsa->r.length = prime_len;
752 ecdsa->s.length = prime_len;
755 static __rte_always_inline void
756 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
757 struct cpt_request_info *req,
758 struct cpt_asym_ec_ctx *ec)
760 int prime_len = ec_grp[ec->curveid].prime.length;
762 memcpy(ecpm->r.x.data, req->rptr, prime_len);
763 memcpy(ecpm->r.y.data, req->rptr + ROUNDUP8(prime_len), prime_len);
764 ecpm->r.x.length = prime_len;
765 ecpm->r.y.length = prime_len;
769 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
770 struct cpt_request_info *req)
772 struct rte_crypto_asym_op *op = cop->asym;
773 struct cpt_asym_sess_misc *sess;
775 sess = get_asym_session_private_data(op->session,
776 otx2_cryptodev_driver_id);
778 switch (sess->xfrm_type) {
779 case RTE_CRYPTO_ASYM_XFORM_RSA:
780 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
782 case RTE_CRYPTO_ASYM_XFORM_MODEX:
783 op->modex.result.length = sess->mod_ctx.modulus.length;
784 memcpy(op->modex.result.data, req->rptr,
785 op->modex.result.length);
787 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
788 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
790 case RTE_CRYPTO_ASYM_XFORM_ECPM:
791 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
794 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
795 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
801 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
802 uintptr_t *rsp, uint8_t cc)
804 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
805 if (likely(cc == NO_ERR)) {
806 /* Verify authentication data if required */
807 if (unlikely(rsp[2]))
808 compl_auth_verify(cop, (uint8_t *)rsp[2],
811 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
813 if (cc == ERR_GC_ICV_MISCOMPARE)
814 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
816 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
819 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
820 sym_session_clear(otx2_cryptodev_driver_id,
822 rte_mempool_put(qp->sess_mp, cop->sym->session);
823 cop->sym->session = NULL;
827 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
828 if (likely(cc == NO_ERR)) {
829 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
831 * Pass cpt_req_info stored in metabuf during
834 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
835 otx2_cpt_asym_post_process(cop,
836 (struct cpt_request_info *)rsp);
838 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
842 static __rte_always_inline uint8_t
843 otx2_cpt_compcode_get(struct cpt_request_info *req)
845 volatile struct cpt_res_s_9s *res;
848 res = (volatile struct cpt_res_s_9s *)req->completion_addr;
850 if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
851 if (rte_get_timer_cycles() < req->time_out)
852 return ERR_REQ_PENDING;
854 CPT_LOG_DP_ERR("Request timed out");
855 return ERR_REQ_TIMEOUT;
858 if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
860 if (unlikely(res->uc_compcode)) {
861 ret = res->uc_compcode;
862 CPT_LOG_DP_DEBUG("Request failed with microcode error");
863 CPT_LOG_DP_DEBUG("MC completion code 0x%x",
867 CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
870 switch (res->compcode) {
871 case CPT_9X_COMP_E_INSTERR:
872 CPT_LOG_DP_ERR("Request failed with instruction error");
874 case CPT_9X_COMP_E_FAULT:
875 CPT_LOG_DP_ERR("Request failed with DMA fault");
877 case CPT_9X_COMP_E_HWERR:
878 CPT_LOG_DP_ERR("Request failed with hardware error");
881 CPT_LOG_DP_ERR("Request failed with unknown completion code");
889 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
891 int i, nb_pending, nb_completed;
892 struct otx2_cpt_qp *qp = qptr;
893 struct pending_queue *pend_q;
894 struct cpt_request_info *req;
895 struct rte_crypto_op *cop;
901 pend_q = &qp->pend_q;
903 nb_pending = pend_q->pending_count;
905 if (nb_ops > nb_pending)
908 for (i = 0; i < nb_ops; i++) {
909 rid = &pend_q->rid_queue[pend_q->deq_head];
910 req = (struct cpt_request_info *)(rid->rid);
912 cc[i] = otx2_cpt_compcode_get(req);
914 if (unlikely(cc[i] == ERR_REQ_PENDING))
919 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
920 pend_q->pending_count -= 1;
925 for (i = 0; i < nb_completed; i++) {
926 rsp = (void *)ops[i];
928 metabuf = (void *)rsp[0];
929 cop = (void *)rsp[1];
933 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
935 free_op_meta(metabuf, qp->meta_info.pool);
944 otx2_cpt_dev_config(struct rte_cryptodev *dev,
945 struct rte_cryptodev_config *conf)
947 struct otx2_cpt_vf *vf = dev->data->dev_private;
950 if (conf->nb_queue_pairs > vf->max_queues) {
951 CPT_LOG_ERR("Invalid number of queue pairs requested");
955 dev->feature_flags &= ~conf->ff_disable;
957 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
958 /* Initialize shared FPM table */
959 ret = cpt_fpm_init(otx2_fpm_iova);
964 /* Unregister error interrupts */
965 if (vf->err_intr_registered)
966 otx2_cpt_err_intr_unregister(dev);
970 ret = otx2_cpt_queues_detach(dev);
972 CPT_LOG_ERR("Could not detach CPT queues");
978 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
980 CPT_LOG_ERR("Could not attach CPT queues");
984 ret = otx2_cpt_msix_offsets_get(dev);
986 CPT_LOG_ERR("Could not get MSI-X offsets");
990 /* Register error interrupts */
991 ret = otx2_cpt_err_intr_register(dev);
993 CPT_LOG_ERR("Could not register error interrupts");
997 ret = otx2_cpt_inline_init(dev);
999 CPT_LOG_ERR("Could not enable inline IPsec");
1000 goto intr_unregister;
1003 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1004 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1010 otx2_cpt_err_intr_unregister(dev);
1012 otx2_cpt_queues_detach(dev);
1017 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1021 CPT_PMD_INIT_FUNC_TRACE();
1027 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1029 CPT_PMD_INIT_FUNC_TRACE();
1031 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1036 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1038 struct otx2_cpt_vf *vf = dev->data->dev_private;
1041 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1042 ret = otx2_cpt_queue_pair_release(dev, i);
1047 /* Unregister error interrupts */
1048 if (vf->err_intr_registered)
1049 otx2_cpt_err_intr_unregister(dev);
1052 if (vf->nb_queues) {
1053 ret = otx2_cpt_queues_detach(dev);
1055 CPT_LOG_ERR("Could not detach CPT queues");
1062 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1063 struct rte_cryptodev_info *info)
1065 struct otx2_cpt_vf *vf = dev->data->dev_private;
1068 info->max_nb_queue_pairs = vf->max_queues;
1069 info->feature_flags = dev->feature_flags;
1070 info->capabilities = otx2_cpt_capabilities_get();
1071 info->sym.max_nb_sessions = 0;
1072 info->driver_id = otx2_cryptodev_driver_id;
1073 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1074 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1079 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1080 const struct rte_cryptodev_qp_conf *conf,
1081 int socket_id __rte_unused)
1083 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1084 struct rte_pci_device *pci_dev;
1085 struct otx2_cpt_qp *qp;
1087 CPT_PMD_INIT_FUNC_TRACE();
1089 if (dev->data->queue_pairs[qp_id] != NULL)
1090 otx2_cpt_queue_pair_release(dev, qp_id);
1092 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1093 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1094 conf->nb_descriptors);
1098 pci_dev = RTE_DEV_TO_PCI(dev->device);
1100 if (pci_dev->mem_resource[2].addr == NULL) {
1101 CPT_LOG_ERR("Invalid PCI mem address");
1105 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1107 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1111 qp->sess_mp = conf->mp_session;
1112 qp->sess_mp_priv = conf->mp_session_private;
1113 dev->data->queue_pairs[qp_id] = qp;
1119 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1121 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1124 CPT_PMD_INIT_FUNC_TRACE();
1129 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1131 ret = otx2_cpt_qp_destroy(dev, qp);
1133 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1137 dev->data->queue_pairs[qp_id] = NULL;
1143 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1145 return cpt_get_session_size();
1149 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1150 struct rte_crypto_sym_xform *xform,
1151 struct rte_cryptodev_sym_session *sess,
1152 struct rte_mempool *pool)
1154 CPT_PMD_INIT_FUNC_TRACE();
1156 return sym_session_configure(dev->driver_id, xform, sess, pool);
1160 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1161 struct rte_cryptodev_sym_session *sess)
1163 CPT_PMD_INIT_FUNC_TRACE();
1165 return sym_session_clear(dev->driver_id, sess);
1169 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1171 return sizeof(struct cpt_asym_sess_misc);
1175 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1176 struct rte_crypto_asym_xform *xform,
1177 struct rte_cryptodev_asym_session *sess,
1178 struct rte_mempool *pool)
1180 struct cpt_asym_sess_misc *priv;
1183 CPT_PMD_INIT_FUNC_TRACE();
1185 if (rte_mempool_get(pool, (void **)&priv)) {
1186 CPT_LOG_ERR("Could not allocate session_private_data");
1190 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1192 ret = cpt_fill_asym_session_parameters(priv, xform);
1194 CPT_LOG_ERR("Could not configure session parameters");
1196 /* Return session to mempool */
1197 rte_mempool_put(pool, priv);
1201 set_asym_session_private_data(sess, dev->driver_id, priv);
1206 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1207 struct rte_cryptodev_asym_session *sess)
1209 struct cpt_asym_sess_misc *priv;
1210 struct rte_mempool *sess_mp;
1212 CPT_PMD_INIT_FUNC_TRACE();
1214 priv = get_asym_session_private_data(sess, dev->driver_id);
1218 /* Free resources allocated in session_cfg */
1219 cpt_free_asym_session_parameters(priv);
1221 /* Reset and free object back to pool */
1222 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1223 sess_mp = rte_mempool_from_obj(priv);
1224 set_asym_session_private_data(sess, dev->driver_id, NULL);
1225 rte_mempool_put(sess_mp, priv);
1228 struct rte_cryptodev_ops otx2_cpt_ops = {
1229 /* Device control ops */
1230 .dev_configure = otx2_cpt_dev_config,
1231 .dev_start = otx2_cpt_dev_start,
1232 .dev_stop = otx2_cpt_dev_stop,
1233 .dev_close = otx2_cpt_dev_close,
1234 .dev_infos_get = otx2_cpt_dev_info_get,
1237 .stats_reset = NULL,
1238 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1239 .queue_pair_release = otx2_cpt_queue_pair_release,
1241 /* Symmetric crypto ops */
1242 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1243 .sym_session_configure = otx2_cpt_sym_session_configure,
1244 .sym_session_clear = otx2_cpt_sym_session_clear,
1246 /* Asymmetric crypto ops */
1247 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1248 .asym_session_configure = otx2_cpt_asym_session_cfg,
1249 .asym_session_clear = otx2_cpt_asym_session_clear,