1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
11 #include "otx2_cryptodev.h"
12 #include "otx2_cryptodev_capabilities.h"
13 #include "otx2_cryptodev_hw_access.h"
14 #include "otx2_cryptodev_mbox.h"
15 #include "otx2_cryptodev_ops.h"
16 #include "otx2_cryptodev_ops_helper.h"
17 #include "otx2_ipsec_anti_replay.h"
18 #include "otx2_ipsec_po_ops.h"
19 #include "otx2_mbox.h"
20 #include "otx2_sec_idev.h"
21 #include "otx2_security.h"
23 #include "cpt_hw_types.h"
24 #include "cpt_pmd_logs.h"
25 #include "cpt_pmd_ops_helper.h"
26 #include "cpt_ucode.h"
27 #include "cpt_ucode_asym.h"
29 #define METABUF_POOL_CACHE_SIZE 512
31 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
33 /* Forward declarations */
36 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
39 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
41 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
45 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
46 struct otx2_cpt_qp *qp, uint8_t qp_id,
49 char mempool_name[RTE_MEMPOOL_NAMESIZE];
50 struct cpt_qp_meta_info *meta_info;
51 struct rte_mempool *pool;
57 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
59 /* Get meta len for scatter gather mode */
60 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
62 /* Extra 32B saved for future considerations */
63 sg_mlen += 4 * sizeof(uint64_t);
65 /* Get meta len for linear buffer (direct) mode */
66 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
68 /* Extra 32B saved for future considerations */
69 lb_mlen += 4 * sizeof(uint64_t);
72 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
74 /* Get meta len required for asymmetric operations */
75 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
79 * Check max requirement for meta buffer to
80 * support crypto op of any type (sym/asym).
82 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
84 /* Allocate mempool */
86 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
87 dev->data->dev_id, qp_id);
89 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
90 METABUF_POOL_CACHE_SIZE, 0,
94 CPT_LOG_ERR("Could not create mempool for metabuf");
98 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
101 CPT_LOG_ERR("Could not set mempool ops");
105 ret = rte_mempool_populate_default(pool);
107 CPT_LOG_ERR("Could not populate metabuf pool");
111 meta_info = &qp->meta_info;
113 meta_info->pool = pool;
114 meta_info->lb_mlen = lb_mlen;
115 meta_info->sg_mlen = sg_mlen;
120 rte_mempool_free(pool);
125 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
127 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
129 rte_mempool_free(meta_info->pool);
131 meta_info->pool = NULL;
132 meta_info->lb_mlen = 0;
133 meta_info->sg_mlen = 0;
137 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
139 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
140 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
143 for (i = 0; i < nb_ethport; i++) {
144 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
145 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
152 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
156 /* Publish inline Tx QP to eth dev security */
157 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
164 static struct otx2_cpt_qp *
165 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
168 struct otx2_cpt_vf *vf = dev->data->dev_private;
169 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
170 const struct rte_memzone *lf_mem;
171 uint32_t len, iq_len, size_div40;
172 char name[RTE_MEMZONE_NAMESIZE];
173 uint64_t used_len, iova;
174 struct otx2_cpt_qp *qp;
179 /* Allocate queue pair */
180 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
183 CPT_LOG_ERR("Could not allocate queue pair");
187 iq_len = OTX2_CPT_IQ_LEN;
190 * Queue size must be a multiple of 40 and effective queue size to
191 * software is (size_div40 - 1) * 40
193 size_div40 = (iq_len + 40 - 1) / 40 + 1;
195 /* For pending queue */
196 len = iq_len * sizeof(uintptr_t);
198 /* Space for instruction group memory */
199 len += size_div40 * 16;
201 /* So that instruction queues start as pg size aligned */
202 len = RTE_ALIGN(len, pg_sz);
204 /* For instruction queues */
205 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
207 /* Wastage after instruction queues */
208 len = RTE_ALIGN(len, pg_sz);
210 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
213 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
214 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
215 RTE_CACHE_LINE_SIZE);
216 if (lf_mem == NULL) {
217 CPT_LOG_ERR("Could not allocate reserved memzone");
226 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
228 CPT_LOG_ERR("Could not create mempool for metabuf");
232 /* Initialize pending queue */
233 qp->pend_q.req_queue = (uintptr_t *)va;
234 qp->pend_q.enq_tail = 0;
235 qp->pend_q.deq_head = 0;
236 qp->pend_q.pending_count = 0;
238 used_len = iq_len * sizeof(uintptr_t);
239 used_len += size_div40 * 16;
240 used_len = RTE_ALIGN(used_len, pg_sz);
243 qp->iq_dma_addr = iova;
245 qp->blkaddr = vf->lf_blkaddr[qp_id];
246 qp->base = OTX2_CPT_LF_BAR2(vf, qp->blkaddr, qp_id);
248 lmtline = vf->otx2_dev.bar2 +
249 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
250 OTX2_LMT_LF_LMTLINE(0);
252 qp->lmtline = (void *)lmtline;
254 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
256 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
257 if (ret && (ret != -ENOENT)) {
258 CPT_LOG_ERR("Could not delete inline configuration");
259 goto mempool_destroy;
262 otx2_cpt_iq_disable(qp);
264 ret = otx2_cpt_qp_inline_cfg(dev, qp);
266 CPT_LOG_ERR("Could not configure queue for inline IPsec");
267 goto mempool_destroy;
270 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
273 CPT_LOG_ERR("Could not enable instruction queue");
274 goto mempool_destroy;
280 otx2_cpt_metabuf_mempool_destroy(qp);
282 rte_memzone_free(lf_mem);
289 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
291 const struct rte_memzone *lf_mem;
292 char name[RTE_MEMZONE_NAMESIZE];
295 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
296 if (ret && (ret != -ENOENT)) {
297 CPT_LOG_ERR("Could not delete inline configuration");
301 otx2_cpt_iq_disable(qp);
303 otx2_cpt_metabuf_mempool_destroy(qp);
305 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
308 lf_mem = rte_memzone_lookup(name);
310 ret = rte_memzone_free(lf_mem);
320 sym_xform_verify(struct rte_crypto_sym_xform *xform)
323 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
324 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
325 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
328 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
329 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
330 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
333 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
334 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
335 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
336 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
339 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
340 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
341 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
342 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
346 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
347 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
348 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
355 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
356 struct rte_cryptodev_sym_session *sess,
357 struct rte_mempool *pool)
359 struct rte_crypto_sym_xform *temp_xform = xform;
360 struct cpt_sess_misc *misc;
361 vq_cmd_word3_t vq_cmd_w3;
365 ret = sym_xform_verify(xform);
369 if (unlikely(rte_mempool_get(pool, &priv))) {
370 CPT_LOG_ERR("Could not allocate session private data");
374 memset(priv, 0, sizeof(struct cpt_sess_misc) +
375 offsetof(struct cpt_ctx, mc_ctx));
379 for ( ; xform != NULL; xform = xform->next) {
380 switch (xform->type) {
381 case RTE_CRYPTO_SYM_XFORM_AEAD:
382 ret = fill_sess_aead(xform, misc);
384 case RTE_CRYPTO_SYM_XFORM_CIPHER:
385 ret = fill_sess_cipher(xform, misc);
387 case RTE_CRYPTO_SYM_XFORM_AUTH:
388 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
389 ret = fill_sess_gmac(xform, misc);
391 ret = fill_sess_auth(xform, misc);
401 if ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&
402 cpt_mac_len_verify(&temp_xform->auth)) {
403 CPT_LOG_ERR("MAC length is not supported");
408 set_sym_session_private_data(sess, driver_id, misc);
410 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
411 sizeof(struct cpt_sess_misc);
414 vq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,
418 * IE engines support IPsec operations
419 * SE engines support IPsec operations, Chacha-Poly and
420 * Air-Crypto operations
422 if (misc->zsk_flag || misc->chacha_poly)
423 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;
425 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;
427 misc->cpt_inst_w7 = vq_cmd_w3.u64;
432 rte_mempool_put(pool, priv);
437 static __rte_always_inline void __rte_hot
438 otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,
439 struct cpt_request_info *req,
441 uint64_t cpt_inst_w7)
443 union cpt_inst_s inst;
447 inst.s9x.res_addr = req->comp_baddr;
451 inst.s9x.ei0 = req->ist.ei0;
452 inst.s9x.ei1 = req->ist.ei1;
453 inst.s9x.ei2 = req->ist.ei2;
454 inst.s9x.ei3 = cpt_inst_w7;
457 inst.s9x.grp = qp->ev.queue_id;
458 inst.s9x.tt = qp->ev.sched_type;
459 inst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |
461 inst.s9x.wq_ptr = (uint64_t)req >> 3;
465 /* Copy CPT command to LMTLINE */
466 memcpy(lmtline, &inst, sizeof(inst));
469 * Make sure compiler does not reorder memcpy and ldeor.
470 * LMTST transactions are always flushed from the write
471 * buffer immediately, a DMB is not required to push out
475 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
476 } while (lmt_status == 0);
480 static __rte_always_inline int32_t __rte_hot
481 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
482 struct pending_queue *pend_q,
483 struct cpt_request_info *req,
484 uint64_t cpt_inst_w7)
486 void *lmtline = qp->lmtline;
487 union cpt_inst_s inst;
491 otx2_ca_enqueue_req(qp, req, lmtline, cpt_inst_w7);
495 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
499 inst.s9x.res_addr = req->comp_baddr;
503 inst.s9x.ei0 = req->ist.ei0;
504 inst.s9x.ei1 = req->ist.ei1;
505 inst.s9x.ei2 = req->ist.ei2;
506 inst.s9x.ei3 = cpt_inst_w7;
508 req->time_out = rte_get_timer_cycles() +
509 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
512 /* Copy CPT command to LMTLINE */
513 memcpy(lmtline, &inst, sizeof(inst));
516 * Make sure compiler does not reorder memcpy and ldeor.
517 * LMTST transactions are always flushed from the write
518 * buffer immediately, a DMB is not required to push out
522 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
523 } while (lmt_status == 0);
525 pend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;
527 /* We will use soft queue length here to limit requests */
528 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
529 pend_q->pending_count += 1;
534 static __rte_always_inline int32_t __rte_hot
535 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
536 struct rte_crypto_op *op,
537 struct pending_queue *pend_q)
539 struct cpt_qp_meta_info *minfo = &qp->meta_info;
540 struct rte_crypto_asym_op *asym_op = op->asym;
541 struct asym_op_params params = {0};
542 struct cpt_asym_sess_misc *sess;
547 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
548 CPT_LOG_ERR("Could not allocate meta buffer for request");
552 sess = get_asym_session_private_data(asym_op->session,
553 otx2_cryptodev_driver_id);
555 /* Store IO address of the mdata to meta_buf */
556 params.meta_buf = rte_mempool_virt2iova(mdata);
559 cop[0] = (uintptr_t)mdata;
560 cop[1] = (uintptr_t)op;
561 cop[2] = cop[3] = 0ULL;
563 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
564 params.req->op = cop;
566 /* Adjust meta_buf to point to end of cpt_request_info structure */
567 params.meta_buf += (4 * sizeof(uintptr_t)) +
568 sizeof(struct cpt_request_info);
569 switch (sess->xfrm_type) {
570 case RTE_CRYPTO_ASYM_XFORM_MODEX:
571 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
575 case RTE_CRYPTO_ASYM_XFORM_RSA:
576 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
580 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
581 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
585 case RTE_CRYPTO_ASYM_XFORM_ECPM:
586 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
587 sess->ec_ctx.curveid);
592 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
597 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req, sess->cpt_inst_w7);
600 CPT_LOG_DP_ERR("Could not enqueue crypto req");
607 free_op_meta(mdata, minfo->pool);
612 static __rte_always_inline int __rte_hot
613 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
614 struct pending_queue *pend_q)
616 struct rte_crypto_sym_op *sym_op = op->sym;
617 struct cpt_request_info *req;
618 struct cpt_sess_misc *sess;
623 sess = get_sym_session_private_data(sym_op->session,
624 otx2_cryptodev_driver_id);
626 cpt_op = sess->cpt_op;
628 if (cpt_op & CPT_OP_CIPHER_MASK)
629 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
632 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
636 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
637 op, (unsigned int)cpt_op, ret);
641 ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
644 /* Free buffer allocated by fill params routines */
645 free_op_meta(mdata, qp->meta_info.pool);
651 static __rte_always_inline int __rte_hot
652 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
653 struct pending_queue *pend_q)
655 uint32_t winsz, esn_low = 0, esn_hi = 0, seql = 0, seqh = 0;
656 struct rte_mbuf *m_src = op->sym->m_src;
657 struct otx2_sec_session_ipsec_lp *sess;
658 struct otx2_ipsec_po_sa_ctl *ctl_wrd;
659 struct otx2_ipsec_po_in_sa *sa;
660 struct otx2_sec_session *priv;
661 struct cpt_request_info *req;
662 uint64_t seq_in_sa, seq = 0;
666 priv = get_sec_session_private_data(op->sym->sec_session);
667 sess = &priv->ipsec.lp;
671 esn = ctl_wrd->esn_en;
672 winsz = sa->replay_win_sz;
674 if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
675 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
678 esn_low = rte_be_to_cpu_32(sa->esn_low);
679 esn_hi = rte_be_to_cpu_32(sa->esn_hi);
680 seql = *rte_pktmbuf_mtod_offset(m_src, uint32_t *,
681 sizeof(struct rte_ipv4_hdr) + 4);
682 seql = rte_be_to_cpu_32(seql);
685 seq = (uint64_t)seql;
687 seqh = anti_replay_get_seqh(winsz, seql, esn_hi,
689 seq = ((uint64_t)seqh << 32) | seql;
692 if (unlikely(seq == 0))
693 return IPSEC_ANTI_REPLAY_FAILED;
695 ret = anti_replay_check(sa->replay, seq, winsz);
697 otx2_err("Anti replay check failed");
698 return IPSEC_ANTI_REPLAY_FAILED;
702 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
706 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
710 ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
713 seq_in_sa = ((uint64_t)esn_hi << 32) | esn_low;
714 if (seq > seq_in_sa) {
715 sa->esn_low = rte_cpu_to_be_32(seql);
716 sa->esn_hi = rte_cpu_to_be_32(seqh);
723 static __rte_always_inline int __rte_hot
724 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
725 struct pending_queue *pend_q)
727 const int driver_id = otx2_cryptodev_driver_id;
728 struct rte_crypto_sym_op *sym_op = op->sym;
729 struct rte_cryptodev_sym_session *sess;
732 /* Create temporary session */
733 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
737 ret = sym_session_configure(driver_id, sym_op->xform, sess,
742 sym_op->session = sess;
744 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
752 sym_session_clear(driver_id, sess);
754 rte_mempool_put(qp->sess_mp, sess);
759 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
761 uint16_t nb_allowed, count = 0;
762 struct otx2_cpt_qp *qp = qptr;
763 struct pending_queue *pend_q;
764 struct rte_crypto_op *op;
767 pend_q = &qp->pend_q;
769 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
770 if (nb_ops > nb_allowed)
773 for (count = 0; count < nb_ops; count++) {
775 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
776 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
777 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
778 else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
779 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
781 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
783 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
784 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
785 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
798 static __rte_always_inline void
799 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
800 struct rte_crypto_rsa_xform *rsa_ctx)
802 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
804 switch (rsa->op_type) {
805 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
806 rsa->cipher.length = rsa_ctx->n.length;
807 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
809 case RTE_CRYPTO_ASYM_OP_DECRYPT:
810 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
811 rsa->message.length = rsa_ctx->n.length;
812 memcpy(rsa->message.data, req->rptr,
813 rsa->message.length);
815 /* Get length of decrypted output */
816 rsa->message.length = rte_cpu_to_be_16
817 (*((uint16_t *)req->rptr));
819 * Offset output data pointer by length field
820 * (2 bytes) and copy decrypted data.
822 memcpy(rsa->message.data, req->rptr + 2,
823 rsa->message.length);
826 case RTE_CRYPTO_ASYM_OP_SIGN:
827 rsa->sign.length = rsa_ctx->n.length;
828 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
830 case RTE_CRYPTO_ASYM_OP_VERIFY:
831 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
832 rsa->sign.length = rsa_ctx->n.length;
833 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
835 /* Get length of signed output */
836 rsa->sign.length = rte_cpu_to_be_16
837 (*((uint16_t *)req->rptr));
839 * Offset output data pointer by length field
840 * (2 bytes) and copy signed data.
842 memcpy(rsa->sign.data, req->rptr + 2,
845 if (memcmp(rsa->sign.data, rsa->message.data,
846 rsa->message.length)) {
847 CPT_LOG_DP_ERR("RSA verification failed");
848 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
852 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
853 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
858 static __rte_always_inline void
859 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
860 struct cpt_request_info *req,
861 struct cpt_asym_ec_ctx *ec)
863 int prime_len = ec_grp[ec->curveid].prime.length;
865 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
868 /* Separate out sign r and s components */
869 memcpy(ecdsa->r.data, req->rptr, prime_len);
870 memcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
872 ecdsa->r.length = prime_len;
873 ecdsa->s.length = prime_len;
876 static __rte_always_inline void
877 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
878 struct cpt_request_info *req,
879 struct cpt_asym_ec_ctx *ec)
881 int prime_len = ec_grp[ec->curveid].prime.length;
883 memcpy(ecpm->r.x.data, req->rptr, prime_len);
884 memcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
886 ecpm->r.x.length = prime_len;
887 ecpm->r.y.length = prime_len;
891 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
892 struct cpt_request_info *req)
894 struct rte_crypto_asym_op *op = cop->asym;
895 struct cpt_asym_sess_misc *sess;
897 sess = get_asym_session_private_data(op->session,
898 otx2_cryptodev_driver_id);
900 switch (sess->xfrm_type) {
901 case RTE_CRYPTO_ASYM_XFORM_RSA:
902 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
904 case RTE_CRYPTO_ASYM_XFORM_MODEX:
905 op->modex.result.length = sess->mod_ctx.modulus.length;
906 memcpy(op->modex.result.data, req->rptr,
907 op->modex.result.length);
909 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
910 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
912 case RTE_CRYPTO_ASYM_XFORM_ECPM:
913 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
916 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
917 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
923 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
925 struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
926 vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
927 struct rte_crypto_sym_op *sym_op = cop->sym;
928 struct rte_mbuf *m = sym_op->m_src;
929 struct rte_ipv6_hdr *ip6;
930 struct rte_ipv4_hdr *ip;
935 mdata_len = (int)rsp[3];
936 rte_pktmbuf_trim(m, mdata_len);
938 if (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
939 data = rte_pktmbuf_mtod(m, char *);
941 if (rsp[4] == RTE_SECURITY_IPSEC_TUNNEL_IPV4) {
942 ip = (struct rte_ipv4_hdr *)(data +
943 OTX2_IPSEC_PO_INB_RPTR_HDR);
944 m_len = rte_be_to_cpu_16(ip->total_length);
946 ip6 = (struct rte_ipv6_hdr *)(data +
947 OTX2_IPSEC_PO_INB_RPTR_HDR);
948 m_len = rte_be_to_cpu_16(ip6->payload_len) +
949 sizeof(struct rte_ipv6_hdr);
954 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
959 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
960 uintptr_t *rsp, uint8_t cc)
964 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
965 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
966 if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
967 otx2_cpt_sec_post_process(cop, rsp);
968 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
970 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
975 if (likely(cc == NO_ERR)) {
976 /* Verify authentication data if required */
977 if (unlikely(rsp[2]))
978 compl_auth_verify(cop, (uint8_t *)rsp[2],
981 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
983 if (cc == ERR_GC_ICV_MISCOMPARE)
984 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
986 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
989 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
990 sym_session_clear(otx2_cryptodev_driver_id,
992 sz = rte_cryptodev_sym_get_existing_header_session_size(
994 memset(cop->sym->session, 0, sz);
995 rte_mempool_put(qp->sess_mp, cop->sym->session);
996 cop->sym->session = NULL;
1000 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
1001 if (likely(cc == NO_ERR)) {
1002 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1004 * Pass cpt_req_info stored in metabuf during
1007 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
1008 otx2_cpt_asym_post_process(cop,
1009 (struct cpt_request_info *)rsp);
1011 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1016 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
1018 int i, nb_pending, nb_completed;
1019 struct otx2_cpt_qp *qp = qptr;
1020 struct pending_queue *pend_q;
1021 struct cpt_request_info *req;
1022 struct rte_crypto_op *cop;
1027 pend_q = &qp->pend_q;
1029 nb_pending = pend_q->pending_count;
1031 if (nb_ops > nb_pending)
1032 nb_ops = nb_pending;
1034 for (i = 0; i < nb_ops; i++) {
1035 req = (struct cpt_request_info *)
1036 pend_q->req_queue[pend_q->deq_head];
1038 cc[i] = otx2_cpt_compcode_get(req);
1040 if (unlikely(cc[i] == ERR_REQ_PENDING))
1045 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1046 pend_q->pending_count -= 1;
1051 for (i = 0; i < nb_completed; i++) {
1052 rsp = (void *)ops[i];
1054 metabuf = (void *)rsp[0];
1055 cop = (void *)rsp[1];
1059 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1061 free_op_meta(metabuf, qp->meta_info.pool);
1064 return nb_completed;
1068 otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
1070 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1071 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1079 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1080 struct rte_cryptodev_config *conf)
1082 struct otx2_cpt_vf *vf = dev->data->dev_private;
1085 if (conf->nb_queue_pairs > vf->max_queues) {
1086 CPT_LOG_ERR("Invalid number of queue pairs requested");
1090 dev->feature_flags &= ~conf->ff_disable;
1092 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1093 /* Initialize shared FPM table */
1094 ret = cpt_fpm_init(otx2_fpm_iova);
1099 /* Unregister error interrupts */
1100 if (vf->err_intr_registered)
1101 otx2_cpt_err_intr_unregister(dev);
1104 if (vf->nb_queues) {
1105 ret = otx2_cpt_queues_detach(dev);
1107 CPT_LOG_ERR("Could not detach CPT queues");
1113 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1115 CPT_LOG_ERR("Could not attach CPT queues");
1119 ret = otx2_cpt_msix_offsets_get(dev);
1121 CPT_LOG_ERR("Could not get MSI-X offsets");
1125 /* Register error interrupts */
1126 ret = otx2_cpt_err_intr_register(dev);
1128 CPT_LOG_ERR("Could not register error interrupts");
1132 ret = otx2_cpt_inline_init(dev);
1134 CPT_LOG_ERR("Could not enable inline IPsec");
1135 goto intr_unregister;
1138 otx2_cpt_set_enqdeq_fns(dev);
1143 otx2_cpt_err_intr_unregister(dev);
1145 otx2_cpt_queues_detach(dev);
1150 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1154 CPT_PMD_INIT_FUNC_TRACE();
1160 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1162 CPT_PMD_INIT_FUNC_TRACE();
1164 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1169 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1171 struct otx2_cpt_vf *vf = dev->data->dev_private;
1174 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1175 ret = otx2_cpt_queue_pair_release(dev, i);
1180 /* Unregister error interrupts */
1181 if (vf->err_intr_registered)
1182 otx2_cpt_err_intr_unregister(dev);
1185 if (vf->nb_queues) {
1186 ret = otx2_cpt_queues_detach(dev);
1188 CPT_LOG_ERR("Could not detach CPT queues");
1195 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1196 struct rte_cryptodev_info *info)
1198 struct otx2_cpt_vf *vf = dev->data->dev_private;
1201 info->max_nb_queue_pairs = vf->max_queues;
1202 info->feature_flags = dev->feature_flags;
1203 info->capabilities = otx2_cpt_capabilities_get();
1204 info->sym.max_nb_sessions = 0;
1205 info->driver_id = otx2_cryptodev_driver_id;
1206 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1207 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1212 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1213 const struct rte_cryptodev_qp_conf *conf,
1214 int socket_id __rte_unused)
1216 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1217 struct rte_pci_device *pci_dev;
1218 struct otx2_cpt_qp *qp;
1220 CPT_PMD_INIT_FUNC_TRACE();
1222 if (dev->data->queue_pairs[qp_id] != NULL)
1223 otx2_cpt_queue_pair_release(dev, qp_id);
1225 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1226 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1227 conf->nb_descriptors);
1231 pci_dev = RTE_DEV_TO_PCI(dev->device);
1233 if (pci_dev->mem_resource[2].addr == NULL) {
1234 CPT_LOG_ERR("Invalid PCI mem address");
1238 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1240 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1244 qp->sess_mp = conf->mp_session;
1245 qp->sess_mp_priv = conf->mp_session_private;
1246 dev->data->queue_pairs[qp_id] = qp;
1252 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1254 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1257 CPT_PMD_INIT_FUNC_TRACE();
1262 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1264 ret = otx2_cpt_qp_destroy(dev, qp);
1266 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1270 dev->data->queue_pairs[qp_id] = NULL;
1276 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1278 return cpt_get_session_size();
1282 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1283 struct rte_crypto_sym_xform *xform,
1284 struct rte_cryptodev_sym_session *sess,
1285 struct rte_mempool *pool)
1287 CPT_PMD_INIT_FUNC_TRACE();
1289 return sym_session_configure(dev->driver_id, xform, sess, pool);
1293 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1294 struct rte_cryptodev_sym_session *sess)
1296 CPT_PMD_INIT_FUNC_TRACE();
1298 return sym_session_clear(dev->driver_id, sess);
1302 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1304 return sizeof(struct cpt_asym_sess_misc);
1308 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1309 struct rte_crypto_asym_xform *xform,
1310 struct rte_cryptodev_asym_session *sess,
1311 struct rte_mempool *pool)
1313 struct cpt_asym_sess_misc *priv;
1314 vq_cmd_word3_t vq_cmd_w3;
1317 CPT_PMD_INIT_FUNC_TRACE();
1319 if (rte_mempool_get(pool, (void **)&priv)) {
1320 CPT_LOG_ERR("Could not allocate session_private_data");
1324 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1326 ret = cpt_fill_asym_session_parameters(priv, xform);
1328 CPT_LOG_ERR("Could not configure session parameters");
1330 /* Return session to mempool */
1331 rte_mempool_put(pool, priv);
1336 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;
1337 priv->cpt_inst_w7 = vq_cmd_w3.u64;
1339 set_asym_session_private_data(sess, dev->driver_id, priv);
1345 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1346 struct rte_cryptodev_asym_session *sess)
1348 struct cpt_asym_sess_misc *priv;
1349 struct rte_mempool *sess_mp;
1351 CPT_PMD_INIT_FUNC_TRACE();
1353 priv = get_asym_session_private_data(sess, dev->driver_id);
1357 /* Free resources allocated in session_cfg */
1358 cpt_free_asym_session_parameters(priv);
1360 /* Reset and free object back to pool */
1361 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1362 sess_mp = rte_mempool_from_obj(priv);
1363 set_asym_session_private_data(sess, dev->driver_id, NULL);
1364 rte_mempool_put(sess_mp, priv);
1367 struct rte_cryptodev_ops otx2_cpt_ops = {
1368 /* Device control ops */
1369 .dev_configure = otx2_cpt_dev_config,
1370 .dev_start = otx2_cpt_dev_start,
1371 .dev_stop = otx2_cpt_dev_stop,
1372 .dev_close = otx2_cpt_dev_close,
1373 .dev_infos_get = otx2_cpt_dev_info_get,
1376 .stats_reset = NULL,
1377 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1378 .queue_pair_release = otx2_cpt_queue_pair_release,
1380 /* Symmetric crypto ops */
1381 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1382 .sym_session_configure = otx2_cpt_sym_session_configure,
1383 .sym_session_clear = otx2_cpt_sym_session_clear,
1385 /* Asymmetric crypto ops */
1386 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1387 .asym_session_configure = otx2_cpt_asym_session_cfg,
1388 .asym_session_clear = otx2_cpt_asym_session_clear,