1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
11 #include "otx2_cryptodev.h"
12 #include "otx2_cryptodev_capabilities.h"
13 #include "otx2_cryptodev_hw_access.h"
14 #include "otx2_cryptodev_mbox.h"
15 #include "otx2_cryptodev_ops.h"
16 #include "otx2_ipsec_po_ops.h"
17 #include "otx2_mbox.h"
18 #include "otx2_sec_idev.h"
19 #include "otx2_security.h"
21 #include "cpt_hw_types.h"
22 #include "cpt_pmd_logs.h"
23 #include "cpt_pmd_ops_helper.h"
24 #include "cpt_ucode.h"
25 #include "cpt_ucode_asym.h"
27 #define METABUF_POOL_CACHE_SIZE 512
29 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
31 /* Forward declarations */
34 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
37 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
39 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
43 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
44 struct otx2_cpt_qp *qp, uint8_t qp_id,
47 char mempool_name[RTE_MEMPOOL_NAMESIZE];
48 struct cpt_qp_meta_info *meta_info;
49 struct rte_mempool *pool;
55 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
57 /* Get meta len for scatter gather mode */
58 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
60 /* Extra 32B saved for future considerations */
61 sg_mlen += 4 * sizeof(uint64_t);
63 /* Get meta len for linear buffer (direct) mode */
64 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
66 /* Extra 32B saved for future considerations */
67 lb_mlen += 4 * sizeof(uint64_t);
70 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
72 /* Get meta len required for asymmetric operations */
73 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
77 * Check max requirement for meta buffer to
78 * support crypto op of any type (sym/asym).
80 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
82 /* Allocate mempool */
84 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
85 dev->data->dev_id, qp_id);
87 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
88 METABUF_POOL_CACHE_SIZE, 0,
92 CPT_LOG_ERR("Could not create mempool for metabuf");
96 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
99 CPT_LOG_ERR("Could not set mempool ops");
103 ret = rte_mempool_populate_default(pool);
105 CPT_LOG_ERR("Could not populate metabuf pool");
109 meta_info = &qp->meta_info;
111 meta_info->pool = pool;
112 meta_info->lb_mlen = lb_mlen;
113 meta_info->sg_mlen = sg_mlen;
118 rte_mempool_free(pool);
123 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
125 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
127 rte_mempool_free(meta_info->pool);
129 meta_info->pool = NULL;
130 meta_info->lb_mlen = 0;
131 meta_info->sg_mlen = 0;
135 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
137 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
138 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
141 for (i = 0; i < nb_ethport; i++) {
142 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
143 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
150 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
154 /* Publish inline Tx QP to eth dev security */
155 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
162 static struct otx2_cpt_qp *
163 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
166 struct otx2_cpt_vf *vf = dev->data->dev_private;
167 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
168 const struct rte_memzone *lf_mem;
169 uint32_t len, iq_len, size_div40;
170 char name[RTE_MEMZONE_NAMESIZE];
171 uint64_t used_len, iova;
172 struct otx2_cpt_qp *qp;
177 /* Allocate queue pair */
178 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
181 CPT_LOG_ERR("Could not allocate queue pair");
185 iq_len = OTX2_CPT_IQ_LEN;
188 * Queue size must be a multiple of 40 and effective queue size to
189 * software is (size_div40 - 1) * 40
191 size_div40 = (iq_len + 40 - 1) / 40 + 1;
193 /* For pending queue */
194 len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
196 /* Space for instruction group memory */
197 len += size_div40 * 16;
199 /* So that instruction queues start as pg size aligned */
200 len = RTE_ALIGN(len, pg_sz);
202 /* For instruction queues */
203 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
205 /* Wastage after instruction queues */
206 len = RTE_ALIGN(len, pg_sz);
208 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
211 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
212 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
213 RTE_CACHE_LINE_SIZE);
214 if (lf_mem == NULL) {
215 CPT_LOG_ERR("Could not allocate reserved memzone");
224 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
226 CPT_LOG_ERR("Could not create mempool for metabuf");
230 /* Initialize pending queue */
231 qp->pend_q.rid_queue = (struct rid *)va;
232 qp->pend_q.enq_tail = 0;
233 qp->pend_q.deq_head = 0;
234 qp->pend_q.pending_count = 0;
236 used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
237 used_len += size_div40 * 16;
238 used_len = RTE_ALIGN(used_len, pg_sz);
241 qp->iq_dma_addr = iova;
243 qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
245 lmtline = vf->otx2_dev.bar2 +
246 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
247 OTX2_LMT_LF_LMTLINE(0);
249 qp->lmtline = (void *)lmtline;
251 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
253 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
254 if (ret && (ret != -ENOENT)) {
255 CPT_LOG_ERR("Could not delete inline configuration");
256 goto mempool_destroy;
259 otx2_cpt_iq_disable(qp);
261 ret = otx2_cpt_qp_inline_cfg(dev, qp);
263 CPT_LOG_ERR("Could not configure queue for inline IPsec");
264 goto mempool_destroy;
267 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
270 CPT_LOG_ERR("Could not enable instruction queue");
271 goto mempool_destroy;
277 otx2_cpt_metabuf_mempool_destroy(qp);
279 rte_memzone_free(lf_mem);
286 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
288 const struct rte_memzone *lf_mem;
289 char name[RTE_MEMZONE_NAMESIZE];
292 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
293 if (ret && (ret != -ENOENT)) {
294 CPT_LOG_ERR("Could not delete inline configuration");
298 otx2_cpt_iq_disable(qp);
300 otx2_cpt_metabuf_mempool_destroy(qp);
302 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
305 lf_mem = rte_memzone_lookup(name);
307 ret = rte_memzone_free(lf_mem);
317 sym_xform_verify(struct rte_crypto_sym_xform *xform)
320 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
321 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
322 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
325 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
326 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
327 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
330 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
331 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
332 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
333 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
336 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
337 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
338 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
339 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
343 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
344 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
345 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
352 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
353 struct rte_cryptodev_sym_session *sess,
354 struct rte_mempool *pool)
356 struct cpt_sess_misc *misc;
360 ret = sym_xform_verify(xform);
364 if (unlikely(rte_mempool_get(pool, &priv))) {
365 CPT_LOG_ERR("Could not allocate session private data");
369 memset(priv, 0, sizeof(struct cpt_sess_misc) +
370 offsetof(struct cpt_ctx, fctx));
374 for ( ; xform != NULL; xform = xform->next) {
375 switch (xform->type) {
376 case RTE_CRYPTO_SYM_XFORM_AEAD:
377 ret = fill_sess_aead(xform, misc);
379 case RTE_CRYPTO_SYM_XFORM_CIPHER:
380 ret = fill_sess_cipher(xform, misc);
382 case RTE_CRYPTO_SYM_XFORM_AUTH:
383 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
384 ret = fill_sess_gmac(xform, misc);
386 ret = fill_sess_auth(xform, misc);
396 set_sym_session_private_data(sess, driver_id, misc);
398 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
399 sizeof(struct cpt_sess_misc);
402 * IE engines support IPsec operations
403 * SE engines support IPsec operations, Chacha-Poly and
404 * Air-Crypto operations
406 if (misc->zsk_flag || misc->chacha_poly)
407 misc->egrp = OTX2_CPT_EGRP_SE;
409 misc->egrp = OTX2_CPT_EGRP_SE_IE;
414 rte_mempool_put(pool, priv);
420 sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
422 void *priv = get_sym_session_private_data(sess, driver_id);
423 struct rte_mempool *pool;
428 memset(priv, 0, cpt_get_session_size());
430 pool = rte_mempool_from_obj(priv);
432 set_sym_session_private_data(sess, driver_id, NULL);
434 rte_mempool_put(pool, priv);
437 static __rte_always_inline int32_t __rte_hot
438 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
439 struct pending_queue *pend_q,
440 struct cpt_request_info *req)
442 void *lmtline = qp->lmtline;
443 union cpt_inst_s inst;
446 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
450 inst.s9x.res_addr = req->comp_baddr;
454 inst.s9x.ei0 = req->ist.ei0;
455 inst.s9x.ei1 = req->ist.ei1;
456 inst.s9x.ei2 = req->ist.ei2;
457 inst.s9x.ei3 = req->ist.ei3;
459 req->time_out = rte_get_timer_cycles() +
460 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
463 /* Copy CPT command to LMTLINE */
464 memcpy(lmtline, &inst, sizeof(inst));
467 * Make sure compiler does not reorder memcpy and ldeor.
468 * LMTST transactions are always flushed from the write
469 * buffer immediately, a DMB is not required to push out
473 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
474 } while (lmt_status == 0);
476 pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
478 /* We will use soft queue length here to limit requests */
479 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
480 pend_q->pending_count += 1;
485 static __rte_always_inline int32_t __rte_hot
486 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
487 struct rte_crypto_op *op,
488 struct pending_queue *pend_q)
490 struct cpt_qp_meta_info *minfo = &qp->meta_info;
491 struct rte_crypto_asym_op *asym_op = op->asym;
492 struct asym_op_params params = {0};
493 struct cpt_asym_sess_misc *sess;
499 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
500 CPT_LOG_ERR("Could not allocate meta buffer for request");
504 sess = get_asym_session_private_data(asym_op->session,
505 otx2_cryptodev_driver_id);
507 /* Store IO address of the mdata to meta_buf */
508 params.meta_buf = rte_mempool_virt2iova(mdata);
511 cop[0] = (uintptr_t)mdata;
512 cop[1] = (uintptr_t)op;
513 cop[2] = cop[3] = 0ULL;
515 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
516 params.req->op = cop;
518 /* Adjust meta_buf to point to end of cpt_request_info structure */
519 params.meta_buf += (4 * sizeof(uintptr_t)) +
520 sizeof(struct cpt_request_info);
521 switch (sess->xfrm_type) {
522 case RTE_CRYPTO_ASYM_XFORM_MODEX:
523 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
527 case RTE_CRYPTO_ASYM_XFORM_RSA:
528 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
532 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
533 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
537 case RTE_CRYPTO_ASYM_XFORM_ECPM:
538 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
539 sess->ec_ctx.curveid);
544 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
549 /* Set engine group of AE */
550 w3 = (vq_cmd_word3_t *)¶ms.req->ist.ei3;
551 w3->s.grp = OTX2_CPT_EGRP_AE;
553 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req);
556 CPT_LOG_DP_ERR("Could not enqueue crypto req");
563 free_op_meta(mdata, minfo->pool);
568 static __rte_always_inline int __rte_hot
569 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
570 struct pending_queue *pend_q)
572 struct rte_crypto_sym_op *sym_op = op->sym;
573 struct cpt_request_info *req;
574 struct cpt_sess_misc *sess;
580 sess = get_sym_session_private_data(sym_op->session,
581 otx2_cryptodev_driver_id);
583 cpt_op = sess->cpt_op;
585 if (cpt_op & CPT_OP_CIPHER_MASK)
586 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
589 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
593 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
594 op, (unsigned int)cpt_op, ret);
598 w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
599 w3->s.grp = sess->egrp;
601 ret = otx2_cpt_enqueue_req(qp, pend_q, req);
604 /* Free buffer allocated by fill params routines */
605 free_op_meta(mdata, qp->meta_info.pool);
611 static __rte_always_inline int __rte_hot
612 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
613 struct pending_queue *pend_q)
615 struct otx2_sec_session_ipsec_lp *sess;
616 struct otx2_ipsec_po_sa_ctl *ctl_wrd;
617 struct otx2_sec_session *priv;
618 struct cpt_request_info *req;
621 priv = get_sec_session_private_data(op->sym->sec_session);
622 sess = &priv->ipsec.lp;
624 ctl_wrd = &sess->in_sa.ctl;
626 if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
627 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
629 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
632 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
636 ret = otx2_cpt_enqueue_req(qp, pend_q, req);
641 static __rte_always_inline int __rte_hot
642 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
643 struct pending_queue *pend_q)
645 const int driver_id = otx2_cryptodev_driver_id;
646 struct rte_crypto_sym_op *sym_op = op->sym;
647 struct rte_cryptodev_sym_session *sess;
650 /* Create temporary session */
651 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
655 ret = sym_session_configure(driver_id, sym_op->xform, sess,
660 sym_op->session = sess;
662 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
670 sym_session_clear(driver_id, sess);
672 rte_mempool_put(qp->sess_mp, sess);
677 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
679 uint16_t nb_allowed, count = 0;
680 struct otx2_cpt_qp *qp = qptr;
681 struct pending_queue *pend_q;
682 struct rte_crypto_op *op;
685 pend_q = &qp->pend_q;
687 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
688 if (nb_ops > nb_allowed)
691 for (count = 0; count < nb_ops; count++) {
693 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
694 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
695 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
696 else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
697 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
699 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
701 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
702 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
703 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
716 static __rte_always_inline void
717 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
718 struct rte_crypto_rsa_xform *rsa_ctx)
720 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
722 switch (rsa->op_type) {
723 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
724 rsa->cipher.length = rsa_ctx->n.length;
725 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
727 case RTE_CRYPTO_ASYM_OP_DECRYPT:
728 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
729 rsa->message.length = rsa_ctx->n.length;
730 memcpy(rsa->message.data, req->rptr,
731 rsa->message.length);
733 /* Get length of decrypted output */
734 rsa->message.length = rte_cpu_to_be_16
735 (*((uint16_t *)req->rptr));
737 * Offset output data pointer by length field
738 * (2 bytes) and copy decrypted data.
740 memcpy(rsa->message.data, req->rptr + 2,
741 rsa->message.length);
744 case RTE_CRYPTO_ASYM_OP_SIGN:
745 rsa->sign.length = rsa_ctx->n.length;
746 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
748 case RTE_CRYPTO_ASYM_OP_VERIFY:
749 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
750 rsa->sign.length = rsa_ctx->n.length;
751 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
753 /* Get length of signed output */
754 rsa->sign.length = rte_cpu_to_be_16
755 (*((uint16_t *)req->rptr));
757 * Offset output data pointer by length field
758 * (2 bytes) and copy signed data.
760 memcpy(rsa->sign.data, req->rptr + 2,
763 if (memcmp(rsa->sign.data, rsa->message.data,
764 rsa->message.length)) {
765 CPT_LOG_DP_ERR("RSA verification failed");
766 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
770 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
771 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
776 static __rte_always_inline void
777 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
778 struct cpt_request_info *req,
779 struct cpt_asym_ec_ctx *ec)
781 int prime_len = ec_grp[ec->curveid].prime.length;
783 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
786 /* Separate out sign r and s components */
787 memcpy(ecdsa->r.data, req->rptr, prime_len);
788 memcpy(ecdsa->s.data, req->rptr + ROUNDUP8(prime_len), prime_len);
789 ecdsa->r.length = prime_len;
790 ecdsa->s.length = prime_len;
793 static __rte_always_inline void
794 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
795 struct cpt_request_info *req,
796 struct cpt_asym_ec_ctx *ec)
798 int prime_len = ec_grp[ec->curveid].prime.length;
800 memcpy(ecpm->r.x.data, req->rptr, prime_len);
801 memcpy(ecpm->r.y.data, req->rptr + ROUNDUP8(prime_len), prime_len);
802 ecpm->r.x.length = prime_len;
803 ecpm->r.y.length = prime_len;
807 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
808 struct cpt_request_info *req)
810 struct rte_crypto_asym_op *op = cop->asym;
811 struct cpt_asym_sess_misc *sess;
813 sess = get_asym_session_private_data(op->session,
814 otx2_cryptodev_driver_id);
816 switch (sess->xfrm_type) {
817 case RTE_CRYPTO_ASYM_XFORM_RSA:
818 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
820 case RTE_CRYPTO_ASYM_XFORM_MODEX:
821 op->modex.result.length = sess->mod_ctx.modulus.length;
822 memcpy(op->modex.result.data, req->rptr,
823 op->modex.result.length);
825 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
826 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
828 case RTE_CRYPTO_ASYM_XFORM_ECPM:
829 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
832 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
833 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
839 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
841 struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
842 vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
843 struct rte_crypto_sym_op *sym_op = cop->sym;
844 struct rte_mbuf *m = sym_op->m_src;
845 struct rte_ipv4_hdr *ip;
850 mdata_len = (int)rsp[3];
851 rte_pktmbuf_trim(m, mdata_len);
853 if ((word0->s.opcode & 0xff) == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
854 data = rte_pktmbuf_mtod(m, char *);
855 ip = (struct rte_ipv4_hdr *)(data + OTX2_IPSEC_PO_INB_RPTR_HDR);
857 m_len = rte_be_to_cpu_16(ip->total_length);
861 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
866 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
867 uintptr_t *rsp, uint8_t cc)
871 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
872 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
873 if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
874 otx2_cpt_sec_post_process(cop, rsp);
875 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
877 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
882 if (likely(cc == NO_ERR)) {
883 /* Verify authentication data if required */
884 if (unlikely(rsp[2]))
885 compl_auth_verify(cop, (uint8_t *)rsp[2],
888 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
890 if (cc == ERR_GC_ICV_MISCOMPARE)
891 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
893 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
896 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
897 sym_session_clear(otx2_cryptodev_driver_id,
899 sz = rte_cryptodev_sym_get_existing_header_session_size(
901 memset(cop->sym->session, 0, sz);
902 rte_mempool_put(qp->sess_mp, cop->sym->session);
903 cop->sym->session = NULL;
907 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
908 if (likely(cc == NO_ERR)) {
909 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
911 * Pass cpt_req_info stored in metabuf during
914 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
915 otx2_cpt_asym_post_process(cop,
916 (struct cpt_request_info *)rsp);
918 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
922 static __rte_always_inline uint8_t
923 otx2_cpt_compcode_get(struct cpt_request_info *req)
925 volatile struct cpt_res_s_9s *res;
928 res = (volatile struct cpt_res_s_9s *)req->completion_addr;
930 if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
931 if (rte_get_timer_cycles() < req->time_out)
932 return ERR_REQ_PENDING;
934 CPT_LOG_DP_ERR("Request timed out");
935 return ERR_REQ_TIMEOUT;
938 if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
940 if (unlikely(res->uc_compcode)) {
941 ret = res->uc_compcode;
942 CPT_LOG_DP_DEBUG("Request failed with microcode error");
943 CPT_LOG_DP_DEBUG("MC completion code 0x%x",
947 CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
950 switch (res->compcode) {
951 case CPT_9X_COMP_E_INSTERR:
952 CPT_LOG_DP_ERR("Request failed with instruction error");
954 case CPT_9X_COMP_E_FAULT:
955 CPT_LOG_DP_ERR("Request failed with DMA fault");
957 case CPT_9X_COMP_E_HWERR:
958 CPT_LOG_DP_ERR("Request failed with hardware error");
961 CPT_LOG_DP_ERR("Request failed with unknown completion code");
969 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
971 int i, nb_pending, nb_completed;
972 struct otx2_cpt_qp *qp = qptr;
973 struct pending_queue *pend_q;
974 struct cpt_request_info *req;
975 struct rte_crypto_op *cop;
981 pend_q = &qp->pend_q;
983 nb_pending = pend_q->pending_count;
985 if (nb_ops > nb_pending)
988 for (i = 0; i < nb_ops; i++) {
989 rid = &pend_q->rid_queue[pend_q->deq_head];
990 req = (struct cpt_request_info *)(rid->rid);
992 cc[i] = otx2_cpt_compcode_get(req);
994 if (unlikely(cc[i] == ERR_REQ_PENDING))
999 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1000 pend_q->pending_count -= 1;
1005 for (i = 0; i < nb_completed; i++) {
1006 rsp = (void *)ops[i];
1008 metabuf = (void *)rsp[0];
1009 cop = (void *)rsp[1];
1013 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1015 free_op_meta(metabuf, qp->meta_info.pool);
1018 return nb_completed;
1024 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1025 struct rte_cryptodev_config *conf)
1027 struct otx2_cpt_vf *vf = dev->data->dev_private;
1030 if (conf->nb_queue_pairs > vf->max_queues) {
1031 CPT_LOG_ERR("Invalid number of queue pairs requested");
1035 dev->feature_flags &= ~conf->ff_disable;
1037 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1038 /* Initialize shared FPM table */
1039 ret = cpt_fpm_init(otx2_fpm_iova);
1044 /* Unregister error interrupts */
1045 if (vf->err_intr_registered)
1046 otx2_cpt_err_intr_unregister(dev);
1049 if (vf->nb_queues) {
1050 ret = otx2_cpt_queues_detach(dev);
1052 CPT_LOG_ERR("Could not detach CPT queues");
1058 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1060 CPT_LOG_ERR("Could not attach CPT queues");
1064 ret = otx2_cpt_msix_offsets_get(dev);
1066 CPT_LOG_ERR("Could not get MSI-X offsets");
1070 /* Register error interrupts */
1071 ret = otx2_cpt_err_intr_register(dev);
1073 CPT_LOG_ERR("Could not register error interrupts");
1077 ret = otx2_cpt_inline_init(dev);
1079 CPT_LOG_ERR("Could not enable inline IPsec");
1080 goto intr_unregister;
1083 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1084 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1090 otx2_cpt_err_intr_unregister(dev);
1092 otx2_cpt_queues_detach(dev);
1097 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1101 CPT_PMD_INIT_FUNC_TRACE();
1107 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1109 CPT_PMD_INIT_FUNC_TRACE();
1111 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1116 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1118 struct otx2_cpt_vf *vf = dev->data->dev_private;
1121 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1122 ret = otx2_cpt_queue_pair_release(dev, i);
1127 /* Unregister error interrupts */
1128 if (vf->err_intr_registered)
1129 otx2_cpt_err_intr_unregister(dev);
1132 if (vf->nb_queues) {
1133 ret = otx2_cpt_queues_detach(dev);
1135 CPT_LOG_ERR("Could not detach CPT queues");
1142 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1143 struct rte_cryptodev_info *info)
1145 struct otx2_cpt_vf *vf = dev->data->dev_private;
1148 info->max_nb_queue_pairs = vf->max_queues;
1149 info->feature_flags = dev->feature_flags;
1150 info->capabilities = otx2_cpt_capabilities_get();
1151 info->sym.max_nb_sessions = 0;
1152 info->driver_id = otx2_cryptodev_driver_id;
1153 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1154 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1159 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1160 const struct rte_cryptodev_qp_conf *conf,
1161 int socket_id __rte_unused)
1163 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1164 struct rte_pci_device *pci_dev;
1165 struct otx2_cpt_qp *qp;
1167 CPT_PMD_INIT_FUNC_TRACE();
1169 if (dev->data->queue_pairs[qp_id] != NULL)
1170 otx2_cpt_queue_pair_release(dev, qp_id);
1172 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1173 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1174 conf->nb_descriptors);
1178 pci_dev = RTE_DEV_TO_PCI(dev->device);
1180 if (pci_dev->mem_resource[2].addr == NULL) {
1181 CPT_LOG_ERR("Invalid PCI mem address");
1185 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1187 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1191 qp->sess_mp = conf->mp_session;
1192 qp->sess_mp_priv = conf->mp_session_private;
1193 dev->data->queue_pairs[qp_id] = qp;
1199 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1201 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1204 CPT_PMD_INIT_FUNC_TRACE();
1209 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1211 ret = otx2_cpt_qp_destroy(dev, qp);
1213 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1217 dev->data->queue_pairs[qp_id] = NULL;
1223 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1225 return cpt_get_session_size();
1229 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1230 struct rte_crypto_sym_xform *xform,
1231 struct rte_cryptodev_sym_session *sess,
1232 struct rte_mempool *pool)
1234 CPT_PMD_INIT_FUNC_TRACE();
1236 return sym_session_configure(dev->driver_id, xform, sess, pool);
1240 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1241 struct rte_cryptodev_sym_session *sess)
1243 CPT_PMD_INIT_FUNC_TRACE();
1245 return sym_session_clear(dev->driver_id, sess);
1249 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1251 return sizeof(struct cpt_asym_sess_misc);
1255 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1256 struct rte_crypto_asym_xform *xform,
1257 struct rte_cryptodev_asym_session *sess,
1258 struct rte_mempool *pool)
1260 struct cpt_asym_sess_misc *priv;
1263 CPT_PMD_INIT_FUNC_TRACE();
1265 if (rte_mempool_get(pool, (void **)&priv)) {
1266 CPT_LOG_ERR("Could not allocate session_private_data");
1270 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1272 ret = cpt_fill_asym_session_parameters(priv, xform);
1274 CPT_LOG_ERR("Could not configure session parameters");
1276 /* Return session to mempool */
1277 rte_mempool_put(pool, priv);
1281 set_asym_session_private_data(sess, dev->driver_id, priv);
1286 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1287 struct rte_cryptodev_asym_session *sess)
1289 struct cpt_asym_sess_misc *priv;
1290 struct rte_mempool *sess_mp;
1292 CPT_PMD_INIT_FUNC_TRACE();
1294 priv = get_asym_session_private_data(sess, dev->driver_id);
1298 /* Free resources allocated in session_cfg */
1299 cpt_free_asym_session_parameters(priv);
1301 /* Reset and free object back to pool */
1302 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1303 sess_mp = rte_mempool_from_obj(priv);
1304 set_asym_session_private_data(sess, dev->driver_id, NULL);
1305 rte_mempool_put(sess_mp, priv);
1308 struct rte_cryptodev_ops otx2_cpt_ops = {
1309 /* Device control ops */
1310 .dev_configure = otx2_cpt_dev_config,
1311 .dev_start = otx2_cpt_dev_start,
1312 .dev_stop = otx2_cpt_dev_stop,
1313 .dev_close = otx2_cpt_dev_close,
1314 .dev_infos_get = otx2_cpt_dev_info_get,
1317 .stats_reset = NULL,
1318 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1319 .queue_pair_release = otx2_cpt_queue_pair_release,
1321 /* Symmetric crypto ops */
1322 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1323 .sym_session_configure = otx2_cpt_sym_session_configure,
1324 .sym_session_clear = otx2_cpt_sym_session_clear,
1326 /* Asymmetric crypto ops */
1327 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1328 .asym_session_configure = otx2_cpt_asym_session_cfg,
1329 .asym_session_clear = otx2_cpt_asym_session_clear,