1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2015-2018 Intel Corporation
4 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
5 #define ADF_TRANSPORT_ACCESS_MACROS_H
10 #define ADF_CSR_WR(csrAddr, csrOffset, val) \
11 rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
14 #define ADF_CSR_RD(csrAddr, csrOffset) \
15 rte_read32((((uint8_t *)csrAddr) + csrOffset))
17 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
18 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
19 #define ADF_RING_CSR_RING_CONFIG 0x000
20 #define ADF_RING_CSR_RING_LBASE 0x040
21 #define ADF_RING_CSR_RING_UBASE 0x080
22 #define ADF_RING_CSR_RING_HEAD 0x0C0
23 #define ADF_RING_CSR_RING_TAIL 0x100
24 #define ADF_RING_CSR_E_STAT 0x14C
25 #define ADF_RING_CSR_INT_SRCSEL 0x174
26 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
27 #define ADF_RING_CSR_INT_COL_EN 0x17C
28 #define ADF_RING_CSR_INT_COL_CTL 0x180
29 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
30 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
31 #define ADF_RING_BUNDLE_SIZE 0x1000
32 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
33 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
34 #define ADF_COALESCING_MIN_TIME 0x1FF
35 #define ADF_COALESCING_MAX_TIME 0xFFFFF
36 #define ADF_COALESCING_DEF_TIME 0x27FF
37 #define ADF_RING_NEAR_WATERMARK_512 0x08
38 #define ADF_RING_NEAR_WATERMARK_0 0x00
39 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F
40 #define ADF_RING_EMPTY_SIG_BYTE 0x7F
42 /* Valid internal ring size values */
43 #define ADF_RING_SIZE_128 0x01
44 #define ADF_RING_SIZE_256 0x02
45 #define ADF_RING_SIZE_512 0x03
46 #define ADF_RING_SIZE_4K 0x06
47 #define ADF_RING_SIZE_16K 0x08
48 #define ADF_RING_SIZE_4M 0x10
49 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
50 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
51 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
53 #define ADF_NUM_BUNDLES_PER_DEV 1
54 #define ADF_NUM_SYM_QPS_PER_BUNDLE 2
56 /* Valid internal msg size values */
57 #define ADF_MSG_SIZE_32 0x01
58 #define ADF_MSG_SIZE_64 0x02
59 #define ADF_MSG_SIZE_128 0x04
60 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
61 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
63 /* Size to bytes conversion macros for ring and msg size values */
64 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
65 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
66 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
67 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
69 /* Minimum ring bufer size for memory allocation */
70 #define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \
71 ADF_RING_SIZE_4K : SIZE)
72 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
73 #define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \
75 /* Max outstanding requests */
76 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
77 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
78 #define BUILD_RING_CONFIG(size) \
79 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \
80 | (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
82 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
83 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \
84 | (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
86 #define BUILD_RING_BASE_ADDR(addr, size) \
87 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
88 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
89 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
90 ADF_RING_CSR_RING_HEAD + (ring << 2))
91 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
92 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
93 ADF_RING_CSR_RING_TAIL + (ring << 2))
94 #define READ_CSR_E_STAT(csr_base_addr, bank) \
95 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
97 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
98 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
99 ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
100 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
102 uint32_t l_base = 0, u_base = 0; \
103 l_base = (uint32_t)(value & 0xFFFFFFFF); \
104 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
105 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
106 ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \
107 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
108 ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
110 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
111 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
112 ADF_RING_CSR_RING_HEAD + (ring << 2), value)
113 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
114 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
115 ADF_RING_CSR_RING_TAIL + (ring << 2), value)
116 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
118 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
119 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
120 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
121 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
123 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
124 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
125 ADF_RING_CSR_INT_COL_EN, value)
126 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
127 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
128 ADF_RING_CSR_INT_COL_CTL, \
129 ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
130 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
131 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
132 ADF_RING_CSR_INT_FLAG_AND_COL, value)