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6 * Copyright(c) 2015 Intel Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
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47 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
48 #define ADF_TRANSPORT_ACCESS_MACROS_H
51 #define ADF_CSR_WR(csrAddr, csrOffset, val) \
52 (void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) \
56 #define ADF_CSR_RD(csrAddr, csrOffset) \
57 (*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)))
59 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
60 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
61 #define ADF_RING_CSR_RING_CONFIG 0x000
62 #define ADF_RING_CSR_RING_LBASE 0x040
63 #define ADF_RING_CSR_RING_UBASE 0x080
64 #define ADF_RING_CSR_RING_HEAD 0x0C0
65 #define ADF_RING_CSR_RING_TAIL 0x100
66 #define ADF_RING_CSR_E_STAT 0x14C
67 #define ADF_RING_CSR_INT_SRCSEL 0x174
68 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
69 #define ADF_RING_CSR_INT_COL_EN 0x17C
70 #define ADF_RING_CSR_INT_COL_CTL 0x180
71 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
72 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
73 #define ADF_RING_BUNDLE_SIZE 0x1000
74 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
75 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
76 #define ADF_COALESCING_MIN_TIME 0x1FF
77 #define ADF_COALESCING_MAX_TIME 0xFFFFF
78 #define ADF_COALESCING_DEF_TIME 0x27FF
79 #define ADF_RING_NEAR_WATERMARK_512 0x08
80 #define ADF_RING_NEAR_WATERMARK_0 0x00
81 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F
83 /* Valid internal ring size values */
84 #define ADF_RING_SIZE_128 0x01
85 #define ADF_RING_SIZE_256 0x02
86 #define ADF_RING_SIZE_512 0x03
87 #define ADF_RING_SIZE_4K 0x06
88 #define ADF_RING_SIZE_16K 0x08
89 #define ADF_RING_SIZE_4M 0x10
90 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
91 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
92 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
94 #define ADF_NUM_BUNDLES_PER_DEV 1
95 #define ADF_NUM_SYM_QPS_PER_BUNDLE 2
97 /* Valid internal msg size values */
98 #define ADF_MSG_SIZE_32 0x01
99 #define ADF_MSG_SIZE_64 0x02
100 #define ADF_MSG_SIZE_128 0x04
101 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
102 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
104 /* Size to bytes conversion macros for ring and msg size values */
105 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
106 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
107 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
108 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
110 /* Minimum ring bufer size for memory allocation */
111 #define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \
112 ADF_RING_SIZE_4K : SIZE)
113 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
114 #define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \
116 /* Max outstanding requests */
117 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
118 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
119 #define BUILD_RING_CONFIG(size) \
120 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \
121 | (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
123 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
124 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \
125 | (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
127 #define BUILD_RING_BASE_ADDR(addr, size) \
128 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
129 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
130 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
131 ADF_RING_CSR_RING_HEAD + (ring << 2))
132 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
133 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
134 ADF_RING_CSR_RING_TAIL + (ring << 2))
135 #define READ_CSR_E_STAT(csr_base_addr, bank) \
136 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
138 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
139 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
140 ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
141 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
143 uint32_t l_base = 0, u_base = 0; \
144 l_base = (uint32_t)(value & 0xFFFFFFFF); \
145 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
146 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
147 ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \
148 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
149 ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
151 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
152 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
153 ADF_RING_CSR_RING_HEAD + (ring << 2), value)
154 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
155 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
156 ADF_RING_CSR_RING_TAIL + (ring << 2), value)
157 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
159 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
160 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
161 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
162 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
164 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
165 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
166 ADF_RING_CSR_INT_COL_EN, value)
167 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
168 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
169 ADF_RING_CSR_INT_COL_CTL, \
170 ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
171 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
172 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
173 ADF_RING_CSR_INT_FLAG_AND_COL, value)