2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
6 * Copyright(c) 2015-2016 Intel Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
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20 * Copyright(c) 2015-2017 Intel Corporation.
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22 * modification, are permitted provided that the following conditions
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33 * from this software without specific prior written permission.
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48 #include <rte_memcpy.h>
49 #include <rte_common.h>
50 #include <rte_spinlock.h>
51 #include <rte_byteorder.h>
53 #include <rte_malloc.h>
54 #include <rte_crypto_sym.h>
56 #include "../qat_logs.h"
58 #include <openssl/sha.h> /* Needed to calculate pre-compute values */
59 #include <openssl/aes.h> /* Needed to calculate pre-compute values */
60 #include <openssl/md5.h> /* Needed to calculate pre-compute values */
64 /* returns block size in bytes per cipher algo */
65 int qat_cipher_get_block_size(enum icp_qat_hw_cipher_algo qat_cipher_alg)
67 switch (qat_cipher_alg) {
68 case ICP_QAT_HW_CIPHER_ALGO_DES:
69 return ICP_QAT_HW_DES_BLK_SZ;
70 case ICP_QAT_HW_CIPHER_ALGO_3DES:
71 return ICP_QAT_HW_3DES_BLK_SZ;
72 case ICP_QAT_HW_CIPHER_ALGO_AES128:
73 case ICP_QAT_HW_CIPHER_ALGO_AES192:
74 case ICP_QAT_HW_CIPHER_ALGO_AES256:
75 return ICP_QAT_HW_AES_BLK_SZ;
77 PMD_DRV_LOG(ERR, "invalid block cipher alg %u", qat_cipher_alg);
84 * Returns size in bytes per hash algo for state1 size field in cd_ctrl
85 * This is digest size rounded up to nearest quadword
87 static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
89 switch (qat_hash_alg) {
90 case ICP_QAT_HW_AUTH_ALGO_SHA1:
91 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,
92 QAT_HW_DEFAULT_ALIGNMENT);
93 case ICP_QAT_HW_AUTH_ALGO_SHA224:
94 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA224_STATE1_SZ,
95 QAT_HW_DEFAULT_ALIGNMENT);
96 case ICP_QAT_HW_AUTH_ALGO_SHA256:
97 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
98 QAT_HW_DEFAULT_ALIGNMENT);
99 case ICP_QAT_HW_AUTH_ALGO_SHA384:
100 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
101 QAT_HW_DEFAULT_ALIGNMENT);
102 case ICP_QAT_HW_AUTH_ALGO_SHA512:
103 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
104 QAT_HW_DEFAULT_ALIGNMENT);
105 case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
106 return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ,
107 QAT_HW_DEFAULT_ALIGNMENT);
108 case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
109 case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
110 return QAT_HW_ROUND_UP(ICP_QAT_HW_GALOIS_128_STATE1_SZ,
111 QAT_HW_DEFAULT_ALIGNMENT);
112 case ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:
113 return QAT_HW_ROUND_UP(ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ,
114 QAT_HW_DEFAULT_ALIGNMENT);
115 case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
116 return QAT_HW_ROUND_UP(ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ,
117 QAT_HW_DEFAULT_ALIGNMENT);
118 case ICP_QAT_HW_AUTH_ALGO_MD5:
119 return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
120 QAT_HW_DEFAULT_ALIGNMENT);
121 case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
122 return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
123 QAT_HW_DEFAULT_ALIGNMENT);
124 case ICP_QAT_HW_AUTH_ALGO_NULL:
125 return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
126 QAT_HW_DEFAULT_ALIGNMENT);
127 case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
128 return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ,
129 QAT_HW_DEFAULT_ALIGNMENT);
130 case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
131 /* return maximum state1 size in this case */
132 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
133 QAT_HW_DEFAULT_ALIGNMENT);
135 PMD_DRV_LOG(ERR, "invalid hash alg %u", qat_hash_alg);
141 /* returns digest size in bytes per hash algo */
142 static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
144 switch (qat_hash_alg) {
145 case ICP_QAT_HW_AUTH_ALGO_SHA1:
146 return ICP_QAT_HW_SHA1_STATE1_SZ;
147 case ICP_QAT_HW_AUTH_ALGO_SHA224:
148 return ICP_QAT_HW_SHA224_STATE1_SZ;
149 case ICP_QAT_HW_AUTH_ALGO_SHA256:
150 return ICP_QAT_HW_SHA256_STATE1_SZ;
151 case ICP_QAT_HW_AUTH_ALGO_SHA384:
152 return ICP_QAT_HW_SHA384_STATE1_SZ;
153 case ICP_QAT_HW_AUTH_ALGO_SHA512:
154 return ICP_QAT_HW_SHA512_STATE1_SZ;
155 case ICP_QAT_HW_AUTH_ALGO_MD5:
156 return ICP_QAT_HW_MD5_STATE1_SZ;
157 case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
158 /* return maximum digest size in this case */
159 return ICP_QAT_HW_SHA512_STATE1_SZ;
161 PMD_DRV_LOG(ERR, "invalid hash alg %u", qat_hash_alg);
167 /* returns block size in byes per hash algo */
168 static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
170 switch (qat_hash_alg) {
171 case ICP_QAT_HW_AUTH_ALGO_SHA1:
173 case ICP_QAT_HW_AUTH_ALGO_SHA224:
174 return SHA256_CBLOCK;
175 case ICP_QAT_HW_AUTH_ALGO_SHA256:
176 return SHA256_CBLOCK;
177 case ICP_QAT_HW_AUTH_ALGO_SHA384:
178 return SHA512_CBLOCK;
179 case ICP_QAT_HW_AUTH_ALGO_SHA512:
180 return SHA512_CBLOCK;
181 case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
183 case ICP_QAT_HW_AUTH_ALGO_MD5:
185 case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
186 /* return maximum block size in this case */
187 return SHA512_CBLOCK;
189 PMD_DRV_LOG(ERR, "invalid hash alg %u", qat_hash_alg);
195 static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)
199 if (!SHA1_Init(&ctx))
201 SHA1_Transform(&ctx, data_in);
202 rte_memcpy(data_out, &ctx, SHA_DIGEST_LENGTH);
206 static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
210 if (!SHA224_Init(&ctx))
212 SHA256_Transform(&ctx, data_in);
213 rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
217 static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
221 if (!SHA256_Init(&ctx))
223 SHA256_Transform(&ctx, data_in);
224 rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
228 static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
232 if (!SHA384_Init(&ctx))
234 SHA512_Transform(&ctx, data_in);
235 rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
239 static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
243 if (!SHA512_Init(&ctx))
245 SHA512_Transform(&ctx, data_in);
246 rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
250 static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)
256 MD5_Transform(&ctx, data_in);
257 rte_memcpy(data_out, &ctx, MD5_DIGEST_LENGTH);
262 static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
267 uint8_t digest[qat_hash_get_digest_size(
268 ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
269 uint32_t *hash_state_out_be32;
270 uint64_t *hash_state_out_be64;
273 PMD_INIT_FUNC_TRACE();
274 digest_size = qat_hash_get_digest_size(hash_alg);
275 if (digest_size <= 0)
278 hash_state_out_be32 = (uint32_t *)data_out;
279 hash_state_out_be64 = (uint64_t *)data_out;
282 case ICP_QAT_HW_AUTH_ALGO_SHA1:
283 if (partial_hash_sha1(data_in, digest))
285 for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
286 *hash_state_out_be32 =
287 rte_bswap32(*(((uint32_t *)digest)+i));
289 case ICP_QAT_HW_AUTH_ALGO_SHA224:
290 if (partial_hash_sha224(data_in, digest))
292 for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
293 *hash_state_out_be32 =
294 rte_bswap32(*(((uint32_t *)digest)+i));
296 case ICP_QAT_HW_AUTH_ALGO_SHA256:
297 if (partial_hash_sha256(data_in, digest))
299 for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
300 *hash_state_out_be32 =
301 rte_bswap32(*(((uint32_t *)digest)+i));
303 case ICP_QAT_HW_AUTH_ALGO_SHA384:
304 if (partial_hash_sha384(data_in, digest))
306 for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
307 *hash_state_out_be64 =
308 rte_bswap64(*(((uint64_t *)digest)+i));
310 case ICP_QAT_HW_AUTH_ALGO_SHA512:
311 if (partial_hash_sha512(data_in, digest))
313 for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
314 *hash_state_out_be64 =
315 rte_bswap64(*(((uint64_t *)digest)+i));
317 case ICP_QAT_HW_AUTH_ALGO_MD5:
318 if (partial_hash_md5(data_in, data_out))
322 PMD_DRV_LOG(ERR, "invalid hash alg %u", hash_alg);
328 #define HMAC_IPAD_VALUE 0x36
329 #define HMAC_OPAD_VALUE 0x5c
330 #define HASH_XCBC_PRECOMP_KEY_NUM 3
332 static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
333 const uint8_t *auth_key,
334 uint16_t auth_keylen,
335 uint8_t *p_state_buf,
336 uint16_t *p_state_len)
339 uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
340 uint8_t opad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
343 PMD_INIT_FUNC_TRACE();
344 if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
345 static uint8_t qat_aes_xcbc_key_seed[
346 ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
347 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
348 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
349 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
350 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
351 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
352 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
356 uint8_t *out = p_state_buf;
360 in = rte_zmalloc("working mem for key",
361 ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
362 rte_memcpy(in, qat_aes_xcbc_key_seed,
363 ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
364 for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
365 if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
368 (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
370 (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
371 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
374 AES_encrypt(in, out, &enc_key);
375 in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
376 out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
378 *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
379 rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
381 } else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
382 (hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
384 uint8_t *out = p_state_buf;
387 memset(p_state_buf, 0, ICP_QAT_HW_GALOIS_H_SZ +
388 ICP_QAT_HW_GALOIS_LEN_A_SZ +
389 ICP_QAT_HW_GALOIS_E_CTR0_SZ);
390 in = rte_zmalloc("working mem for key",
391 ICP_QAT_HW_GALOIS_H_SZ, 16);
392 memset(in, 0, ICP_QAT_HW_GALOIS_H_SZ);
393 if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
397 AES_encrypt(in, out, &enc_key);
398 *p_state_len = ICP_QAT_HW_GALOIS_H_SZ +
399 ICP_QAT_HW_GALOIS_LEN_A_SZ +
400 ICP_QAT_HW_GALOIS_E_CTR0_SZ;
405 block_size = qat_hash_get_block_size(hash_alg);
408 /* init ipad and opad from key and xor with fixed values */
409 memset(ipad, 0, block_size);
410 memset(opad, 0, block_size);
412 if (auth_keylen > (unsigned int)block_size) {
413 PMD_DRV_LOG(ERR, "invalid keylen %u", auth_keylen);
416 rte_memcpy(ipad, auth_key, auth_keylen);
417 rte_memcpy(opad, auth_key, auth_keylen);
419 for (i = 0; i < block_size; i++) {
420 uint8_t *ipad_ptr = ipad + i;
421 uint8_t *opad_ptr = opad + i;
422 *ipad_ptr ^= HMAC_IPAD_VALUE;
423 *opad_ptr ^= HMAC_OPAD_VALUE;
426 /* do partial hash of ipad and copy to state1 */
427 if (partial_hash_compute(hash_alg, ipad, p_state_buf)) {
428 memset(ipad, 0, block_size);
429 memset(opad, 0, block_size);
430 PMD_DRV_LOG(ERR, "ipad precompute failed");
435 * State len is a multiple of 8, so may be larger than the digest.
436 * Put the partial hash of opad state_len bytes after state1
438 *p_state_len = qat_hash_get_state1_size(hash_alg);
439 if (partial_hash_compute(hash_alg, opad, p_state_buf + *p_state_len)) {
440 memset(ipad, 0, block_size);
441 memset(opad, 0, block_size);
442 PMD_DRV_LOG(ERR, "opad precompute failed");
446 /* don't leave data lying around */
447 memset(ipad, 0, block_size);
448 memset(opad, 0, block_size);
452 void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,
453 enum qat_crypto_proto_flag proto_flags)
455 PMD_INIT_FUNC_TRACE();
457 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
458 header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_LA;
459 header->comn_req_flags =
460 ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_64BIT_ADR,
461 QAT_COMN_PTR_TYPE_FLAT);
462 ICP_QAT_FW_LA_PARTIAL_SET(header->serv_specif_flags,
463 ICP_QAT_FW_LA_PARTIAL_NONE);
464 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,
465 ICP_QAT_FW_CIPH_IV_16BYTE_DATA);
467 switch (proto_flags) {
468 case QAT_CRYPTO_PROTO_FLAG_NONE:
469 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
470 ICP_QAT_FW_LA_NO_PROTO);
472 case QAT_CRYPTO_PROTO_FLAG_CCM:
473 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
474 ICP_QAT_FW_LA_CCM_PROTO);
476 case QAT_CRYPTO_PROTO_FLAG_GCM:
477 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
478 ICP_QAT_FW_LA_GCM_PROTO);
480 case QAT_CRYPTO_PROTO_FLAG_SNOW3G:
481 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
482 ICP_QAT_FW_LA_SNOW_3G_PROTO);
484 case QAT_CRYPTO_PROTO_FLAG_ZUC:
485 ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(header->serv_specif_flags,
486 ICP_QAT_FW_LA_ZUC_3G_PROTO);
490 ICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,
491 ICP_QAT_FW_LA_NO_UPDATE_STATE);
492 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,
493 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
497 * Snow3G and ZUC should never use this function
498 * and set its protocol flag in both cipher and auth part of content
499 * descriptor building function
501 static enum qat_crypto_proto_flag
502 qat_get_crypto_proto_flag(uint16_t flags)
504 int proto = ICP_QAT_FW_LA_PROTO_GET(flags);
505 enum qat_crypto_proto_flag qat_proto_flag =
506 QAT_CRYPTO_PROTO_FLAG_NONE;
509 case ICP_QAT_FW_LA_GCM_PROTO:
510 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
512 case ICP_QAT_FW_LA_CCM_PROTO:
513 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;
517 return qat_proto_flag;
520 int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
522 uint32_t cipherkeylen)
524 struct icp_qat_hw_cipher_algo_blk *cipher;
525 struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
526 struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
527 struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
528 void *ptr = &req_tmpl->cd_ctrl;
529 struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
530 struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
531 enum icp_qat_hw_cipher_convert key_convert;
532 enum qat_crypto_proto_flag qat_proto_flag =
533 QAT_CRYPTO_PROTO_FLAG_NONE;
534 uint32_t total_key_size;
535 uint16_t cipher_offset, cd_size;
536 uint32_t wordIndex = 0;
537 uint32_t *temp_key = NULL;
538 PMD_INIT_FUNC_TRACE();
540 if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
541 cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
542 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
543 ICP_QAT_FW_SLICE_CIPHER);
544 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
545 ICP_QAT_FW_SLICE_DRAM_WR);
546 ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
547 ICP_QAT_FW_LA_NO_RET_AUTH_RES);
548 ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
549 ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
550 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
551 } else if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
552 cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
553 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
554 ICP_QAT_FW_SLICE_CIPHER);
555 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
556 ICP_QAT_FW_SLICE_AUTH);
557 ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,
558 ICP_QAT_FW_SLICE_AUTH);
559 ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl,
560 ICP_QAT_FW_SLICE_DRAM_WR);
561 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
562 } else if (cdesc->qat_cmd != ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
563 PMD_DRV_LOG(ERR, "Invalid param, must be a cipher command.");
567 if (cdesc->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE) {
569 * CTR Streaming ciphers are a special case. Decrypt = encrypt
570 * Overriding default values previously set
572 cdesc->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
573 key_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;
574 } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2
575 || cdesc->qat_cipher_alg ==
576 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)
577 key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
578 else if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT)
579 key_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;
581 key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
583 if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
584 total_key_size = ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ +
585 ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;
586 cipher_cd_ctrl->cipher_state_sz =
587 ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
588 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;
590 } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
591 total_key_size = ICP_QAT_HW_KASUMI_F8_KEY_SZ;
592 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_KASUMI_BLK_SZ >> 3;
593 cipher_cd_ctrl->cipher_padding_sz =
594 (2 * ICP_QAT_HW_KASUMI_BLK_SZ) >> 3;
595 } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) {
596 total_key_size = ICP_QAT_HW_3DES_KEY_SZ;
597 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_3DES_BLK_SZ >> 3;
599 qat_get_crypto_proto_flag(header->serv_specif_flags);
600 } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_DES) {
601 total_key_size = ICP_QAT_HW_DES_KEY_SZ;
602 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_DES_BLK_SZ >> 3;
604 qat_get_crypto_proto_flag(header->serv_specif_flags);
605 } else if (cdesc->qat_cipher_alg ==
606 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
607 total_key_size = ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ +
608 ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;
609 cipher_cd_ctrl->cipher_state_sz =
610 ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
611 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;
612 cdesc->min_qat_dev_gen = QAT_GEN2;
614 total_key_size = cipherkeylen;
615 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
617 qat_get_crypto_proto_flag(header->serv_specif_flags);
619 cipher_cd_ctrl->cipher_key_sz = total_key_size >> 3;
620 cipher_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);
621 cipher_cd_ctrl->cipher_cfg_offset = cipher_offset >> 3;
623 header->service_cmd_id = cdesc->qat_cmd;
624 qat_alg_init_common_hdr(header, qat_proto_flag);
626 cipher = (struct icp_qat_hw_cipher_algo_blk *)cdesc->cd_cur_ptr;
627 cipher->cipher_config.val =
628 ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,
629 cdesc->qat_cipher_alg, key_convert,
632 if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
633 temp_key = (uint32_t *)(cdesc->cd_cur_ptr +
634 sizeof(struct icp_qat_hw_cipher_config)
636 memcpy(cipher->key, cipherkey, cipherkeylen);
637 memcpy(temp_key, cipherkey, cipherkeylen);
639 /* XOR Key with KASUMI F8 key modifier at 4 bytes level */
640 for (wordIndex = 0; wordIndex < (cipherkeylen >> 2);
642 temp_key[wordIndex] ^= KASUMI_F8_KEY_MODIFIER_4_BYTES;
644 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
645 cipherkeylen + cipherkeylen;
647 memcpy(cipher->key, cipherkey, cipherkeylen);
648 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
652 if (total_key_size > cipherkeylen) {
653 uint32_t padding_size = total_key_size-cipherkeylen;
654 if ((cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES)
655 && (cipherkeylen == QAT_3DES_KEY_SZ_OPT2))
656 /* K3 not provided so use K1 = K3*/
657 memcpy(cdesc->cd_cur_ptr, cipherkey, padding_size);
659 memset(cdesc->cd_cur_ptr, 0, padding_size);
660 cdesc->cd_cur_ptr += padding_size;
662 cd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;
663 cd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;
668 int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
673 unsigned int operation)
675 struct icp_qat_hw_auth_setup *hash;
676 struct icp_qat_hw_cipher_algo_blk *cipherconfig;
677 struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
678 struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
679 struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
680 void *ptr = &req_tmpl->cd_ctrl;
681 struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
682 struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
683 struct icp_qat_fw_la_auth_req_params *auth_param =
684 (struct icp_qat_fw_la_auth_req_params *)
685 ((char *)&req_tmpl->serv_specif_rqpars +
686 sizeof(struct icp_qat_fw_la_cipher_req_params));
687 uint16_t state1_size = 0, state2_size = 0;
688 uint16_t hash_offset, cd_size;
689 uint32_t *aad_len = NULL;
690 uint32_t wordIndex = 0;
692 enum qat_crypto_proto_flag qat_proto_flag =
693 QAT_CRYPTO_PROTO_FLAG_NONE;
695 PMD_INIT_FUNC_TRACE();
697 if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
698 ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,
699 ICP_QAT_FW_SLICE_AUTH);
700 ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl,
701 ICP_QAT_FW_SLICE_DRAM_WR);
702 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
703 } else if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
704 ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,
705 ICP_QAT_FW_SLICE_AUTH);
706 ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl,
707 ICP_QAT_FW_SLICE_CIPHER);
708 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
709 ICP_QAT_FW_SLICE_CIPHER);
710 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
711 ICP_QAT_FW_SLICE_DRAM_WR);
712 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
713 } else if (cdesc->qat_cmd != ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
714 PMD_DRV_LOG(ERR, "Invalid param, must be a hash command.");
718 if (operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
719 ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
720 ICP_QAT_FW_LA_NO_RET_AUTH_RES);
721 ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
722 ICP_QAT_FW_LA_CMP_AUTH_RES);
723 cdesc->auth_op = ICP_QAT_HW_AUTH_VERIFY;
725 ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
726 ICP_QAT_FW_LA_RET_AUTH_RES);
727 ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
728 ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
729 cdesc->auth_op = ICP_QAT_HW_AUTH_GENERATE;
733 * Setup the inner hash config
735 hash_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);
736 hash = (struct icp_qat_hw_auth_setup *)cdesc->cd_cur_ptr;
737 hash->auth_config.reserved = 0;
738 hash->auth_config.config =
739 ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,
740 cdesc->qat_hash_alg, digestsize);
742 if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
743 || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
744 || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3)
745 hash->auth_counter.counter = 0;
747 hash->auth_counter.counter = rte_bswap32(
748 qat_hash_get_block_size(cdesc->qat_hash_alg));
750 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_auth_setup);
753 * cd_cur_ptr now points at the state1 information.
755 switch (cdesc->qat_hash_alg) {
756 case ICP_QAT_HW_AUTH_ALGO_SHA1:
757 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1,
758 authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
759 PMD_DRV_LOG(ERR, "(SHA)precompute failed");
762 state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
764 case ICP_QAT_HW_AUTH_ALGO_SHA224:
765 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
766 authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
767 PMD_DRV_LOG(ERR, "(SHA)precompute failed");
770 state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
772 case ICP_QAT_HW_AUTH_ALGO_SHA256:
773 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
774 authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
775 PMD_DRV_LOG(ERR, "(SHA)precompute failed");
778 state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
780 case ICP_QAT_HW_AUTH_ALGO_SHA384:
781 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
782 authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
783 PMD_DRV_LOG(ERR, "(SHA)precompute failed");
786 state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
788 case ICP_QAT_HW_AUTH_ALGO_SHA512:
789 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
790 authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
791 PMD_DRV_LOG(ERR, "(SHA)precompute failed");
794 state2_size = ICP_QAT_HW_SHA512_STATE2_SZ;
796 case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
797 state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
798 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
799 authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
801 PMD_DRV_LOG(ERR, "(XCBC)precompute failed");
805 case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
806 case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
807 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
808 state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
809 if (qat_alg_do_precomputes(cdesc->qat_hash_alg,
810 authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
812 PMD_DRV_LOG(ERR, "(GCM)precompute failed");
816 * Write (the length of AAD) into bytes 16-19 of state2
817 * in big-endian format. This field is 8 bytes
819 auth_param->u2.aad_sz =
820 RTE_ALIGN_CEIL(aad_length, 16);
821 auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
823 aad_len = (uint32_t *)(cdesc->cd_cur_ptr +
824 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
825 ICP_QAT_HW_GALOIS_H_SZ);
826 *aad_len = rte_bswap32(aad_length);
827 cdesc->aad_len = aad_length;
829 case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
830 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;
831 state1_size = qat_hash_get_state1_size(
832 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2);
833 state2_size = ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ;
834 memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size);
836 cipherconfig = (struct icp_qat_hw_cipher_algo_blk *)
837 (cdesc->cd_cur_ptr + state1_size + state2_size);
838 cipherconfig->cipher_config.val =
839 ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_ECB_MODE,
840 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2,
841 ICP_QAT_HW_CIPHER_KEY_CONVERT,
842 ICP_QAT_HW_CIPHER_ENCRYPT);
843 memcpy(cipherconfig->key, authkey, authkeylen);
844 memset(cipherconfig->key + authkeylen,
845 0, ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ);
846 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
847 authkeylen + ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;
848 auth_param->hash_state_sz = ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
850 case ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:
851 hash->auth_config.config =
852 ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE0,
853 cdesc->qat_hash_alg, digestsize);
854 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;
855 state1_size = qat_hash_get_state1_size(
856 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3);
857 state2_size = ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ;
858 memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size
859 + ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ);
861 memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
862 cdesc->cd_cur_ptr += state1_size + state2_size
863 + ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;
864 auth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
865 cdesc->min_qat_dev_gen = QAT_GEN2;
868 case ICP_QAT_HW_AUTH_ALGO_MD5:
869 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
870 authkey, authkeylen, cdesc->cd_cur_ptr,
872 PMD_DRV_LOG(ERR, "(MD5)precompute failed");
875 state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
877 case ICP_QAT_HW_AUTH_ALGO_NULL:
878 state1_size = qat_hash_get_state1_size(
879 ICP_QAT_HW_AUTH_ALGO_NULL);
880 state2_size = ICP_QAT_HW_NULL_STATE2_SZ;
882 case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
883 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;
884 state1_size = qat_hash_get_state1_size(
885 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC);
886 state2_size = ICP_QAT_HW_AES_CBC_MAC_KEY_SZ +
887 ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ;
889 if (aad_length > 0) {
890 aad_length += ICP_QAT_HW_CCM_AAD_B0_LEN +
891 ICP_QAT_HW_CCM_AAD_LEN_INFO;
892 auth_param->u2.aad_sz =
893 RTE_ALIGN_CEIL(aad_length,
894 ICP_QAT_HW_CCM_AAD_ALIGNMENT);
896 auth_param->u2.aad_sz = ICP_QAT_HW_CCM_AAD_B0_LEN;
899 cdesc->aad_len = aad_length;
900 hash->auth_counter.counter = 0;
902 hash_cd_ctrl->outer_prefix_sz = digestsize;
903 auth_param->hash_state_sz = digestsize;
905 memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
907 case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
908 state1_size = qat_hash_get_state1_size(
909 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9);
910 state2_size = ICP_QAT_HW_KASUMI_F9_STATE2_SZ;
911 memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size);
912 pTempKey = (uint32_t *)(cdesc->cd_cur_ptr + state1_size
915 * The Inner Hash Initial State2 block must contain IK
916 * (Initialisation Key), followed by IK XOR-ed with KM
917 * (Key Modifier): IK||(IK^KM).
919 /* write the auth key */
920 memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
921 /* initialise temp key with auth key */
922 memcpy(pTempKey, authkey, authkeylen);
923 /* XOR Key with KASUMI F9 key modifier at 4 bytes level */
924 for (wordIndex = 0; wordIndex < (authkeylen >> 2); wordIndex++)
925 pTempKey[wordIndex] ^= KASUMI_F9_KEY_MODIFIER_4_BYTES;
928 PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
932 /* Request template setup */
933 qat_alg_init_common_hdr(header, qat_proto_flag);
934 header->service_cmd_id = cdesc->qat_cmd;
936 /* Auth CD config setup */
937 hash_cd_ctrl->hash_cfg_offset = hash_offset >> 3;
938 hash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;
939 hash_cd_ctrl->inner_res_sz = digestsize;
940 hash_cd_ctrl->final_sz = digestsize;
941 hash_cd_ctrl->inner_state1_sz = state1_size;
942 auth_param->auth_res_sz = digestsize;
944 hash_cd_ctrl->inner_state2_sz = state2_size;
945 hash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +
946 ((sizeof(struct icp_qat_hw_auth_setup) +
947 RTE_ALIGN_CEIL(hash_cd_ctrl->inner_state1_sz, 8))
950 cdesc->cd_cur_ptr += state1_size + state2_size;
951 cd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;
953 cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
954 cd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;
959 int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
962 case ICP_QAT_HW_AES_128_KEY_SZ:
963 *alg = ICP_QAT_HW_CIPHER_ALGO_AES128;
965 case ICP_QAT_HW_AES_192_KEY_SZ:
966 *alg = ICP_QAT_HW_CIPHER_ALGO_AES192;
968 case ICP_QAT_HW_AES_256_KEY_SZ:
969 *alg = ICP_QAT_HW_CIPHER_ALGO_AES256;
977 int qat_alg_validate_aes_docsisbpi_key(int key_len,
978 enum icp_qat_hw_cipher_algo *alg)
981 case ICP_QAT_HW_AES_128_KEY_SZ:
982 *alg = ICP_QAT_HW_CIPHER_ALGO_AES128;
990 int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
993 case ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ:
994 *alg = ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2;
1002 int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1005 case ICP_QAT_HW_KASUMI_KEY_SZ:
1006 *alg = ICP_QAT_HW_CIPHER_ALGO_KASUMI;
1014 int qat_alg_validate_des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1017 case ICP_QAT_HW_DES_KEY_SZ:
1018 *alg = ICP_QAT_HW_CIPHER_ALGO_DES;
1026 int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1029 case QAT_3DES_KEY_SZ_OPT1:
1030 case QAT_3DES_KEY_SZ_OPT2:
1031 *alg = ICP_QAT_HW_CIPHER_ALGO_3DES;
1039 int qat_alg_validate_zuc_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1042 case ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ:
1043 *alg = ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3;