4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
177 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
179 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
181 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
198 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
200 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
202 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
218 { /* AES GCM (AUTH) */
219 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
221 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
223 .algo = RTE_CRYPTO_AUTH_AES_GCM,
243 { /* AES GMAC (AUTH) */
244 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
246 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
248 .algo = RTE_CRYPTO_AUTH_AES_GMAC,
268 { /* SNOW 3G (UIA2) */
269 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
271 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
273 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
293 { /* AES GCM (CIPHER) */
294 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
296 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
298 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
314 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
316 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
318 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
333 { /* SNOW 3G (UEA2) */
334 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
336 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
338 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
354 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
356 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
358 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
374 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
376 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
378 .algo = RTE_CRYPTO_AUTH_NULL,
394 { /* NULL (CIPHER) */
395 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
397 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
399 .algo = RTE_CRYPTO_CIPHER_NULL,
415 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
417 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
419 .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
435 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
437 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
439 .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
460 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
462 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
464 .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
480 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
482 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
484 .algo = RTE_CRYPTO_CIPHER_3DES_CTR,
500 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
502 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
504 .algo = RTE_CRYPTO_CIPHER_DES_CBC,
519 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
522 static inline uint32_t
523 adf_modulo(uint32_t data, uint32_t shift);
526 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
527 struct qat_crypto_op_cookie *qat_op_cookie);
529 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
532 struct qat_session *sess = session;
533 phys_addr_t cd_paddr;
535 PMD_INIT_FUNC_TRACE();
537 cd_paddr = sess->cd_paddr;
538 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
539 sess->cd_paddr = cd_paddr;
541 PMD_DRV_LOG(ERR, "NULL session");
545 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
548 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
549 return ICP_QAT_FW_LA_CMD_CIPHER;
551 /* Authentication Only */
552 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
553 return ICP_QAT_FW_LA_CMD_AUTH;
555 if (xform->next == NULL)
558 /* Cipher then Authenticate */
559 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
560 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
561 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
563 /* Authenticate then Cipher */
564 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
565 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
566 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
571 static struct rte_crypto_auth_xform *
572 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
575 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
584 static struct rte_crypto_cipher_xform *
585 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
588 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
589 return &xform->cipher;
597 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
598 struct rte_crypto_sym_xform *xform, void *session_private)
600 struct qat_pmd_private *internals = dev->data->dev_private;
602 struct qat_session *session = session_private;
604 struct rte_crypto_cipher_xform *cipher_xform = NULL;
606 /* Get cipher xform from crypto xform chain */
607 cipher_xform = qat_get_cipher_xform(xform);
609 switch (cipher_xform->algo) {
610 case RTE_CRYPTO_CIPHER_AES_CBC:
611 if (qat_alg_validate_aes_key(cipher_xform->key.length,
612 &session->qat_cipher_alg) != 0) {
613 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
616 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
618 case RTE_CRYPTO_CIPHER_AES_GCM:
619 if (qat_alg_validate_aes_key(cipher_xform->key.length,
620 &session->qat_cipher_alg) != 0) {
621 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
624 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
626 case RTE_CRYPTO_CIPHER_AES_CTR:
627 if (qat_alg_validate_aes_key(cipher_xform->key.length,
628 &session->qat_cipher_alg) != 0) {
629 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
632 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
634 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
635 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
636 &session->qat_cipher_alg) != 0) {
637 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
640 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
642 case RTE_CRYPTO_CIPHER_NULL:
643 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
645 case RTE_CRYPTO_CIPHER_KASUMI_F8:
646 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
647 &session->qat_cipher_alg) != 0) {
648 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
651 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
653 case RTE_CRYPTO_CIPHER_3DES_CBC:
654 if (qat_alg_validate_3des_key(cipher_xform->key.length,
655 &session->qat_cipher_alg) != 0) {
656 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
659 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
661 case RTE_CRYPTO_CIPHER_DES_CBC:
662 if (qat_alg_validate_des_key(cipher_xform->key.length,
663 &session->qat_cipher_alg) != 0) {
664 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
667 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
669 case RTE_CRYPTO_CIPHER_3DES_CTR:
670 if (qat_alg_validate_3des_key(cipher_xform->key.length,
671 &session->qat_cipher_alg) != 0) {
672 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
675 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
677 case RTE_CRYPTO_CIPHER_3DES_ECB:
678 case RTE_CRYPTO_CIPHER_AES_ECB:
679 case RTE_CRYPTO_CIPHER_AES_CCM:
680 case RTE_CRYPTO_CIPHER_AES_F8:
681 case RTE_CRYPTO_CIPHER_AES_XTS:
682 case RTE_CRYPTO_CIPHER_ARC4:
683 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
684 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
688 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
693 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
694 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
696 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
698 if (qat_alg_aead_session_create_content_desc_cipher(session,
699 cipher_xform->key.data,
700 cipher_xform->key.length))
706 rte_mempool_put(internals->sess_mp, session);
712 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
713 struct rte_crypto_sym_xform *xform, void *session_private)
715 struct qat_pmd_private *internals = dev->data->dev_private;
717 struct qat_session *session = session_private;
721 PMD_INIT_FUNC_TRACE();
723 /* Get requested QAT command id */
724 qat_cmd_id = qat_get_cmd_id(xform);
725 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
726 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
729 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
730 switch (session->qat_cmd) {
731 case ICP_QAT_FW_LA_CMD_CIPHER:
732 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
734 case ICP_QAT_FW_LA_CMD_AUTH:
735 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
737 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
738 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
739 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
741 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
742 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
743 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
745 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
746 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
747 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
748 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
749 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
750 case ICP_QAT_FW_LA_CMD_MGF1:
751 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
752 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
753 case ICP_QAT_FW_LA_CMD_DELIMITER:
754 PMD_DRV_LOG(ERR, "Unsupported Service %u",
758 PMD_DRV_LOG(ERR, "Unsupported Service %u",
765 rte_mempool_put(internals->sess_mp, session);
770 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
771 struct rte_crypto_sym_xform *xform,
772 struct qat_session *session_private)
775 struct qat_pmd_private *internals = dev->data->dev_private;
776 struct qat_session *session = session_private;
777 struct rte_crypto_auth_xform *auth_xform = NULL;
778 struct rte_crypto_cipher_xform *cipher_xform = NULL;
779 auth_xform = qat_get_auth_xform(xform);
781 switch (auth_xform->algo) {
782 case RTE_CRYPTO_AUTH_SHA1_HMAC:
783 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
785 case RTE_CRYPTO_AUTH_SHA224_HMAC:
786 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
788 case RTE_CRYPTO_AUTH_SHA256_HMAC:
789 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
791 case RTE_CRYPTO_AUTH_SHA384_HMAC:
792 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
794 case RTE_CRYPTO_AUTH_SHA512_HMAC:
795 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
797 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
798 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
800 case RTE_CRYPTO_AUTH_AES_GCM:
801 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
803 case RTE_CRYPTO_AUTH_AES_GMAC:
804 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
806 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
807 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
809 case RTE_CRYPTO_AUTH_MD5_HMAC:
810 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
812 case RTE_CRYPTO_AUTH_NULL:
813 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
815 case RTE_CRYPTO_AUTH_KASUMI_F9:
816 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
818 case RTE_CRYPTO_AUTH_SHA1:
819 case RTE_CRYPTO_AUTH_SHA256:
820 case RTE_CRYPTO_AUTH_SHA512:
821 case RTE_CRYPTO_AUTH_SHA224:
822 case RTE_CRYPTO_AUTH_SHA384:
823 case RTE_CRYPTO_AUTH_MD5:
824 case RTE_CRYPTO_AUTH_AES_CCM:
825 case RTE_CRYPTO_AUTH_AES_CMAC:
826 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
827 case RTE_CRYPTO_AUTH_ZUC_EIA3:
828 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
832 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
836 cipher_xform = qat_get_cipher_xform(xform);
838 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
839 (session->qat_hash_alg ==
840 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
841 if (qat_alg_aead_session_create_content_desc_auth(session,
842 cipher_xform->key.data,
843 cipher_xform->key.length,
844 auth_xform->add_auth_data_length,
845 auth_xform->digest_length,
849 if (qat_alg_aead_session_create_content_desc_auth(session,
850 auth_xform->key.data,
851 auth_xform->key.length,
852 auth_xform->add_auth_data_length,
853 auth_xform->digest_length,
860 if (internals->sess_mp != NULL)
861 rte_mempool_put(internals->sess_mp, session);
865 unsigned qat_crypto_sym_get_session_private_size(
866 struct rte_cryptodev *dev __rte_unused)
868 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
872 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
875 register struct qat_queue *queue;
876 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
877 register uint32_t nb_ops_sent = 0;
878 register struct rte_crypto_op **cur_op = ops;
880 uint16_t nb_ops_possible = nb_ops;
881 register uint8_t *base_addr;
882 register uint32_t tail;
885 if (unlikely(nb_ops == 0))
888 /* read params used a lot in main loop into registers */
889 queue = &(tmp_qp->tx_q);
890 base_addr = (uint8_t *)queue->base_addr;
893 /* Find how many can actually fit on the ring */
894 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
895 - queue->max_inflights;
897 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
898 nb_ops_possible = nb_ops - overflow;
899 if (nb_ops_possible == 0)
903 while (nb_ops_sent != nb_ops_possible) {
904 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
905 tmp_qp->op_cookies[tail / queue->msg_size]);
907 tmp_qp->stats.enqueue_err_count++;
909 * This message cannot be enqueued,
910 * decrease number of ops that wasnt sent
912 rte_atomic16_sub(&tmp_qp->inflights16,
913 nb_ops_possible - nb_ops_sent);
914 if (nb_ops_sent == 0)
919 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
924 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
925 queue->hw_queue_number, tail);
927 tmp_qp->stats.enqueued_count += nb_ops_sent;
932 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
935 struct qat_queue *queue;
936 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
937 uint32_t msg_counter = 0;
938 struct rte_crypto_op *rx_op;
939 struct icp_qat_fw_comn_resp *resp_msg;
941 queue = &(tmp_qp->rx_q);
942 resp_msg = (struct icp_qat_fw_comn_resp *)
943 ((uint8_t *)queue->base_addr + queue->head);
945 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
946 msg_counter != nb_ops) {
947 rx_op = (struct rte_crypto_op *)(uintptr_t)
948 (resp_msg->opaque_data);
950 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
951 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
952 sizeof(struct icp_qat_fw_comn_resp));
954 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
955 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
956 resp_msg->comn_hdr.comn_status)) {
957 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
959 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
961 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
962 queue->head = adf_modulo(queue->head +
964 ADF_RING_SIZE_MODULO(queue->queue_size));
965 resp_msg = (struct icp_qat_fw_comn_resp *)
966 ((uint8_t *)queue->base_addr +
972 if (msg_counter > 0) {
973 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
974 queue->hw_bundle_number,
975 queue->hw_queue_number, queue->head);
976 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
977 tmp_qp->stats.dequeued_count += msg_counter;
983 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
984 struct qat_alg_buf_list *list, uint32_t data_len)
988 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
989 buff_start + rte_pktmbuf_data_len(buf);
991 list->bufers[0].addr = buff_start;
992 list->bufers[0].resrvd = 0;
993 list->bufers[0].len = buf_len;
995 if (data_len <= buf_len) {
997 list->bufers[0].len = data_len;
1003 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1004 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1006 QAT_SGL_MAX_NUMBER);
1010 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1011 list->bufers[nr].resrvd = 0;
1012 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1014 buf_len += list->bufers[nr].len;
1017 if (buf_len > data_len) {
1018 list->bufers[nr].len -=
1024 list->num_bufs = nr;
1030 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1031 struct qat_crypto_op_cookie *qat_op_cookie)
1034 struct qat_session *ctx;
1035 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1036 struct icp_qat_fw_la_auth_req_params *auth_param;
1037 register struct icp_qat_fw_la_bulk_req *qat_req;
1038 uint8_t do_auth = 0, do_cipher = 0;
1039 uint32_t cipher_len = 0, cipher_ofs = 0;
1040 uint32_t auth_len = 0, auth_ofs = 0;
1041 uint32_t min_ofs = 0;
1042 uint64_t src_buf_start = 0, dst_buf_start = 0;
1046 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1047 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1048 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1049 "operation requests, op (%p) is not a "
1050 "symmetric operation.", op);
1054 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
1055 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1056 " requests, op (%p) is sessionless.", op);
1060 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
1061 PMD_DRV_LOG(ERR, "Session was not created for this device");
1065 ctx = (struct qat_session *)op->sym->session->_private;
1066 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1067 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1068 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1069 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1070 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1072 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1073 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1076 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1079 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1086 if (ctx->qat_cipher_alg ==
1087 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1088 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
1091 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1092 || (cipher_param->cipher_offset
1093 % BYTE_LENGTH != 0))) {
1095 "SNOW3G/KASUMI in QAT PMD only supports byte aligned values");
1096 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1099 cipher_len = op->sym->cipher.data.length >> 3;
1100 cipher_ofs = op->sym->cipher.data.offset >> 3;
1103 cipher_len = op->sym->cipher.data.length;
1104 cipher_ofs = op->sym->cipher.data.offset;
1107 /* copy IV into request if it fits */
1108 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
1109 sizeof(cipher_param->u.cipher_IV_array))) {
1110 rte_memcpy(cipher_param->u.cipher_IV_array,
1111 op->sym->cipher.iv.data,
1112 op->sym->cipher.iv.length);
1114 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1115 qat_req->comn_hdr.serv_specif_flags,
1116 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1117 cipher_param->u.s.cipher_IV_ptr =
1118 op->sym->cipher.iv.phys_addr;
1120 min_ofs = cipher_ofs;
1125 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1126 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1127 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1128 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1130 "For SNOW3G/KASUMI, QAT PMD only supports byte aligned values");
1131 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1134 auth_ofs = op->sym->auth.data.offset >> 3;
1135 auth_len = op->sym->auth.data.length >> 3;
1137 if (ctx->qat_hash_alg ==
1138 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1140 auth_len = auth_len + auth_ofs + 1 -
1141 ICP_QAT_HW_KASUMI_BLK_SZ;
1142 auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1144 auth_len = auth_len + auth_ofs + 1;
1150 auth_ofs = op->sym->auth.data.offset;
1151 auth_len = op->sym->auth.data.length;
1155 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1157 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1161 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1164 /* adjust for chain case */
1165 if (do_cipher && do_auth)
1166 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1168 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1171 if (unlikely(op->sym->m_dst != NULL)) {
1172 /* Out-of-place operation (OOP)
1173 * Don't align DMA start. DMA the minimum data-set
1174 * so as not to overwrite data in dest buffer
1177 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1179 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1182 /* In-place operation
1183 * Start DMA at nearest aligned address below min_ofs
1186 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1187 & QAT_64_BTYE_ALIGN_MASK;
1189 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1190 rte_pktmbuf_headroom(op->sym->m_src))
1192 /* alignment has pushed addr ahead of start of mbuf
1193 * so revert and take the performance hit
1196 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1199 dst_buf_start = src_buf_start;
1203 cipher_param->cipher_offset =
1204 (uint32_t)rte_pktmbuf_mtophys_offset(
1205 op->sym->m_src, cipher_ofs) - src_buf_start;
1206 cipher_param->cipher_length = cipher_len;
1208 cipher_param->cipher_offset = 0;
1209 cipher_param->cipher_length = 0;
1212 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1213 op->sym->m_src, auth_ofs) - src_buf_start;
1214 auth_param->auth_len = auth_len;
1216 auth_param->auth_off = 0;
1217 auth_param->auth_len = 0;
1219 qat_req->comn_mid.dst_length =
1220 qat_req->comn_mid.src_length =
1221 (cipher_param->cipher_offset + cipher_param->cipher_length)
1222 > (auth_param->auth_off + auth_param->auth_len) ?
1223 (cipher_param->cipher_offset + cipher_param->cipher_length)
1224 : (auth_param->auth_off + auth_param->auth_len);
1228 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1229 QAT_COMN_PTR_TYPE_SGL);
1230 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1231 &qat_op_cookie->qat_sgl_list_src,
1232 qat_req->comn_mid.src_length);
1234 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1238 if (likely(op->sym->m_dst == NULL))
1239 qat_req->comn_mid.dest_data_addr =
1240 qat_req->comn_mid.src_data_addr =
1241 qat_op_cookie->qat_sgl_src_phys_addr;
1243 ret = qat_sgl_fill_array(op->sym->m_dst,
1245 &qat_op_cookie->qat_sgl_list_dst,
1246 qat_req->comn_mid.dst_length);
1249 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1254 qat_req->comn_mid.src_data_addr =
1255 qat_op_cookie->qat_sgl_src_phys_addr;
1256 qat_req->comn_mid.dest_data_addr =
1257 qat_op_cookie->qat_sgl_dst_phys_addr;
1260 qat_req->comn_mid.src_data_addr = src_buf_start;
1261 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1264 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1265 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1266 if (op->sym->cipher.iv.length == 12) {
1268 * For GCM a 12 bit IV is allowed,
1269 * but we need to inform the f/w
1271 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1272 qat_req->comn_hdr.serv_specif_flags,
1273 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1275 if (op->sym->cipher.data.length == 0) {
1279 qat_req->comn_mid.dest_data_addr =
1280 qat_req->comn_mid.src_data_addr =
1281 op->sym->auth.aad.phys_addr;
1282 qat_req->comn_mid.dst_length =
1283 qat_req->comn_mid.src_length =
1284 rte_pktmbuf_data_len(op->sym->m_src);
1285 cipher_param->cipher_length = 0;
1286 cipher_param->cipher_offset = 0;
1287 auth_param->u1.aad_adr = 0;
1288 auth_param->auth_len = op->sym->auth.aad.length;
1289 auth_param->auth_off = op->sym->auth.data.offset;
1290 auth_param->u2.aad_sz = 0;
1294 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1295 rte_hexdump(stdout, "qat_req:", qat_req,
1296 sizeof(struct icp_qat_fw_la_bulk_req));
1297 rte_hexdump(stdout, "src_data:",
1298 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1299 rte_pktmbuf_data_len(op->sym->m_src));
1300 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
1301 op->sym->cipher.iv.length);
1302 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1303 op->sym->auth.digest.length);
1304 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1305 op->sym->auth.aad.length);
1310 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1312 uint32_t div = data >> shift;
1313 uint32_t mult = div << shift;
1318 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1320 struct rte_cryptodev_sym_session *sess = sym_sess;
1321 struct qat_session *s = (void *)sess->_private;
1323 PMD_INIT_FUNC_TRACE();
1324 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1325 offsetof(struct qat_session, cd) +
1326 offsetof(struct rte_cryptodev_sym_session, _private);
1329 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
1331 PMD_INIT_FUNC_TRACE();
1335 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1337 PMD_INIT_FUNC_TRACE();
1341 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1343 PMD_INIT_FUNC_TRACE();
1346 int qat_dev_close(struct rte_cryptodev *dev)
1350 PMD_INIT_FUNC_TRACE();
1352 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1353 ret = qat_crypto_sym_qp_release(dev, i);
1361 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
1362 struct rte_cryptodev_info *info)
1364 struct qat_pmd_private *internals = dev->data->dev_private;
1366 PMD_INIT_FUNC_TRACE();
1368 info->max_nb_queue_pairs =
1369 ADF_NUM_SYM_QPS_PER_BUNDLE *
1370 ADF_NUM_BUNDLES_PER_DEV;
1371 info->feature_flags = dev->feature_flags;
1372 info->capabilities = qat_pmd_capabilities;
1373 info->sym.max_nb_sessions = internals->max_nb_sessions;
1374 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1378 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1379 struct rte_cryptodev_stats *stats)
1382 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1384 PMD_INIT_FUNC_TRACE();
1385 if (stats == NULL) {
1386 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1389 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1390 if (qp[i] == NULL) {
1391 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1395 stats->enqueued_count += qp[i]->stats.enqueued_count;
1396 stats->dequeued_count += qp[i]->stats.enqueued_count;
1397 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1398 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
1402 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1405 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1407 PMD_INIT_FUNC_TRACE();
1408 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1409 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1410 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");