4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_malloc.h>
50 #include <rte_launch.h>
52 #include <rte_per_lcore.h>
53 #include <rte_lcore.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_mempool.h>
57 #include <rte_string_fns.h>
58 #include <rte_spinlock.h>
59 #include <rte_hexdump.h>
60 #include <rte_crypto_sym.h>
61 #include <rte_byteorder.h>
63 #include <rte_bus_pci.h>
65 #include <openssl/evp.h>
69 #include "qat_crypto.h"
70 #include "adf_transport_access_macros.h"
75 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
76 struct qat_pmd_private *internals) {
78 const struct rte_cryptodev_capabilities *capability;
80 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
81 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
82 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
85 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
88 if (capability->sym.cipher.algo == algo)
95 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
96 struct qat_pmd_private *internals) {
98 const struct rte_cryptodev_capabilities *capability;
100 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
101 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
102 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
105 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
108 if (capability->sym.auth.algo == algo)
114 /** Encrypt a single partial block
115 * Depends on openssl libcrypto
116 * Uses ECB+XOR to do CFB encryption, same result, more performant
119 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
120 uint8_t *iv, int ivlen, int srclen,
123 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
125 uint8_t encrypted_iv[16];
128 /* ECB method: encrypt the IV, then XOR this with plaintext */
129 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
131 goto cipher_encrypt_err;
133 for (i = 0; i < srclen; i++)
134 *(dst+i) = *(src+i)^(encrypted_iv[i]);
139 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
143 /** Decrypt a single partial block
144 * Depends on openssl libcrypto
145 * Uses ECB+XOR to do CFB encryption, same result, more performant
148 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
149 uint8_t *iv, int ivlen, int srclen,
152 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
154 uint8_t encrypted_iv[16];
157 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
158 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
160 goto cipher_decrypt_err;
162 for (i = 0; i < srclen; i++)
163 *(dst+i) = *(src+i)^(encrypted_iv[i]);
168 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
172 /** Creates a context in either AES or DES in ECB mode
173 * Depends on openssl libcrypto
176 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
177 enum rte_crypto_cipher_operation direction __rte_unused,
178 uint8_t *key, void **ctx)
180 const EVP_CIPHER *algo = NULL;
182 *ctx = EVP_CIPHER_CTX_new();
189 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
190 algo = EVP_des_ecb();
192 algo = EVP_aes_128_ecb();
194 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
195 if (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {
204 EVP_CIPHER_CTX_free(*ctx);
208 /** Frees a context previously created
209 * Depends on openssl libcrypto
212 bpi_cipher_ctx_free(void *bpi_ctx)
215 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
218 static inline uint32_t
219 adf_modulo(uint32_t data, uint32_t shift);
222 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
223 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
226 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
227 struct rte_cryptodev_sym_session *sess)
229 PMD_INIT_FUNC_TRACE();
230 uint8_t index = dev->driver_id;
231 void *sess_priv = get_session_private_data(sess, index);
232 struct qat_session *s = (struct qat_session *)sess_priv;
236 bpi_cipher_ctx_free(s->bpi_ctx);
237 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
238 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
239 set_session_private_data(sess, index, NULL);
240 rte_mempool_put(sess_mp, sess_priv);
245 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
248 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
249 return ICP_QAT_FW_LA_CMD_CIPHER;
251 /* Authentication Only */
252 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
253 return ICP_QAT_FW_LA_CMD_AUTH;
256 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
257 /* AES-GCM and AES-CCM works with different direction
258 * GCM first encrypts and generate hash where AES-CCM
259 * first generate hash and encrypts. Similar relation
260 * applies to decryption.
262 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
263 if (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)
264 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
266 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
268 if (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)
269 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
271 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
274 if (xform->next == NULL)
277 /* Cipher then Authenticate */
278 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
279 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
280 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
282 /* Authenticate then Cipher */
283 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
284 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
285 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
290 static struct rte_crypto_auth_xform *
291 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
294 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
303 static struct rte_crypto_cipher_xform *
304 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
307 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
308 return &xform->cipher;
317 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
318 struct rte_crypto_sym_xform *xform,
319 struct qat_session *session)
321 struct qat_pmd_private *internals = dev->data->dev_private;
322 struct rte_crypto_cipher_xform *cipher_xform = NULL;
325 /* Get cipher xform from crypto xform chain */
326 cipher_xform = qat_get_cipher_xform(xform);
328 session->cipher_iv.offset = cipher_xform->iv.offset;
329 session->cipher_iv.length = cipher_xform->iv.length;
331 switch (cipher_xform->algo) {
332 case RTE_CRYPTO_CIPHER_AES_CBC:
333 if (qat_alg_validate_aes_key(cipher_xform->key.length,
334 &session->qat_cipher_alg) != 0) {
335 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
339 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
341 case RTE_CRYPTO_CIPHER_AES_CTR:
342 if (qat_alg_validate_aes_key(cipher_xform->key.length,
343 &session->qat_cipher_alg) != 0) {
344 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
348 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
350 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
351 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
352 &session->qat_cipher_alg) != 0) {
353 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
357 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
359 case RTE_CRYPTO_CIPHER_NULL:
360 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
362 case RTE_CRYPTO_CIPHER_KASUMI_F8:
363 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
364 &session->qat_cipher_alg) != 0) {
365 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
369 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
371 case RTE_CRYPTO_CIPHER_3DES_CBC:
372 if (qat_alg_validate_3des_key(cipher_xform->key.length,
373 &session->qat_cipher_alg) != 0) {
374 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
378 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
380 case RTE_CRYPTO_CIPHER_DES_CBC:
381 if (qat_alg_validate_des_key(cipher_xform->key.length,
382 &session->qat_cipher_alg) != 0) {
383 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
387 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
389 case RTE_CRYPTO_CIPHER_3DES_CTR:
390 if (qat_alg_validate_3des_key(cipher_xform->key.length,
391 &session->qat_cipher_alg) != 0) {
392 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
396 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
398 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
399 ret = bpi_cipher_ctx_init(
402 cipher_xform->key.data,
405 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
408 if (qat_alg_validate_des_key(cipher_xform->key.length,
409 &session->qat_cipher_alg) != 0) {
410 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
414 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
416 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
417 ret = bpi_cipher_ctx_init(
420 cipher_xform->key.data,
423 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
426 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
427 &session->qat_cipher_alg) != 0) {
428 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
432 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
434 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
435 if (!qat_is_cipher_alg_supported(
436 cipher_xform->algo, internals)) {
437 PMD_DRV_LOG(ERR, "%s not supported on this device",
438 rte_crypto_cipher_algorithm_strings
439 [cipher_xform->algo]);
443 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
444 &session->qat_cipher_alg) != 0) {
445 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
449 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
451 case RTE_CRYPTO_CIPHER_3DES_ECB:
452 case RTE_CRYPTO_CIPHER_AES_ECB:
453 case RTE_CRYPTO_CIPHER_AES_F8:
454 case RTE_CRYPTO_CIPHER_AES_XTS:
455 case RTE_CRYPTO_CIPHER_ARC4:
456 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
461 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
467 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
468 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
470 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
472 if (qat_alg_aead_session_create_content_desc_cipher(session,
473 cipher_xform->key.data,
474 cipher_xform->key.length)) {
482 if (session->bpi_ctx) {
483 bpi_cipher_ctx_free(session->bpi_ctx);
484 session->bpi_ctx = NULL;
490 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
491 struct rte_crypto_sym_xform *xform,
492 struct rte_cryptodev_sym_session *sess,
493 struct rte_mempool *mempool)
495 void *sess_private_data;
498 if (rte_mempool_get(mempool, &sess_private_data)) {
500 "Couldn't get object from session mempool");
504 ret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);
506 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
507 "session parameters");
509 /* Return session to mempool */
510 rte_mempool_put(mempool, sess_private_data);
514 set_session_private_data(sess, dev->driver_id,
521 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
522 struct rte_crypto_sym_xform *xform, void *session_private)
524 struct qat_session *session = session_private;
528 PMD_INIT_FUNC_TRACE();
530 /* Set context descriptor physical address */
531 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
532 offsetof(struct qat_session, cd);
534 session->min_qat_dev_gen = QAT_GEN1;
536 /* Get requested QAT command id */
537 qat_cmd_id = qat_get_cmd_id(xform);
538 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
539 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
542 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
543 switch (session->qat_cmd) {
544 case ICP_QAT_FW_LA_CMD_CIPHER:
545 ret = qat_crypto_sym_configure_session_cipher(dev, xform, session);
549 case ICP_QAT_FW_LA_CMD_AUTH:
550 ret = qat_crypto_sym_configure_session_auth(dev, xform, session);
554 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
555 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
556 ret = qat_crypto_sym_configure_session_aead(xform,
561 ret = qat_crypto_sym_configure_session_cipher(dev,
565 ret = qat_crypto_sym_configure_session_auth(dev,
571 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
572 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
573 ret = qat_crypto_sym_configure_session_aead(xform,
578 ret = qat_crypto_sym_configure_session_auth(dev,
582 ret = qat_crypto_sym_configure_session_cipher(dev,
588 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
589 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
590 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
591 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
592 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
593 case ICP_QAT_FW_LA_CMD_MGF1:
594 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
595 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
596 case ICP_QAT_FW_LA_CMD_DELIMITER:
597 PMD_DRV_LOG(ERR, "Unsupported Service %u",
601 PMD_DRV_LOG(ERR, "Unsupported Service %u",
610 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
611 struct rte_crypto_sym_xform *xform,
612 struct qat_session *session)
614 struct rte_crypto_auth_xform *auth_xform = NULL;
615 struct qat_pmd_private *internals = dev->data->dev_private;
616 auth_xform = qat_get_auth_xform(xform);
617 uint8_t *key_data = auth_xform->key.data;
618 uint8_t key_length = auth_xform->key.length;
620 switch (auth_xform->algo) {
621 case RTE_CRYPTO_AUTH_SHA1_HMAC:
622 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
624 case RTE_CRYPTO_AUTH_SHA224_HMAC:
625 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
627 case RTE_CRYPTO_AUTH_SHA256_HMAC:
628 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
630 case RTE_CRYPTO_AUTH_SHA384_HMAC:
631 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
633 case RTE_CRYPTO_AUTH_SHA512_HMAC:
634 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
636 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
637 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
639 case RTE_CRYPTO_AUTH_AES_GMAC:
640 if (qat_alg_validate_aes_key(auth_xform->key.length,
641 &session->qat_cipher_alg) != 0) {
642 PMD_DRV_LOG(ERR, "Invalid AES key size");
645 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
646 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
649 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
650 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
652 case RTE_CRYPTO_AUTH_MD5_HMAC:
653 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
655 case RTE_CRYPTO_AUTH_NULL:
656 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
658 case RTE_CRYPTO_AUTH_KASUMI_F9:
659 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
661 case RTE_CRYPTO_AUTH_ZUC_EIA3:
662 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
663 PMD_DRV_LOG(ERR, "%s not supported on this device",
664 rte_crypto_auth_algorithm_strings
668 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
670 case RTE_CRYPTO_AUTH_SHA1:
671 case RTE_CRYPTO_AUTH_SHA256:
672 case RTE_CRYPTO_AUTH_SHA512:
673 case RTE_CRYPTO_AUTH_SHA224:
674 case RTE_CRYPTO_AUTH_SHA384:
675 case RTE_CRYPTO_AUTH_MD5:
676 case RTE_CRYPTO_AUTH_AES_CMAC:
677 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
678 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
682 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
687 session->auth_iv.offset = auth_xform->iv.offset;
688 session->auth_iv.length = auth_xform->iv.length;
690 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
691 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
692 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
693 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
695 * It needs to create cipher desc content first,
696 * then authentication
698 if (qat_alg_aead_session_create_content_desc_cipher(session,
699 auth_xform->key.data,
700 auth_xform->key.length))
703 if (qat_alg_aead_session_create_content_desc_auth(session,
707 auth_xform->digest_length,
711 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
712 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
714 * It needs to create authentication desc content first,
717 if (qat_alg_aead_session_create_content_desc_auth(session,
721 auth_xform->digest_length,
725 if (qat_alg_aead_session_create_content_desc_cipher(session,
726 auth_xform->key.data,
727 auth_xform->key.length))
730 /* Restore to authentication only only */
731 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
733 if (qat_alg_aead_session_create_content_desc_auth(session,
737 auth_xform->digest_length,
742 session->digest_length = auth_xform->digest_length;
747 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
748 struct qat_session *session)
750 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
751 enum rte_crypto_auth_operation crypto_operation;
754 * Store AEAD IV parameters as cipher IV,
755 * to avoid unnecessary memory usage
757 session->cipher_iv.offset = xform->aead.iv.offset;
758 session->cipher_iv.length = xform->aead.iv.length;
760 switch (aead_xform->algo) {
761 case RTE_CRYPTO_AEAD_AES_GCM:
762 if (qat_alg_validate_aes_key(aead_xform->key.length,
763 &session->qat_cipher_alg) != 0) {
764 PMD_DRV_LOG(ERR, "Invalid AES key size");
767 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
768 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
770 case RTE_CRYPTO_AEAD_AES_CCM:
771 if (qat_alg_validate_aes_key(aead_xform->key.length,
772 &session->qat_cipher_alg) != 0) {
773 PMD_DRV_LOG(ERR, "Invalid AES key size");
776 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
777 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;
780 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
785 if ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
786 aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||
787 (aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
788 aead_xform->algo == RTE_CRYPTO_AEAD_AES_CCM)) {
789 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
791 * It needs to create cipher desc content first,
792 * then authentication
795 crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
796 RTE_CRYPTO_AUTH_OP_GENERATE : RTE_CRYPTO_AUTH_OP_VERIFY;
798 if (qat_alg_aead_session_create_content_desc_cipher(session,
799 aead_xform->key.data,
800 aead_xform->key.length))
803 if (qat_alg_aead_session_create_content_desc_auth(session,
804 aead_xform->key.data,
805 aead_xform->key.length,
806 aead_xform->aad_length,
807 aead_xform->digest_length,
811 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
813 * It needs to create authentication desc content first,
817 crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
818 RTE_CRYPTO_AUTH_OP_VERIFY : RTE_CRYPTO_AUTH_OP_GENERATE;
820 if (qat_alg_aead_session_create_content_desc_auth(session,
821 aead_xform->key.data,
822 aead_xform->key.length,
823 aead_xform->aad_length,
824 aead_xform->digest_length,
828 if (qat_alg_aead_session_create_content_desc_cipher(session,
829 aead_xform->key.data,
830 aead_xform->key.length))
834 session->digest_length = aead_xform->digest_length;
838 unsigned qat_crypto_sym_get_session_private_size(
839 struct rte_cryptodev *dev __rte_unused)
841 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
844 static inline uint32_t
845 qat_bpicipher_preprocess(struct qat_session *ctx,
846 struct rte_crypto_op *op)
848 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
849 struct rte_crypto_sym_op *sym_op = op->sym;
850 uint8_t last_block_len = block_len > 0 ?
851 sym_op->cipher.data.length % block_len : 0;
853 if (last_block_len &&
854 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
856 /* Decrypt last block */
857 uint8_t *last_block, *dst, *iv;
858 uint32_t last_block_offset = sym_op->cipher.data.offset +
859 sym_op->cipher.data.length - last_block_len;
860 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
861 uint8_t *, last_block_offset);
863 if (unlikely(sym_op->m_dst != NULL))
864 /* out-of-place operation (OOP) */
865 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
866 uint8_t *, last_block_offset);
870 if (last_block_len < sym_op->cipher.data.length)
871 /* use previous block ciphertext as IV */
872 iv = last_block - block_len;
874 /* runt block, i.e. less than one full block */
875 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
876 ctx->cipher_iv.offset);
878 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
879 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
881 if (sym_op->m_dst != NULL)
882 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
885 bpi_cipher_decrypt(last_block, dst, iv, block_len,
886 last_block_len, ctx->bpi_ctx);
887 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
888 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
890 if (sym_op->m_dst != NULL)
891 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
896 return sym_op->cipher.data.length - last_block_len;
899 static inline uint32_t
900 qat_bpicipher_postprocess(struct qat_session *ctx,
901 struct rte_crypto_op *op)
903 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
904 struct rte_crypto_sym_op *sym_op = op->sym;
905 uint8_t last_block_len = block_len > 0 ?
906 sym_op->cipher.data.length % block_len : 0;
908 if (last_block_len > 0 &&
909 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
911 /* Encrypt last block */
912 uint8_t *last_block, *dst, *iv;
913 uint32_t last_block_offset;
915 last_block_offset = sym_op->cipher.data.offset +
916 sym_op->cipher.data.length - last_block_len;
917 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
918 uint8_t *, last_block_offset);
920 if (unlikely(sym_op->m_dst != NULL))
921 /* out-of-place operation (OOP) */
922 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
923 uint8_t *, last_block_offset);
927 if (last_block_len < sym_op->cipher.data.length)
928 /* use previous block ciphertext as IV */
929 iv = dst - block_len;
931 /* runt block, i.e. less than one full block */
932 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
933 ctx->cipher_iv.offset);
935 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
936 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
938 if (sym_op->m_dst != NULL)
939 rte_hexdump(stdout, "BPI: dst before post-process:",
940 dst, last_block_len);
942 bpi_cipher_encrypt(last_block, dst, iv, block_len,
943 last_block_len, ctx->bpi_ctx);
944 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
945 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
947 if (sym_op->m_dst != NULL)
948 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
952 return sym_op->cipher.data.length - last_block_len;
956 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
957 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
958 q->hw_queue_number, q->tail);
959 q->nb_pending_requests = 0;
960 q->csr_tail = q->tail;
964 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
967 register struct qat_queue *queue;
968 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
969 register uint32_t nb_ops_sent = 0;
970 register struct rte_crypto_op **cur_op = ops;
972 uint16_t nb_ops_possible = nb_ops;
973 register uint8_t *base_addr;
974 register uint32_t tail;
977 if (unlikely(nb_ops == 0))
980 /* read params used a lot in main loop into registers */
981 queue = &(tmp_qp->tx_q);
982 base_addr = (uint8_t *)queue->base_addr;
985 /* Find how many can actually fit on the ring */
986 tmp_qp->inflights16 += nb_ops;
987 overflow = tmp_qp->inflights16 - queue->max_inflights;
989 tmp_qp->inflights16 -= overflow;
990 nb_ops_possible = nb_ops - overflow;
991 if (nb_ops_possible == 0)
995 while (nb_ops_sent != nb_ops_possible) {
996 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
997 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
999 tmp_qp->stats.enqueue_err_count++;
1001 * This message cannot be enqueued,
1002 * decrease number of ops that wasn't sent
1004 tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
1005 if (nb_ops_sent == 0)
1010 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
1016 tmp_qp->stats.enqueued_count += nb_ops_sent;
1017 queue->nb_pending_requests += nb_ops_sent;
1018 if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
1019 queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
1020 txq_write_tail(tmp_qp, queue);
1026 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
1028 uint32_t old_head, new_head;
1031 old_head = q->csr_head;
1033 max_head = qp->nb_descriptors * q->msg_size;
1035 /* write out free descriptors */
1036 void *cur_desc = (uint8_t *)q->base_addr + old_head;
1038 if (new_head < old_head) {
1039 memset(cur_desc, ADF_RING_EMPTY_SIG, max_head - old_head);
1040 memset(q->base_addr, ADF_RING_EMPTY_SIG, new_head);
1042 memset(cur_desc, ADF_RING_EMPTY_SIG, new_head - old_head);
1044 q->nb_processed_responses = 0;
1045 q->csr_head = new_head;
1047 /* write current head to CSR */
1048 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
1049 q->hw_queue_number, new_head);
1053 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
1056 struct qat_queue *rx_queue, *tx_queue;
1057 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
1058 uint32_t msg_counter = 0;
1059 struct rte_crypto_op *rx_op;
1060 struct icp_qat_fw_comn_resp *resp_msg;
1063 rx_queue = &(tmp_qp->rx_q);
1064 tx_queue = &(tmp_qp->tx_q);
1065 head = rx_queue->head;
1066 resp_msg = (struct icp_qat_fw_comn_resp *)
1067 ((uint8_t *)rx_queue->base_addr + head);
1069 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
1070 msg_counter != nb_ops) {
1071 rx_op = (struct rte_crypto_op *)(uintptr_t)
1072 (resp_msg->opaque_data);
1074 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1075 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
1076 sizeof(struct icp_qat_fw_comn_resp));
1078 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
1079 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
1080 resp_msg->comn_hdr.comn_status)) {
1081 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1083 struct qat_session *sess = (struct qat_session *)
1084 get_session_private_data(
1085 rx_op->sym->session,
1086 cryptodev_qat_driver_id);
1089 qat_bpicipher_postprocess(sess, rx_op);
1090 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1093 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
1094 resp_msg = (struct icp_qat_fw_comn_resp *)
1095 ((uint8_t *)rx_queue->base_addr + head);
1100 if (msg_counter > 0) {
1101 rx_queue->head = head;
1102 tmp_qp->stats.dequeued_count += msg_counter;
1103 rx_queue->nb_processed_responses += msg_counter;
1104 tmp_qp->inflights16 -= msg_counter;
1106 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
1107 rxq_free_desc(tmp_qp, rx_queue);
1109 /* also check if tail needs to be advanced */
1110 if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
1111 tx_queue->tail != tx_queue->csr_tail) {
1112 txq_write_tail(tmp_qp, tx_queue);
1118 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1119 struct qat_alg_buf_list *list, uint32_t data_len)
1123 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1124 buff_start + rte_pktmbuf_data_len(buf);
1126 list->bufers[0].addr = buff_start;
1127 list->bufers[0].resrvd = 0;
1128 list->bufers[0].len = buf_len;
1130 if (data_len <= buf_len) {
1131 list->num_bufs = nr;
1132 list->bufers[0].len = data_len;
1138 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1139 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1141 QAT_SGL_MAX_NUMBER);
1145 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1146 list->bufers[nr].resrvd = 0;
1147 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1149 buf_len += list->bufers[nr].len;
1152 if (buf_len > data_len) {
1153 list->bufers[nr].len -=
1159 list->num_bufs = nr;
1165 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1166 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1167 struct rte_crypto_op *op,
1168 struct icp_qat_fw_la_bulk_req *qat_req)
1170 /* copy IV into request if it fits */
1171 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1172 rte_memcpy(cipher_param->u.cipher_IV_array,
1173 rte_crypto_op_ctod_offset(op, uint8_t *,
1177 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1178 qat_req->comn_hdr.serv_specif_flags,
1179 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1180 cipher_param->u.s.cipher_IV_ptr =
1181 rte_crypto_op_ctophys_offset(op,
1186 /** Set IV for CCM is special case, 0th byte is set to q-1
1187 * where q is padding of nonce in 16 byte block
1190 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
1191 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1192 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
1194 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
1195 ICP_QAT_HW_CCM_NONCE_OFFSET,
1196 rte_crypto_op_ctod_offset(op, uint8_t *,
1197 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
1199 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
1200 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
1202 if (aad_len_field_sz)
1203 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
1204 rte_crypto_op_ctod_offset(op, uint8_t *,
1205 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
1210 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1211 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1214 struct qat_session *ctx;
1215 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1216 struct icp_qat_fw_la_auth_req_params *auth_param;
1217 register struct icp_qat_fw_la_bulk_req *qat_req;
1218 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1219 uint32_t cipher_len = 0, cipher_ofs = 0;
1220 uint32_t auth_len = 0, auth_ofs = 0;
1221 uint32_t min_ofs = 0;
1222 uint64_t src_buf_start = 0, dst_buf_start = 0;
1225 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1226 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1227 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1228 "operation requests, op (%p) is not a "
1229 "symmetric operation.", op);
1233 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1234 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1235 " requests, op (%p) is sessionless.", op);
1239 ctx = (struct qat_session *)get_session_private_data(
1240 op->sym->session, cryptodev_qat_driver_id);
1242 if (unlikely(ctx == NULL)) {
1243 PMD_DRV_LOG(ERR, "Session was not created for this device");
1247 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1248 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1249 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1255 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1256 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1257 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1258 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1259 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1261 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1262 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1263 /* AES-GCM or AES-CCM */
1264 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1265 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
1266 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
1267 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
1268 && ctx->qat_hash_alg ==
1269 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
1275 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1278 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1285 if (ctx->qat_cipher_alg ==
1286 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1287 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1288 ctx->qat_cipher_alg ==
1289 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1292 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1293 || (cipher_param->cipher_offset
1294 % BYTE_LENGTH != 0))) {
1296 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1297 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1300 cipher_len = op->sym->cipher.data.length >> 3;
1301 cipher_ofs = op->sym->cipher.data.offset >> 3;
1303 } else if (ctx->bpi_ctx) {
1304 /* DOCSIS - only send complete blocks to device
1305 * Process any partial block using CFB mode.
1306 * Even if 0 complete blocks, still send this to device
1307 * to get into rx queue for post-process and dequeuing
1309 cipher_len = qat_bpicipher_preprocess(ctx, op);
1310 cipher_ofs = op->sym->cipher.data.offset;
1312 cipher_len = op->sym->cipher.data.length;
1313 cipher_ofs = op->sym->cipher.data.offset;
1316 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1317 cipher_param, op, qat_req);
1318 min_ofs = cipher_ofs;
1323 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1324 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1325 ctx->qat_hash_alg ==
1326 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1327 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1328 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1330 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1331 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1334 auth_ofs = op->sym->auth.data.offset >> 3;
1335 auth_len = op->sym->auth.data.length >> 3;
1337 auth_param->u1.aad_adr =
1338 rte_crypto_op_ctophys_offset(op,
1339 ctx->auth_iv.offset);
1341 } else if (ctx->qat_hash_alg ==
1342 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1343 ctx->qat_hash_alg ==
1344 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1346 set_cipher_iv(ctx->auth_iv.length,
1347 ctx->auth_iv.offset,
1348 cipher_param, op, qat_req);
1349 auth_ofs = op->sym->auth.data.offset;
1350 auth_len = op->sym->auth.data.length;
1352 auth_param->u1.aad_adr = 0;
1353 auth_param->u2.aad_sz = 0;
1356 * If len(iv)==12B fw computes J0
1358 if (ctx->auth_iv.length == 12) {
1359 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1360 qat_req->comn_hdr.serv_specif_flags,
1361 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1365 auth_ofs = op->sym->auth.data.offset;
1366 auth_len = op->sym->auth.data.length;
1371 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1377 * This address may used for setting AAD physical pointer
1378 * into IV offset from op
1380 phys_addr_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
1381 if (ctx->qat_hash_alg ==
1382 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1383 ctx->qat_hash_alg ==
1384 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1386 * If len(iv)==12B fw computes J0
1388 if (ctx->cipher_iv.length == 12) {
1389 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1390 qat_req->comn_hdr.serv_specif_flags,
1391 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1394 set_cipher_iv(ctx->cipher_iv.length,
1395 ctx->cipher_iv.offset,
1396 cipher_param, op, qat_req);
1398 } else if (ctx->qat_hash_alg ==
1399 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
1401 /* In case of AES-CCM this may point to user selected memory
1402 * or iv offset in cypto_op
1404 uint8_t *aad_data = op->sym->aead.aad.data;
1405 /* This is true AAD length, it not includes 18 bytes of
1408 uint8_t aad_ccm_real_len = 0;
1410 uint8_t aad_len_field_sz = 0;
1411 uint32_t msg_len_be =
1412 rte_bswap32(op->sym->aead.data.length);
1414 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
1415 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
1416 aad_ccm_real_len = ctx->aad_len -
1417 ICP_QAT_HW_CCM_AAD_B0_LEN -
1418 ICP_QAT_HW_CCM_AAD_LEN_INFO;
1421 * aad_len not greater than 18, so no actual aad data,
1422 * then use IV after op for B0 block
1424 aad_data = rte_crypto_op_ctod_offset(op, uint8_t *,
1425 ctx->cipher_iv.offset);
1426 aad_phys_addr_aead =
1427 rte_crypto_op_ctophys_offset(op,
1428 ctx->cipher_iv.offset);
1431 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST - ctx->cipher_iv.length;
1433 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(aad_len_field_sz,
1434 ctx->digest_length, q);
1436 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
1437 memcpy(aad_data + ctx->cipher_iv.length +
1438 ICP_QAT_HW_CCM_NONCE_OFFSET
1439 + (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
1440 (uint8_t *)&msg_len_be,
1441 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
1443 memcpy(aad_data + ctx->cipher_iv.length +
1444 ICP_QAT_HW_CCM_NONCE_OFFSET,
1445 (uint8_t *)&msg_len_be
1446 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
1450 if (aad_len_field_sz > 0) {
1451 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
1452 = rte_bswap16(aad_ccm_real_len);
1454 if ((aad_ccm_real_len + aad_len_field_sz)
1455 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
1456 uint8_t pad_len = 0;
1457 uint8_t pad_idx = 0;
1459 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
1460 ((aad_ccm_real_len + aad_len_field_sz) %
1461 ICP_QAT_HW_CCM_AAD_B0_LEN);
1462 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
1463 aad_ccm_real_len + aad_len_field_sz;
1464 memset(&aad_data[pad_idx],
1470 set_cipher_iv_ccm(ctx->cipher_iv.length,
1471 ctx->cipher_iv.offset,
1472 cipher_param, op, q,
1477 cipher_len = op->sym->aead.data.length;
1478 cipher_ofs = op->sym->aead.data.offset;
1479 auth_len = op->sym->aead.data.length;
1480 auth_ofs = op->sym->aead.data.offset;
1482 auth_param->u1.aad_adr = aad_phys_addr_aead;
1483 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1484 min_ofs = op->sym->aead.data.offset;
1487 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1490 /* adjust for chain case */
1491 if (do_cipher && do_auth)
1492 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1494 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1497 if (unlikely(op->sym->m_dst != NULL)) {
1498 /* Out-of-place operation (OOP)
1499 * Don't align DMA start. DMA the minimum data-set
1500 * so as not to overwrite data in dest buffer
1503 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1505 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1508 /* In-place operation
1509 * Start DMA at nearest aligned address below min_ofs
1512 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1513 & QAT_64_BTYE_ALIGN_MASK;
1515 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1516 rte_pktmbuf_headroom(op->sym->m_src))
1518 /* alignment has pushed addr ahead of start of mbuf
1519 * so revert and take the performance hit
1522 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1525 dst_buf_start = src_buf_start;
1528 if (do_cipher || do_aead) {
1529 cipher_param->cipher_offset =
1530 (uint32_t)rte_pktmbuf_mtophys_offset(
1531 op->sym->m_src, cipher_ofs) - src_buf_start;
1532 cipher_param->cipher_length = cipher_len;
1534 cipher_param->cipher_offset = 0;
1535 cipher_param->cipher_length = 0;
1538 if (do_auth || do_aead) {
1539 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1540 op->sym->m_src, auth_ofs) - src_buf_start;
1541 auth_param->auth_len = auth_len;
1543 auth_param->auth_off = 0;
1544 auth_param->auth_len = 0;
1547 qat_req->comn_mid.dst_length =
1548 qat_req->comn_mid.src_length =
1549 (cipher_param->cipher_offset + cipher_param->cipher_length)
1550 > (auth_param->auth_off + auth_param->auth_len) ?
1551 (cipher_param->cipher_offset + cipher_param->cipher_length)
1552 : (auth_param->auth_off + auth_param->auth_len);
1556 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1557 QAT_COMN_PTR_TYPE_SGL);
1558 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1559 &qat_op_cookie->qat_sgl_list_src,
1560 qat_req->comn_mid.src_length);
1562 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1566 if (likely(op->sym->m_dst == NULL))
1567 qat_req->comn_mid.dest_data_addr =
1568 qat_req->comn_mid.src_data_addr =
1569 qat_op_cookie->qat_sgl_src_phys_addr;
1571 ret = qat_sgl_fill_array(op->sym->m_dst,
1573 &qat_op_cookie->qat_sgl_list_dst,
1574 qat_req->comn_mid.dst_length);
1577 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1582 qat_req->comn_mid.src_data_addr =
1583 qat_op_cookie->qat_sgl_src_phys_addr;
1584 qat_req->comn_mid.dest_data_addr =
1585 qat_op_cookie->qat_sgl_dst_phys_addr;
1588 qat_req->comn_mid.src_data_addr = src_buf_start;
1589 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1592 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1593 rte_hexdump(stdout, "qat_req:", qat_req,
1594 sizeof(struct icp_qat_fw_la_bulk_req));
1595 rte_hexdump(stdout, "src_data:",
1596 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1597 rte_pktmbuf_data_len(op->sym->m_src));
1599 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1601 ctx->cipher_iv.offset);
1602 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1603 ctx->cipher_iv.length);
1607 if (ctx->auth_iv.length) {
1608 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1610 ctx->auth_iv.offset);
1611 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1612 ctx->auth_iv.length);
1614 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1615 ctx->digest_length);
1619 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1620 ctx->digest_length);
1621 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1628 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1630 uint32_t div = data >> shift;
1631 uint32_t mult = div << shift;
1636 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1637 __rte_unused struct rte_cryptodev_config *config)
1639 PMD_INIT_FUNC_TRACE();
1643 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1645 PMD_INIT_FUNC_TRACE();
1649 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1651 PMD_INIT_FUNC_TRACE();
1654 int qat_dev_close(struct rte_cryptodev *dev)
1658 PMD_INIT_FUNC_TRACE();
1660 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1661 ret = qat_crypto_sym_qp_release(dev, i);
1669 void qat_dev_info_get(struct rte_cryptodev *dev,
1670 struct rte_cryptodev_info *info)
1672 struct qat_pmd_private *internals = dev->data->dev_private;
1674 PMD_INIT_FUNC_TRACE();
1676 info->max_nb_queue_pairs =
1677 ADF_NUM_SYM_QPS_PER_BUNDLE *
1678 ADF_NUM_BUNDLES_PER_DEV;
1679 info->feature_flags = dev->feature_flags;
1680 info->capabilities = internals->qat_dev_capabilities;
1681 info->sym.max_nb_sessions = internals->max_nb_sessions;
1682 info->driver_id = cryptodev_qat_driver_id;
1683 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1687 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1688 struct rte_cryptodev_stats *stats)
1691 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1693 PMD_INIT_FUNC_TRACE();
1694 if (stats == NULL) {
1695 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1698 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1699 if (qp[i] == NULL) {
1700 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1704 stats->enqueued_count += qp[i]->stats.enqueued_count;
1705 stats->dequeued_count += qp[i]->stats.dequeued_count;
1706 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1707 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1711 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1714 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1716 PMD_INIT_FUNC_TRACE();
1717 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1718 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1719 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");