4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
177 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
179 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
181 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
198 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
200 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
202 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
218 { /* AES GCM (AUTH) */
219 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
221 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
223 .algo = RTE_CRYPTO_AUTH_AES_GCM,
243 { /* AES GMAC (AUTH) */
244 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
246 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
248 .algo = RTE_CRYPTO_AUTH_AES_GMAC,
268 { /* SNOW 3G (UIA2) */
269 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
271 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
273 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
293 { /* AES GCM (CIPHER) */
294 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
296 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
298 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
314 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
316 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
318 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
333 { /* SNOW 3G (UEA2) */
334 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
336 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
338 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
354 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
356 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
358 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
374 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
376 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
378 .algo = RTE_CRYPTO_AUTH_NULL,
394 { /* NULL (CIPHER) */
395 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
397 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
399 .algo = RTE_CRYPTO_CIPHER_NULL,
415 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
417 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
419 .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
435 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
437 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
439 .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
459 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
462 static inline uint32_t
463 adf_modulo(uint32_t data, uint32_t shift);
466 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
468 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
471 struct qat_session *sess = session;
472 phys_addr_t cd_paddr;
474 PMD_INIT_FUNC_TRACE();
476 cd_paddr = sess->cd_paddr;
477 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
478 sess->cd_paddr = cd_paddr;
480 PMD_DRV_LOG(ERR, "NULL session");
484 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
487 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
488 return ICP_QAT_FW_LA_CMD_CIPHER;
490 /* Authentication Only */
491 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
492 return ICP_QAT_FW_LA_CMD_AUTH;
494 if (xform->next == NULL)
497 /* Cipher then Authenticate */
498 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
499 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
500 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
502 /* Authenticate then Cipher */
503 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
504 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
505 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
510 static struct rte_crypto_auth_xform *
511 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
514 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
523 static struct rte_crypto_cipher_xform *
524 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
527 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
528 return &xform->cipher;
536 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
537 struct rte_crypto_sym_xform *xform, void *session_private)
539 struct qat_pmd_private *internals = dev->data->dev_private;
541 struct qat_session *session = session_private;
543 struct rte_crypto_cipher_xform *cipher_xform = NULL;
545 /* Get cipher xform from crypto xform chain */
546 cipher_xform = qat_get_cipher_xform(xform);
548 switch (cipher_xform->algo) {
549 case RTE_CRYPTO_CIPHER_AES_CBC:
550 if (qat_alg_validate_aes_key(cipher_xform->key.length,
551 &session->qat_cipher_alg) != 0) {
552 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
555 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
557 case RTE_CRYPTO_CIPHER_AES_GCM:
558 if (qat_alg_validate_aes_key(cipher_xform->key.length,
559 &session->qat_cipher_alg) != 0) {
560 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
563 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
565 case RTE_CRYPTO_CIPHER_AES_CTR:
566 if (qat_alg_validate_aes_key(cipher_xform->key.length,
567 &session->qat_cipher_alg) != 0) {
568 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
571 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
573 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
574 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
575 &session->qat_cipher_alg) != 0) {
576 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
579 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
581 case RTE_CRYPTO_CIPHER_NULL:
582 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
584 case RTE_CRYPTO_CIPHER_KASUMI_F8:
585 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
586 &session->qat_cipher_alg) != 0) {
587 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
590 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
592 case RTE_CRYPTO_CIPHER_3DES_ECB:
593 case RTE_CRYPTO_CIPHER_3DES_CBC:
594 case RTE_CRYPTO_CIPHER_AES_ECB:
595 case RTE_CRYPTO_CIPHER_AES_CCM:
596 case RTE_CRYPTO_CIPHER_AES_F8:
597 case RTE_CRYPTO_CIPHER_AES_XTS:
598 case RTE_CRYPTO_CIPHER_ARC4:
599 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
600 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
604 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
609 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
610 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
612 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
614 if (qat_alg_aead_session_create_content_desc_cipher(session,
615 cipher_xform->key.data,
616 cipher_xform->key.length))
622 rte_mempool_put(internals->sess_mp, session);
628 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
629 struct rte_crypto_sym_xform *xform, void *session_private)
631 struct qat_pmd_private *internals = dev->data->dev_private;
633 struct qat_session *session = session_private;
637 PMD_INIT_FUNC_TRACE();
639 /* Get requested QAT command id */
640 qat_cmd_id = qat_get_cmd_id(xform);
641 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
642 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
645 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
646 switch (session->qat_cmd) {
647 case ICP_QAT_FW_LA_CMD_CIPHER:
648 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
650 case ICP_QAT_FW_LA_CMD_AUTH:
651 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
653 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
654 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
655 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
657 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
658 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
659 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
661 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
662 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
663 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
664 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
665 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
666 case ICP_QAT_FW_LA_CMD_MGF1:
667 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
668 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
669 case ICP_QAT_FW_LA_CMD_DELIMITER:
670 PMD_DRV_LOG(ERR, "Unsupported Service %u",
674 PMD_DRV_LOG(ERR, "Unsupported Service %u",
681 rte_mempool_put(internals->sess_mp, session);
686 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
687 struct rte_crypto_sym_xform *xform,
688 struct qat_session *session_private)
691 struct qat_pmd_private *internals = dev->data->dev_private;
692 struct qat_session *session = session_private;
693 struct rte_crypto_auth_xform *auth_xform = NULL;
694 struct rte_crypto_cipher_xform *cipher_xform = NULL;
695 auth_xform = qat_get_auth_xform(xform);
697 switch (auth_xform->algo) {
698 case RTE_CRYPTO_AUTH_SHA1_HMAC:
699 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
701 case RTE_CRYPTO_AUTH_SHA224_HMAC:
702 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
704 case RTE_CRYPTO_AUTH_SHA256_HMAC:
705 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
707 case RTE_CRYPTO_AUTH_SHA384_HMAC:
708 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
710 case RTE_CRYPTO_AUTH_SHA512_HMAC:
711 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
713 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
714 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
716 case RTE_CRYPTO_AUTH_AES_GCM:
717 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
719 case RTE_CRYPTO_AUTH_AES_GMAC:
720 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
722 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
723 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
725 case RTE_CRYPTO_AUTH_MD5_HMAC:
726 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
728 case RTE_CRYPTO_AUTH_NULL:
729 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
731 case RTE_CRYPTO_AUTH_KASUMI_F9:
732 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
734 case RTE_CRYPTO_AUTH_SHA1:
735 case RTE_CRYPTO_AUTH_SHA256:
736 case RTE_CRYPTO_AUTH_SHA512:
737 case RTE_CRYPTO_AUTH_SHA224:
738 case RTE_CRYPTO_AUTH_SHA384:
739 case RTE_CRYPTO_AUTH_MD5:
740 case RTE_CRYPTO_AUTH_AES_CCM:
741 case RTE_CRYPTO_AUTH_AES_CMAC:
742 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
743 case RTE_CRYPTO_AUTH_ZUC_EIA3:
744 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
748 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
752 cipher_xform = qat_get_cipher_xform(xform);
754 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
755 (session->qat_hash_alg ==
756 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
757 if (qat_alg_aead_session_create_content_desc_auth(session,
758 cipher_xform->key.data,
759 cipher_xform->key.length,
760 auth_xform->add_auth_data_length,
761 auth_xform->digest_length,
765 if (qat_alg_aead_session_create_content_desc_auth(session,
766 auth_xform->key.data,
767 auth_xform->key.length,
768 auth_xform->add_auth_data_length,
769 auth_xform->digest_length,
776 if (internals->sess_mp != NULL)
777 rte_mempool_put(internals->sess_mp, session);
781 unsigned qat_crypto_sym_get_session_private_size(
782 struct rte_cryptodev *dev __rte_unused)
784 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
789 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
792 register struct qat_queue *queue;
793 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
794 register uint32_t nb_ops_sent = 0;
795 register struct rte_crypto_op **cur_op = ops;
797 uint16_t nb_ops_possible = nb_ops;
798 register uint8_t *base_addr;
799 register uint32_t tail;
802 if (unlikely(nb_ops == 0))
805 /* read params used a lot in main loop into registers */
806 queue = &(tmp_qp->tx_q);
807 base_addr = (uint8_t *)queue->base_addr;
810 /* Find how many can actually fit on the ring */
811 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
812 - queue->max_inflights;
814 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
815 nb_ops_possible = nb_ops - overflow;
816 if (nb_ops_possible == 0)
820 while (nb_ops_sent != nb_ops_possible) {
821 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
823 tmp_qp->stats.enqueue_err_count++;
824 if (nb_ops_sent == 0)
829 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
834 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
835 queue->hw_queue_number, tail);
837 tmp_qp->stats.enqueued_count += nb_ops_sent;
842 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
845 struct qat_queue *queue;
846 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
847 uint32_t msg_counter = 0;
848 struct rte_crypto_op *rx_op;
849 struct icp_qat_fw_comn_resp *resp_msg;
851 queue = &(tmp_qp->rx_q);
852 resp_msg = (struct icp_qat_fw_comn_resp *)
853 ((uint8_t *)queue->base_addr + queue->head);
855 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
856 msg_counter != nb_ops) {
857 rx_op = (struct rte_crypto_op *)(uintptr_t)
858 (resp_msg->opaque_data);
860 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
861 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
862 sizeof(struct icp_qat_fw_comn_resp));
864 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
865 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
866 resp_msg->comn_hdr.comn_status)) {
867 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
869 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
871 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
872 queue->head = adf_modulo(queue->head +
874 ADF_RING_SIZE_MODULO(queue->queue_size));
875 resp_msg = (struct icp_qat_fw_comn_resp *)
876 ((uint8_t *)queue->base_addr +
882 if (msg_counter > 0) {
883 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
884 queue->hw_bundle_number,
885 queue->hw_queue_number, queue->head);
886 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
887 tmp_qp->stats.dequeued_count += msg_counter;
893 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
895 struct qat_session *ctx;
896 struct icp_qat_fw_la_cipher_req_params *cipher_param;
897 struct icp_qat_fw_la_auth_req_params *auth_param;
898 register struct icp_qat_fw_la_bulk_req *qat_req;
900 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
901 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
902 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
903 "operation requests, op (%p) is not a "
904 "symmetric operation.", op);
908 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
909 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
910 " requests, op (%p) is sessionless.", op);
914 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
915 PMD_DRV_LOG(ERR, "Session was not created for this device");
919 ctx = (struct qat_session *)op->sym->session->_private;
920 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
921 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
922 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
924 qat_req->comn_mid.dst_length =
925 qat_req->comn_mid.src_length =
926 rte_pktmbuf_data_len(op->sym->m_src);
928 qat_req->comn_mid.dest_data_addr =
929 qat_req->comn_mid.src_data_addr =
930 rte_pktmbuf_mtophys(op->sym->m_src);
932 if (unlikely(op->sym->m_dst != NULL)) {
933 qat_req->comn_mid.dest_data_addr =
934 rte_pktmbuf_mtophys(op->sym->m_dst);
935 qat_req->comn_mid.dst_length =
936 rte_pktmbuf_data_len(op->sym->m_dst);
939 cipher_param = (void *)&qat_req->serv_specif_rqpars;
940 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
942 cipher_param->cipher_length = op->sym->cipher.data.length;
943 cipher_param->cipher_offset = op->sym->cipher.data.offset;
944 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
945 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
946 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
947 (cipher_param->cipher_offset
948 % BYTE_LENGTH != 0))) {
949 PMD_DRV_LOG(ERR, " For SNOW 3G/KASUMI, QAT PMD only "
950 "supports byte aligned values");
951 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
954 cipher_param->cipher_length >>= 3;
955 cipher_param->cipher_offset >>= 3;
958 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
959 sizeof(cipher_param->u.cipher_IV_array))) {
960 rte_memcpy(cipher_param->u.cipher_IV_array,
961 op->sym->cipher.iv.data,
962 op->sym->cipher.iv.length);
964 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
965 qat_req->comn_hdr.serv_specif_flags,
966 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
967 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
969 if (op->sym->auth.digest.phys_addr) {
970 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
971 qat_req->comn_hdr.serv_specif_flags,
972 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
973 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
975 auth_param->auth_off = op->sym->auth.data.offset;
976 auth_param->auth_len = op->sym->auth.data.length;
977 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
978 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
979 (auth_param->auth_len % BYTE_LENGTH != 0))) {
980 PMD_DRV_LOG(ERR, " For SNOW 3G, QAT PMD only "
981 "supports byte aligned values");
982 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
985 auth_param->auth_off >>= 3;
986 auth_param->auth_len >>= 3;
988 if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
989 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&
990 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
991 auth_param->auth_len = (auth_param->auth_len >> 3)
992 + (auth_param->auth_off >> 3)
995 auth_param->auth_off = 8;
996 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH
997 && ctx->qat_hash_alg ==
998 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
999 auth_param->auth_len = (auth_param->auth_len >> 3)
1000 + (auth_param->auth_off >> 3)
1001 + (BYTE_LENGTH >> 3);
1002 auth_param->auth_off = 0;
1004 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1006 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1007 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1008 if (op->sym->cipher.iv.length == 12) {
1010 * For GCM a 12 bit IV is allowed,
1011 * but we need to inform the f/w
1013 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1014 qat_req->comn_hdr.serv_specif_flags,
1015 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1017 if (op->sym->cipher.data.length == 0) {
1021 qat_req->comn_mid.dest_data_addr =
1022 qat_req->comn_mid.src_data_addr =
1023 op->sym->auth.aad.phys_addr;
1024 auth_param->u1.aad_adr = 0;
1025 auth_param->auth_len = op->sym->auth.aad.length;
1026 auth_param->u2.aad_sz = 0;
1032 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1033 rte_hexdump(stdout, "qat_req:", qat_req,
1034 sizeof(struct icp_qat_fw_la_bulk_req));
1035 rte_hexdump(stdout, "src_data:",
1036 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1037 rte_pktmbuf_data_len(op->sym->m_src));
1038 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
1039 op->sym->cipher.iv.length);
1040 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1041 op->sym->auth.digest.length);
1042 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1043 op->sym->auth.aad.length);
1048 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1050 uint32_t div = data >> shift;
1051 uint32_t mult = div << shift;
1056 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1058 struct rte_cryptodev_sym_session *sess = sym_sess;
1059 struct qat_session *s = (void *)sess->_private;
1061 PMD_INIT_FUNC_TRACE();
1062 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1063 offsetof(struct qat_session, cd) +
1064 offsetof(struct rte_cryptodev_sym_session, _private);
1067 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
1069 PMD_INIT_FUNC_TRACE();
1073 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1075 PMD_INIT_FUNC_TRACE();
1079 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1081 PMD_INIT_FUNC_TRACE();
1084 int qat_dev_close(struct rte_cryptodev *dev)
1088 PMD_INIT_FUNC_TRACE();
1090 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1091 ret = qat_crypto_sym_qp_release(dev, i);
1099 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
1100 struct rte_cryptodev_info *info)
1102 struct qat_pmd_private *internals = dev->data->dev_private;
1104 PMD_INIT_FUNC_TRACE();
1106 info->max_nb_queue_pairs =
1107 ADF_NUM_SYM_QPS_PER_BUNDLE *
1108 ADF_NUM_BUNDLES_PER_DEV;
1109 info->feature_flags = dev->feature_flags;
1110 info->capabilities = qat_pmd_capabilities;
1111 info->sym.max_nb_sessions = internals->max_nb_sessions;
1112 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1116 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1117 struct rte_cryptodev_stats *stats)
1120 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1122 PMD_INIT_FUNC_TRACE();
1123 if (stats == NULL) {
1124 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1127 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1128 if (qp[i] == NULL) {
1129 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1133 stats->enqueued_count += qp[i]->stats.enqueued_count;
1134 stats->dequeued_count += qp[i]->stats.enqueued_count;
1135 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1136 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
1140 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1143 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1145 PMD_INIT_FUNC_TRACE();
1146 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1147 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1148 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");