4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
177 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
179 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
181 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
198 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
200 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
202 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
218 { /* AES GCM (AUTH) */
219 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
221 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
223 .algo = RTE_CRYPTO_AUTH_AES_GCM,
243 { /* AES GMAC (AUTH) */
244 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
246 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
248 .algo = RTE_CRYPTO_AUTH_AES_GMAC,
268 { /* SNOW3G (UIA2) */
269 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
271 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
273 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
293 { /* AES GCM (CIPHER) */
294 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
296 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
298 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
314 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
316 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
318 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
333 { /* SNOW3G (UEA2) */
334 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
336 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
338 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
354 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
356 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
358 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
374 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
376 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
378 .algo = RTE_CRYPTO_AUTH_NULL,
394 { /* NULL (CIPHER) */
395 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
397 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
399 .algo = RTE_CRYPTO_CIPHER_NULL,
415 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
417 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
419 .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
435 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
437 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
439 .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
459 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
462 static inline uint32_t
463 adf_modulo(uint32_t data, uint32_t shift);
466 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
468 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
471 struct qat_session *sess = session;
472 phys_addr_t cd_paddr;
474 PMD_INIT_FUNC_TRACE();
476 cd_paddr = sess->cd_paddr;
477 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
478 sess->cd_paddr = cd_paddr;
480 PMD_DRV_LOG(ERR, "NULL session");
484 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
487 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
488 return ICP_QAT_FW_LA_CMD_CIPHER;
490 /* Authentication Only */
491 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
492 return ICP_QAT_FW_LA_CMD_AUTH;
494 if (xform->next == NULL)
497 /* Cipher then Authenticate */
498 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
499 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
500 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
502 /* Authenticate then Cipher */
503 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
504 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
505 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
510 static struct rte_crypto_auth_xform *
511 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
514 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
523 static struct rte_crypto_cipher_xform *
524 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
527 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
528 return &xform->cipher;
536 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
537 struct rte_crypto_sym_xform *xform, void *session_private)
539 struct qat_pmd_private *internals = dev->data->dev_private;
541 struct qat_session *session = session_private;
543 struct rte_crypto_cipher_xform *cipher_xform = NULL;
545 /* Get cipher xform from crypto xform chain */
546 cipher_xform = qat_get_cipher_xform(xform);
548 switch (cipher_xform->algo) {
549 case RTE_CRYPTO_CIPHER_AES_CBC:
550 if (qat_alg_validate_aes_key(cipher_xform->key.length,
551 &session->qat_cipher_alg) != 0) {
552 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
555 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
557 case RTE_CRYPTO_CIPHER_AES_GCM:
558 if (qat_alg_validate_aes_key(cipher_xform->key.length,
559 &session->qat_cipher_alg) != 0) {
560 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
563 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
565 case RTE_CRYPTO_CIPHER_AES_CTR:
566 if (qat_alg_validate_aes_key(cipher_xform->key.length,
567 &session->qat_cipher_alg) != 0) {
568 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
571 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
573 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
574 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
575 &session->qat_cipher_alg) != 0) {
576 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
579 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
581 case RTE_CRYPTO_CIPHER_NULL:
582 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
584 case RTE_CRYPTO_CIPHER_KASUMI_F8:
585 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
586 &session->qat_cipher_alg) != 0) {
587 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
590 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
592 case RTE_CRYPTO_CIPHER_3DES_ECB:
593 case RTE_CRYPTO_CIPHER_3DES_CBC:
594 case RTE_CRYPTO_CIPHER_AES_ECB:
595 case RTE_CRYPTO_CIPHER_AES_CCM:
596 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
600 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
605 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
606 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
608 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
610 if (qat_alg_aead_session_create_content_desc_cipher(session,
611 cipher_xform->key.data,
612 cipher_xform->key.length))
618 rte_mempool_put(internals->sess_mp, session);
624 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
625 struct rte_crypto_sym_xform *xform, void *session_private)
627 struct qat_pmd_private *internals = dev->data->dev_private;
629 struct qat_session *session = session_private;
633 PMD_INIT_FUNC_TRACE();
635 /* Get requested QAT command id */
636 qat_cmd_id = qat_get_cmd_id(xform);
637 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
638 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
641 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
642 switch (session->qat_cmd) {
643 case ICP_QAT_FW_LA_CMD_CIPHER:
644 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
646 case ICP_QAT_FW_LA_CMD_AUTH:
647 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
649 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
650 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
651 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
653 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
654 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
655 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
657 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
658 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
659 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
660 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
661 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
662 case ICP_QAT_FW_LA_CMD_MGF1:
663 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
664 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
665 case ICP_QAT_FW_LA_CMD_DELIMITER:
666 PMD_DRV_LOG(ERR, "Unsupported Service %u",
670 PMD_DRV_LOG(ERR, "Unsupported Service %u",
677 rte_mempool_put(internals->sess_mp, session);
682 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
683 struct rte_crypto_sym_xform *xform,
684 struct qat_session *session_private)
687 struct qat_pmd_private *internals = dev->data->dev_private;
688 struct qat_session *session = session_private;
689 struct rte_crypto_auth_xform *auth_xform = NULL;
690 struct rte_crypto_cipher_xform *cipher_xform = NULL;
691 auth_xform = qat_get_auth_xform(xform);
693 switch (auth_xform->algo) {
694 case RTE_CRYPTO_AUTH_SHA1_HMAC:
695 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
697 case RTE_CRYPTO_AUTH_SHA224_HMAC:
698 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
700 case RTE_CRYPTO_AUTH_SHA256_HMAC:
701 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
703 case RTE_CRYPTO_AUTH_SHA384_HMAC:
704 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
706 case RTE_CRYPTO_AUTH_SHA512_HMAC:
707 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
709 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
710 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
712 case RTE_CRYPTO_AUTH_AES_GCM:
713 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
715 case RTE_CRYPTO_AUTH_AES_GMAC:
716 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
718 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
719 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
721 case RTE_CRYPTO_AUTH_MD5_HMAC:
722 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
724 case RTE_CRYPTO_AUTH_NULL:
725 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
727 case RTE_CRYPTO_AUTH_KASUMI_F9:
728 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
730 case RTE_CRYPTO_AUTH_SHA1:
731 case RTE_CRYPTO_AUTH_SHA256:
732 case RTE_CRYPTO_AUTH_SHA512:
733 case RTE_CRYPTO_AUTH_SHA224:
734 case RTE_CRYPTO_AUTH_SHA384:
735 case RTE_CRYPTO_AUTH_MD5:
736 case RTE_CRYPTO_AUTH_AES_CCM:
737 case RTE_CRYPTO_AUTH_AES_CMAC:
738 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
739 case RTE_CRYPTO_AUTH_ZUC_EIA3:
740 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
744 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
748 cipher_xform = qat_get_cipher_xform(xform);
750 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
751 (session->qat_hash_alg ==
752 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
753 if (qat_alg_aead_session_create_content_desc_auth(session,
754 cipher_xform->key.data,
755 cipher_xform->key.length,
756 auth_xform->add_auth_data_length,
757 auth_xform->digest_length,
761 if (qat_alg_aead_session_create_content_desc_auth(session,
762 auth_xform->key.data,
763 auth_xform->key.length,
764 auth_xform->add_auth_data_length,
765 auth_xform->digest_length,
772 if (internals->sess_mp != NULL)
773 rte_mempool_put(internals->sess_mp, session);
777 unsigned qat_crypto_sym_get_session_private_size(
778 struct rte_cryptodev *dev __rte_unused)
780 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
785 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
788 register struct qat_queue *queue;
789 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
790 register uint32_t nb_ops_sent = 0;
791 register struct rte_crypto_op **cur_op = ops;
793 uint16_t nb_ops_possible = nb_ops;
794 register uint8_t *base_addr;
795 register uint32_t tail;
798 if (unlikely(nb_ops == 0))
801 /* read params used a lot in main loop into registers */
802 queue = &(tmp_qp->tx_q);
803 base_addr = (uint8_t *)queue->base_addr;
806 /* Find how many can actually fit on the ring */
807 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
808 - queue->max_inflights;
810 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
811 nb_ops_possible = nb_ops - overflow;
812 if (nb_ops_possible == 0)
816 while (nb_ops_sent != nb_ops_possible) {
817 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
819 tmp_qp->stats.enqueue_err_count++;
820 if (nb_ops_sent == 0)
825 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
830 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
831 queue->hw_queue_number, tail);
833 tmp_qp->stats.enqueued_count += nb_ops_sent;
838 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
841 struct qat_queue *queue;
842 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
843 uint32_t msg_counter = 0;
844 struct rte_crypto_op *rx_op;
845 struct icp_qat_fw_comn_resp *resp_msg;
847 queue = &(tmp_qp->rx_q);
848 resp_msg = (struct icp_qat_fw_comn_resp *)
849 ((uint8_t *)queue->base_addr + queue->head);
851 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
852 msg_counter != nb_ops) {
853 rx_op = (struct rte_crypto_op *)(uintptr_t)
854 (resp_msg->opaque_data);
856 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
857 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
858 sizeof(struct icp_qat_fw_comn_resp));
860 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
861 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
862 resp_msg->comn_hdr.comn_status)) {
863 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
865 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
867 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
868 queue->head = adf_modulo(queue->head +
870 ADF_RING_SIZE_MODULO(queue->queue_size));
871 resp_msg = (struct icp_qat_fw_comn_resp *)
872 ((uint8_t *)queue->base_addr +
878 if (msg_counter > 0) {
879 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
880 queue->hw_bundle_number,
881 queue->hw_queue_number, queue->head);
882 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
883 tmp_qp->stats.dequeued_count += msg_counter;
889 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
891 struct qat_session *ctx;
892 struct icp_qat_fw_la_cipher_req_params *cipher_param;
893 struct icp_qat_fw_la_auth_req_params *auth_param;
894 register struct icp_qat_fw_la_bulk_req *qat_req;
896 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
897 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
898 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
899 "operation requests, op (%p) is not a "
900 "symmetric operation.", op);
904 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
905 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
906 " requests, op (%p) is sessionless.", op);
910 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
911 PMD_DRV_LOG(ERR, "Session was not created for this device");
915 ctx = (struct qat_session *)op->sym->session->_private;
916 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
917 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
918 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
920 qat_req->comn_mid.dst_length =
921 qat_req->comn_mid.src_length =
922 rte_pktmbuf_data_len(op->sym->m_src);
924 qat_req->comn_mid.dest_data_addr =
925 qat_req->comn_mid.src_data_addr =
926 rte_pktmbuf_mtophys(op->sym->m_src);
928 if (unlikely(op->sym->m_dst != NULL)) {
929 qat_req->comn_mid.dest_data_addr =
930 rte_pktmbuf_mtophys(op->sym->m_dst);
931 qat_req->comn_mid.dst_length =
932 rte_pktmbuf_data_len(op->sym->m_dst);
935 cipher_param = (void *)&qat_req->serv_specif_rqpars;
936 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
938 cipher_param->cipher_length = op->sym->cipher.data.length;
939 cipher_param->cipher_offset = op->sym->cipher.data.offset;
940 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
941 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
942 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
943 (cipher_param->cipher_offset
944 % BYTE_LENGTH != 0))) {
945 PMD_DRV_LOG(ERR, " For Snow3g/Kasumi, QAT PMD only "
946 "supports byte aligned values");
947 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
950 cipher_param->cipher_length >>= 3;
951 cipher_param->cipher_offset >>= 3;
954 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
955 sizeof(cipher_param->u.cipher_IV_array))) {
956 rte_memcpy(cipher_param->u.cipher_IV_array,
957 op->sym->cipher.iv.data,
958 op->sym->cipher.iv.length);
960 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
961 qat_req->comn_hdr.serv_specif_flags,
962 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
963 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
965 if (op->sym->auth.digest.phys_addr) {
966 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
967 qat_req->comn_hdr.serv_specif_flags,
968 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
969 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
971 auth_param->auth_off = op->sym->auth.data.offset;
972 auth_param->auth_len = op->sym->auth.data.length;
973 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
974 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
975 (auth_param->auth_len % BYTE_LENGTH != 0))) {
976 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
977 "supports byte aligned values");
978 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
981 auth_param->auth_off >>= 3;
982 auth_param->auth_len >>= 3;
984 if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
985 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&
986 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
987 auth_param->auth_len = (auth_param->auth_len >> 3)
988 + (auth_param->auth_off >> 3)
991 auth_param->auth_off = 8;
992 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH
993 && ctx->qat_hash_alg ==
994 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
995 auth_param->auth_len = (auth_param->auth_len >> 3)
996 + (auth_param->auth_off >> 3)
997 + (BYTE_LENGTH >> 3);
998 auth_param->auth_off = 0;
1000 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1002 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1003 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1004 if (op->sym->cipher.iv.length == 12) {
1006 * For GCM a 12 bit IV is allowed,
1007 * but we need to inform the f/w
1009 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1010 qat_req->comn_hdr.serv_specif_flags,
1011 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1013 if (op->sym->cipher.data.length == 0) {
1017 qat_req->comn_mid.dest_data_addr =
1018 qat_req->comn_mid.src_data_addr =
1019 op->sym->auth.aad.phys_addr;
1020 auth_param->u1.aad_adr = 0;
1021 auth_param->auth_len = op->sym->auth.aad.length;
1022 auth_param->u2.aad_sz = 0;
1028 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1029 rte_hexdump(stdout, "qat_req:", qat_req,
1030 sizeof(struct icp_qat_fw_la_bulk_req));
1031 rte_hexdump(stdout, "src_data:",
1032 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1033 rte_pktmbuf_data_len(op->sym->m_src));
1034 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
1035 op->sym->cipher.iv.length);
1036 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1037 op->sym->auth.digest.length);
1038 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1039 op->sym->auth.aad.length);
1044 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1046 uint32_t div = data >> shift;
1047 uint32_t mult = div << shift;
1052 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1054 struct rte_cryptodev_sym_session *sess = sym_sess;
1055 struct qat_session *s = (void *)sess->_private;
1057 PMD_INIT_FUNC_TRACE();
1058 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1059 offsetof(struct qat_session, cd) +
1060 offsetof(struct rte_cryptodev_sym_session, _private);
1063 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
1065 PMD_INIT_FUNC_TRACE();
1069 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1071 PMD_INIT_FUNC_TRACE();
1075 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1077 PMD_INIT_FUNC_TRACE();
1080 int qat_dev_close(struct rte_cryptodev *dev)
1084 PMD_INIT_FUNC_TRACE();
1086 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1087 ret = qat_crypto_sym_qp_release(dev, i);
1095 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
1096 struct rte_cryptodev_info *info)
1098 struct qat_pmd_private *internals = dev->data->dev_private;
1100 PMD_INIT_FUNC_TRACE();
1102 info->max_nb_queue_pairs =
1103 ADF_NUM_SYM_QPS_PER_BUNDLE *
1104 ADF_NUM_BUNDLES_PER_DEV;
1105 info->feature_flags = dev->feature_flags;
1106 info->capabilities = qat_pmd_capabilities;
1107 info->sym.max_nb_sessions = internals->max_nb_sessions;
1108 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1112 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1113 struct rte_cryptodev_stats *stats)
1116 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1118 PMD_INIT_FUNC_TRACE();
1119 if (stats == NULL) {
1120 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1123 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1124 if (qp[i] == NULL) {
1125 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1129 stats->enqueued_count += qp[i]->stats.enqueued_count;
1130 stats->dequeued_count += qp[i]->stats.enqueued_count;
1131 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1132 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
1136 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1139 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1141 PMD_INIT_FUNC_TRACE();
1142 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1143 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1144 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");