1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_mempool.h>
7 #include <rte_hexdump.h>
8 #include <rte_crypto_sym.h>
9 #include <rte_byteorder.h>
11 #include <rte_bus_pci.h>
13 #include <openssl/evp.h>
17 #include "qat_crypto.h"
18 #include "adf_transport_access_macros.h"
21 /* bpi is only used for partial blocks of DES and AES
22 * so AES block len can be assumed as max len for iv, src and dst
24 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
27 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
28 struct qat_pmd_private *internals) {
30 const struct rte_cryptodev_capabilities *capability;
32 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
33 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
34 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
37 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
40 if (capability->sym.cipher.algo == algo)
47 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
48 struct qat_pmd_private *internals) {
50 const struct rte_cryptodev_capabilities *capability;
52 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
53 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
54 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
57 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
60 if (capability->sym.auth.algo == algo)
66 /** Encrypt a single partial block
67 * Depends on openssl libcrypto
68 * Uses ECB+XOR to do CFB encryption, same result, more performant
71 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
72 uint8_t *iv, int ivlen, int srclen,
75 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
77 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
78 uint8_t *encr = encrypted_iv;
80 /* ECB method: encrypt the IV, then XOR this with plaintext */
81 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
83 goto cipher_encrypt_err;
85 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
91 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
95 /** Decrypt a single partial block
96 * Depends on openssl libcrypto
97 * Uses ECB+XOR to do CFB encryption, same result, more performant
100 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
101 uint8_t *iv, int ivlen, int srclen,
104 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
106 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
107 uint8_t *encr = encrypted_iv;
109 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
110 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
112 goto cipher_decrypt_err;
114 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
120 PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
124 /** Creates a context in either AES or DES in ECB mode
125 * Depends on openssl libcrypto
128 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
129 enum rte_crypto_cipher_operation direction __rte_unused,
130 uint8_t *key, void **ctx)
132 const EVP_CIPHER *algo = NULL;
134 *ctx = EVP_CIPHER_CTX_new();
141 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
142 algo = EVP_des_ecb();
144 algo = EVP_aes_128_ecb();
146 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
147 if (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {
156 EVP_CIPHER_CTX_free(*ctx);
160 /** Frees a context previously created
161 * Depends on openssl libcrypto
164 bpi_cipher_ctx_free(void *bpi_ctx)
167 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
170 static inline uint32_t
171 adf_modulo(uint32_t data, uint32_t shift);
174 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
175 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
178 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
179 struct rte_cryptodev_sym_session *sess)
181 PMD_INIT_FUNC_TRACE();
182 uint8_t index = dev->driver_id;
183 void *sess_priv = get_session_private_data(sess, index);
184 struct qat_session *s = (struct qat_session *)sess_priv;
188 bpi_cipher_ctx_free(s->bpi_ctx);
189 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
190 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
191 set_session_private_data(sess, index, NULL);
192 rte_mempool_put(sess_mp, sess_priv);
197 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
200 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
201 return ICP_QAT_FW_LA_CMD_CIPHER;
203 /* Authentication Only */
204 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
205 return ICP_QAT_FW_LA_CMD_AUTH;
208 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
209 /* AES-GCM and AES-CCM works with different direction
210 * GCM first encrypts and generate hash where AES-CCM
211 * first generate hash and encrypts. Similar relation
212 * applies to decryption.
214 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
215 if (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)
216 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
218 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
220 if (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)
221 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
223 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
226 if (xform->next == NULL)
229 /* Cipher then Authenticate */
230 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
231 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
232 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
234 /* Authenticate then Cipher */
235 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
236 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
237 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
242 static struct rte_crypto_auth_xform *
243 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
255 static struct rte_crypto_cipher_xform *
256 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
259 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
260 return &xform->cipher;
269 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
270 struct rte_crypto_sym_xform *xform,
271 struct qat_session *session)
273 struct qat_pmd_private *internals = dev->data->dev_private;
274 struct rte_crypto_cipher_xform *cipher_xform = NULL;
277 /* Get cipher xform from crypto xform chain */
278 cipher_xform = qat_get_cipher_xform(xform);
280 session->cipher_iv.offset = cipher_xform->iv.offset;
281 session->cipher_iv.length = cipher_xform->iv.length;
283 switch (cipher_xform->algo) {
284 case RTE_CRYPTO_CIPHER_AES_CBC:
285 if (qat_alg_validate_aes_key(cipher_xform->key.length,
286 &session->qat_cipher_alg) != 0) {
287 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
291 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
293 case RTE_CRYPTO_CIPHER_AES_CTR:
294 if (qat_alg_validate_aes_key(cipher_xform->key.length,
295 &session->qat_cipher_alg) != 0) {
296 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
300 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
302 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
303 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
304 &session->qat_cipher_alg) != 0) {
305 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
309 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
311 case RTE_CRYPTO_CIPHER_NULL:
312 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
314 case RTE_CRYPTO_CIPHER_KASUMI_F8:
315 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
316 &session->qat_cipher_alg) != 0) {
317 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
321 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
323 case RTE_CRYPTO_CIPHER_3DES_CBC:
324 if (qat_alg_validate_3des_key(cipher_xform->key.length,
325 &session->qat_cipher_alg) != 0) {
326 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
330 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
332 case RTE_CRYPTO_CIPHER_DES_CBC:
333 if (qat_alg_validate_des_key(cipher_xform->key.length,
334 &session->qat_cipher_alg) != 0) {
335 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
339 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
341 case RTE_CRYPTO_CIPHER_3DES_CTR:
342 if (qat_alg_validate_3des_key(cipher_xform->key.length,
343 &session->qat_cipher_alg) != 0) {
344 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
348 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
350 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
351 ret = bpi_cipher_ctx_init(
354 cipher_xform->key.data,
357 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
360 if (qat_alg_validate_des_key(cipher_xform->key.length,
361 &session->qat_cipher_alg) != 0) {
362 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
366 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
368 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
369 ret = bpi_cipher_ctx_init(
372 cipher_xform->key.data,
375 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
378 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
379 &session->qat_cipher_alg) != 0) {
380 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
384 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
386 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
387 if (!qat_is_cipher_alg_supported(
388 cipher_xform->algo, internals)) {
389 PMD_DRV_LOG(ERR, "%s not supported on this device",
390 rte_crypto_cipher_algorithm_strings
391 [cipher_xform->algo]);
395 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
396 &session->qat_cipher_alg) != 0) {
397 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
401 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
403 case RTE_CRYPTO_CIPHER_3DES_ECB:
404 case RTE_CRYPTO_CIPHER_AES_ECB:
405 case RTE_CRYPTO_CIPHER_AES_F8:
406 case RTE_CRYPTO_CIPHER_AES_XTS:
407 case RTE_CRYPTO_CIPHER_ARC4:
408 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
413 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
419 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
420 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
422 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
424 if (qat_alg_aead_session_create_content_desc_cipher(session,
425 cipher_xform->key.data,
426 cipher_xform->key.length)) {
434 if (session->bpi_ctx) {
435 bpi_cipher_ctx_free(session->bpi_ctx);
436 session->bpi_ctx = NULL;
442 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
443 struct rte_crypto_sym_xform *xform,
444 struct rte_cryptodev_sym_session *sess,
445 struct rte_mempool *mempool)
447 void *sess_private_data;
450 if (rte_mempool_get(mempool, &sess_private_data)) {
452 "Couldn't get object from session mempool");
456 ret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);
458 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
459 "session parameters");
461 /* Return session to mempool */
462 rte_mempool_put(mempool, sess_private_data);
466 set_session_private_data(sess, dev->driver_id,
473 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
474 struct rte_crypto_sym_xform *xform, void *session_private)
476 struct qat_session *session = session_private;
480 PMD_INIT_FUNC_TRACE();
482 /* Set context descriptor physical address */
483 session->cd_paddr = rte_mempool_virt2iova(session) +
484 offsetof(struct qat_session, cd);
486 session->min_qat_dev_gen = QAT_GEN1;
488 /* Get requested QAT command id */
489 qat_cmd_id = qat_get_cmd_id(xform);
490 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
491 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
494 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
495 switch (session->qat_cmd) {
496 case ICP_QAT_FW_LA_CMD_CIPHER:
497 ret = qat_crypto_sym_configure_session_cipher(dev, xform, session);
501 case ICP_QAT_FW_LA_CMD_AUTH:
502 ret = qat_crypto_sym_configure_session_auth(dev, xform, session);
506 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
507 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
508 ret = qat_crypto_sym_configure_session_aead(xform,
513 ret = qat_crypto_sym_configure_session_cipher(dev,
517 ret = qat_crypto_sym_configure_session_auth(dev,
523 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
524 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
525 ret = qat_crypto_sym_configure_session_aead(xform,
530 ret = qat_crypto_sym_configure_session_auth(dev,
534 ret = qat_crypto_sym_configure_session_cipher(dev,
540 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
541 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
542 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
543 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
544 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
545 case ICP_QAT_FW_LA_CMD_MGF1:
546 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
547 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
548 case ICP_QAT_FW_LA_CMD_DELIMITER:
549 PMD_DRV_LOG(ERR, "Unsupported Service %u",
553 PMD_DRV_LOG(ERR, "Unsupported Service %u",
562 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
563 struct rte_crypto_sym_xform *xform,
564 struct qat_session *session)
566 struct rte_crypto_auth_xform *auth_xform = NULL;
567 struct qat_pmd_private *internals = dev->data->dev_private;
568 auth_xform = qat_get_auth_xform(xform);
569 uint8_t *key_data = auth_xform->key.data;
570 uint8_t key_length = auth_xform->key.length;
572 switch (auth_xform->algo) {
573 case RTE_CRYPTO_AUTH_SHA1_HMAC:
574 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
576 case RTE_CRYPTO_AUTH_SHA224_HMAC:
577 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
579 case RTE_CRYPTO_AUTH_SHA256_HMAC:
580 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
582 case RTE_CRYPTO_AUTH_SHA384_HMAC:
583 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
585 case RTE_CRYPTO_AUTH_SHA512_HMAC:
586 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
588 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
589 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
591 case RTE_CRYPTO_AUTH_AES_GMAC:
592 if (qat_alg_validate_aes_key(auth_xform->key.length,
593 &session->qat_cipher_alg) != 0) {
594 PMD_DRV_LOG(ERR, "Invalid AES key size");
597 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
598 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
601 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
602 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
604 case RTE_CRYPTO_AUTH_MD5_HMAC:
605 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
607 case RTE_CRYPTO_AUTH_NULL:
608 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
610 case RTE_CRYPTO_AUTH_KASUMI_F9:
611 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
613 case RTE_CRYPTO_AUTH_ZUC_EIA3:
614 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
615 PMD_DRV_LOG(ERR, "%s not supported on this device",
616 rte_crypto_auth_algorithm_strings
620 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
622 case RTE_CRYPTO_AUTH_SHA1:
623 case RTE_CRYPTO_AUTH_SHA256:
624 case RTE_CRYPTO_AUTH_SHA512:
625 case RTE_CRYPTO_AUTH_SHA224:
626 case RTE_CRYPTO_AUTH_SHA384:
627 case RTE_CRYPTO_AUTH_MD5:
628 case RTE_CRYPTO_AUTH_AES_CMAC:
629 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
630 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
634 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
639 session->auth_iv.offset = auth_xform->iv.offset;
640 session->auth_iv.length = auth_xform->iv.length;
642 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
643 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
644 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
645 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
647 * It needs to create cipher desc content first,
648 * then authentication
650 if (qat_alg_aead_session_create_content_desc_cipher(session,
651 auth_xform->key.data,
652 auth_xform->key.length))
655 if (qat_alg_aead_session_create_content_desc_auth(session,
659 auth_xform->digest_length,
663 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
664 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
666 * It needs to create authentication desc content first,
669 if (qat_alg_aead_session_create_content_desc_auth(session,
673 auth_xform->digest_length,
677 if (qat_alg_aead_session_create_content_desc_cipher(session,
678 auth_xform->key.data,
679 auth_xform->key.length))
682 /* Restore to authentication only only */
683 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
685 if (qat_alg_aead_session_create_content_desc_auth(session,
689 auth_xform->digest_length,
694 session->digest_length = auth_xform->digest_length;
699 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
700 struct qat_session *session)
702 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
703 enum rte_crypto_auth_operation crypto_operation;
706 * Store AEAD IV parameters as cipher IV,
707 * to avoid unnecessary memory usage
709 session->cipher_iv.offset = xform->aead.iv.offset;
710 session->cipher_iv.length = xform->aead.iv.length;
712 switch (aead_xform->algo) {
713 case RTE_CRYPTO_AEAD_AES_GCM:
714 if (qat_alg_validate_aes_key(aead_xform->key.length,
715 &session->qat_cipher_alg) != 0) {
716 PMD_DRV_LOG(ERR, "Invalid AES key size");
719 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
720 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
722 case RTE_CRYPTO_AEAD_AES_CCM:
723 if (qat_alg_validate_aes_key(aead_xform->key.length,
724 &session->qat_cipher_alg) != 0) {
725 PMD_DRV_LOG(ERR, "Invalid AES key size");
728 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
729 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;
732 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
737 if ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
738 aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||
739 (aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
740 aead_xform->algo == RTE_CRYPTO_AEAD_AES_CCM)) {
741 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
743 * It needs to create cipher desc content first,
744 * then authentication
747 crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
748 RTE_CRYPTO_AUTH_OP_GENERATE : RTE_CRYPTO_AUTH_OP_VERIFY;
750 if (qat_alg_aead_session_create_content_desc_cipher(session,
751 aead_xform->key.data,
752 aead_xform->key.length))
755 if (qat_alg_aead_session_create_content_desc_auth(session,
756 aead_xform->key.data,
757 aead_xform->key.length,
758 aead_xform->aad_length,
759 aead_xform->digest_length,
763 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
765 * It needs to create authentication desc content first,
769 crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
770 RTE_CRYPTO_AUTH_OP_VERIFY : RTE_CRYPTO_AUTH_OP_GENERATE;
772 if (qat_alg_aead_session_create_content_desc_auth(session,
773 aead_xform->key.data,
774 aead_xform->key.length,
775 aead_xform->aad_length,
776 aead_xform->digest_length,
780 if (qat_alg_aead_session_create_content_desc_cipher(session,
781 aead_xform->key.data,
782 aead_xform->key.length))
786 session->digest_length = aead_xform->digest_length;
790 unsigned qat_crypto_sym_get_session_private_size(
791 struct rte_cryptodev *dev __rte_unused)
793 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
796 static inline uint32_t
797 qat_bpicipher_preprocess(struct qat_session *ctx,
798 struct rte_crypto_op *op)
800 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
801 struct rte_crypto_sym_op *sym_op = op->sym;
802 uint8_t last_block_len = block_len > 0 ?
803 sym_op->cipher.data.length % block_len : 0;
805 if (last_block_len &&
806 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
808 /* Decrypt last block */
809 uint8_t *last_block, *dst, *iv;
810 uint32_t last_block_offset = sym_op->cipher.data.offset +
811 sym_op->cipher.data.length - last_block_len;
812 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
813 uint8_t *, last_block_offset);
815 if (unlikely(sym_op->m_dst != NULL))
816 /* out-of-place operation (OOP) */
817 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
818 uint8_t *, last_block_offset);
822 if (last_block_len < sym_op->cipher.data.length)
823 /* use previous block ciphertext as IV */
824 iv = last_block - block_len;
826 /* runt block, i.e. less than one full block */
827 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
828 ctx->cipher_iv.offset);
830 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
831 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
833 if (sym_op->m_dst != NULL)
834 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
837 bpi_cipher_decrypt(last_block, dst, iv, block_len,
838 last_block_len, ctx->bpi_ctx);
839 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
840 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
842 if (sym_op->m_dst != NULL)
843 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
848 return sym_op->cipher.data.length - last_block_len;
851 static inline uint32_t
852 qat_bpicipher_postprocess(struct qat_session *ctx,
853 struct rte_crypto_op *op)
855 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
856 struct rte_crypto_sym_op *sym_op = op->sym;
857 uint8_t last_block_len = block_len > 0 ?
858 sym_op->cipher.data.length % block_len : 0;
860 if (last_block_len > 0 &&
861 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
863 /* Encrypt last block */
864 uint8_t *last_block, *dst, *iv;
865 uint32_t last_block_offset;
867 last_block_offset = sym_op->cipher.data.offset +
868 sym_op->cipher.data.length - last_block_len;
869 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
870 uint8_t *, last_block_offset);
872 if (unlikely(sym_op->m_dst != NULL))
873 /* out-of-place operation (OOP) */
874 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
875 uint8_t *, last_block_offset);
879 if (last_block_len < sym_op->cipher.data.length)
880 /* use previous block ciphertext as IV */
881 iv = dst - block_len;
883 /* runt block, i.e. less than one full block */
884 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
885 ctx->cipher_iv.offset);
887 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
888 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
890 if (sym_op->m_dst != NULL)
891 rte_hexdump(stdout, "BPI: dst before post-process:",
892 dst, last_block_len);
894 bpi_cipher_encrypt(last_block, dst, iv, block_len,
895 last_block_len, ctx->bpi_ctx);
896 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
897 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
899 if (sym_op->m_dst != NULL)
900 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
904 return sym_op->cipher.data.length - last_block_len;
908 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
909 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
910 q->hw_queue_number, q->tail);
911 q->nb_pending_requests = 0;
912 q->csr_tail = q->tail;
916 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
919 register struct qat_queue *queue;
920 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
921 register uint32_t nb_ops_sent = 0;
922 register struct rte_crypto_op **cur_op = ops;
924 uint16_t nb_ops_possible = nb_ops;
925 register uint8_t *base_addr;
926 register uint32_t tail;
929 if (unlikely(nb_ops == 0))
932 /* read params used a lot in main loop into registers */
933 queue = &(tmp_qp->tx_q);
934 base_addr = (uint8_t *)queue->base_addr;
937 /* Find how many can actually fit on the ring */
938 tmp_qp->inflights16 += nb_ops;
939 overflow = tmp_qp->inflights16 - queue->max_inflights;
941 tmp_qp->inflights16 -= overflow;
942 nb_ops_possible = nb_ops - overflow;
943 if (nb_ops_possible == 0)
947 while (nb_ops_sent != nb_ops_possible) {
948 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
949 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
951 tmp_qp->stats.enqueue_err_count++;
953 * This message cannot be enqueued,
954 * decrease number of ops that wasn't sent
956 tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
957 if (nb_ops_sent == 0)
962 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
968 tmp_qp->stats.enqueued_count += nb_ops_sent;
969 queue->nb_pending_requests += nb_ops_sent;
970 if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
971 queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
972 txq_write_tail(tmp_qp, queue);
978 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
980 uint32_t old_head, new_head;
983 old_head = q->csr_head;
985 max_head = qp->nb_descriptors * q->msg_size;
987 /* write out free descriptors */
988 void *cur_desc = (uint8_t *)q->base_addr + old_head;
990 if (new_head < old_head) {
991 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
992 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
994 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
996 q->nb_processed_responses = 0;
997 q->csr_head = new_head;
999 /* write current head to CSR */
1000 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
1001 q->hw_queue_number, new_head);
1005 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
1008 struct qat_queue *rx_queue, *tx_queue;
1009 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
1010 uint32_t msg_counter = 0;
1011 struct rte_crypto_op *rx_op;
1012 struct icp_qat_fw_comn_resp *resp_msg;
1015 rx_queue = &(tmp_qp->rx_q);
1016 tx_queue = &(tmp_qp->tx_q);
1017 head = rx_queue->head;
1018 resp_msg = (struct icp_qat_fw_comn_resp *)
1019 ((uint8_t *)rx_queue->base_addr + head);
1021 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
1022 msg_counter != nb_ops) {
1023 rx_op = (struct rte_crypto_op *)(uintptr_t)
1024 (resp_msg->opaque_data);
1026 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1027 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
1028 sizeof(struct icp_qat_fw_comn_resp));
1030 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
1031 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
1032 resp_msg->comn_hdr.comn_status)) {
1033 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1035 struct qat_session *sess = (struct qat_session *)
1036 get_session_private_data(
1037 rx_op->sym->session,
1038 cryptodev_qat_driver_id);
1041 qat_bpicipher_postprocess(sess, rx_op);
1042 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1045 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
1046 resp_msg = (struct icp_qat_fw_comn_resp *)
1047 ((uint8_t *)rx_queue->base_addr + head);
1052 if (msg_counter > 0) {
1053 rx_queue->head = head;
1054 tmp_qp->stats.dequeued_count += msg_counter;
1055 rx_queue->nb_processed_responses += msg_counter;
1056 tmp_qp->inflights16 -= msg_counter;
1058 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
1059 rxq_free_desc(tmp_qp, rx_queue);
1061 /* also check if tail needs to be advanced */
1062 if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
1063 tx_queue->tail != tx_queue->csr_tail) {
1064 txq_write_tail(tmp_qp, tx_queue);
1070 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1071 struct qat_alg_buf_list *list, uint32_t data_len)
1075 uint32_t buf_len = rte_pktmbuf_iova(buf) -
1076 buff_start + rte_pktmbuf_data_len(buf);
1078 list->bufers[0].addr = buff_start;
1079 list->bufers[0].resrvd = 0;
1080 list->bufers[0].len = buf_len;
1082 if (data_len <= buf_len) {
1083 list->num_bufs = nr;
1084 list->bufers[0].len = data_len;
1090 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1091 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1093 QAT_SGL_MAX_NUMBER);
1097 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1098 list->bufers[nr].resrvd = 0;
1099 list->bufers[nr].addr = rte_pktmbuf_iova(buf);
1101 buf_len += list->bufers[nr].len;
1104 if (buf_len > data_len) {
1105 list->bufers[nr].len -=
1111 list->num_bufs = nr;
1117 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1118 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1119 struct rte_crypto_op *op,
1120 struct icp_qat_fw_la_bulk_req *qat_req)
1122 /* copy IV into request if it fits */
1123 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1124 rte_memcpy(cipher_param->u.cipher_IV_array,
1125 rte_crypto_op_ctod_offset(op, uint8_t *,
1129 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1130 qat_req->comn_hdr.serv_specif_flags,
1131 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1132 cipher_param->u.s.cipher_IV_ptr =
1133 rte_crypto_op_ctophys_offset(op,
1138 /** Set IV for CCM is special case, 0th byte is set to q-1
1139 * where q is padding of nonce in 16 byte block
1142 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
1143 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1144 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
1146 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
1147 ICP_QAT_HW_CCM_NONCE_OFFSET,
1148 rte_crypto_op_ctod_offset(op, uint8_t *,
1149 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
1151 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
1152 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
1154 if (aad_len_field_sz)
1155 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
1156 rte_crypto_op_ctod_offset(op, uint8_t *,
1157 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
1162 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1163 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1166 struct qat_session *ctx;
1167 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1168 struct icp_qat_fw_la_auth_req_params *auth_param;
1169 register struct icp_qat_fw_la_bulk_req *qat_req;
1170 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1171 uint32_t cipher_len = 0, cipher_ofs = 0;
1172 uint32_t auth_len = 0, auth_ofs = 0;
1173 uint32_t min_ofs = 0;
1174 uint64_t src_buf_start = 0, dst_buf_start = 0;
1177 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1178 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1179 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1180 "operation requests, op (%p) is not a "
1181 "symmetric operation.", op);
1185 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1186 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1187 " requests, op (%p) is sessionless.", op);
1191 ctx = (struct qat_session *)get_session_private_data(
1192 op->sym->session, cryptodev_qat_driver_id);
1194 if (unlikely(ctx == NULL)) {
1195 PMD_DRV_LOG(ERR, "Session was not created for this device");
1199 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1200 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1201 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1207 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1208 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1209 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1210 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1211 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1213 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1214 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1215 /* AES-GCM or AES-CCM */
1216 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1217 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
1218 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
1219 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
1220 && ctx->qat_hash_alg ==
1221 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
1227 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1230 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1237 if (ctx->qat_cipher_alg ==
1238 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1239 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1240 ctx->qat_cipher_alg ==
1241 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1244 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1245 || (cipher_param->cipher_offset
1246 % BYTE_LENGTH != 0))) {
1248 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1249 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1252 cipher_len = op->sym->cipher.data.length >> 3;
1253 cipher_ofs = op->sym->cipher.data.offset >> 3;
1255 } else if (ctx->bpi_ctx) {
1256 /* DOCSIS - only send complete blocks to device
1257 * Process any partial block using CFB mode.
1258 * Even if 0 complete blocks, still send this to device
1259 * to get into rx queue for post-process and dequeuing
1261 cipher_len = qat_bpicipher_preprocess(ctx, op);
1262 cipher_ofs = op->sym->cipher.data.offset;
1264 cipher_len = op->sym->cipher.data.length;
1265 cipher_ofs = op->sym->cipher.data.offset;
1268 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1269 cipher_param, op, qat_req);
1270 min_ofs = cipher_ofs;
1275 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1276 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1277 ctx->qat_hash_alg ==
1278 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1279 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1280 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1282 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1283 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1286 auth_ofs = op->sym->auth.data.offset >> 3;
1287 auth_len = op->sym->auth.data.length >> 3;
1289 auth_param->u1.aad_adr =
1290 rte_crypto_op_ctophys_offset(op,
1291 ctx->auth_iv.offset);
1293 } else if (ctx->qat_hash_alg ==
1294 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1295 ctx->qat_hash_alg ==
1296 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1298 set_cipher_iv(ctx->auth_iv.length,
1299 ctx->auth_iv.offset,
1300 cipher_param, op, qat_req);
1301 auth_ofs = op->sym->auth.data.offset;
1302 auth_len = op->sym->auth.data.length;
1304 auth_param->u1.aad_adr = 0;
1305 auth_param->u2.aad_sz = 0;
1308 * If len(iv)==12B fw computes J0
1310 if (ctx->auth_iv.length == 12) {
1311 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1312 qat_req->comn_hdr.serv_specif_flags,
1313 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1317 auth_ofs = op->sym->auth.data.offset;
1318 auth_len = op->sym->auth.data.length;
1323 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
1324 auth_param->auth_res_addr =
1325 op->sym->auth.digest.phys_addr;
1331 * This address may used for setting AAD physical pointer
1332 * into IV offset from op
1334 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
1335 if (ctx->qat_hash_alg ==
1336 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1337 ctx->qat_hash_alg ==
1338 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1340 * If len(iv)==12B fw computes J0
1342 if (ctx->cipher_iv.length == 12) {
1343 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1344 qat_req->comn_hdr.serv_specif_flags,
1345 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1348 set_cipher_iv(ctx->cipher_iv.length,
1349 ctx->cipher_iv.offset,
1350 cipher_param, op, qat_req);
1352 } else if (ctx->qat_hash_alg ==
1353 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
1355 /* In case of AES-CCM this may point to user selected memory
1356 * or iv offset in cypto_op
1358 uint8_t *aad_data = op->sym->aead.aad.data;
1359 /* This is true AAD length, it not includes 18 bytes of
1362 uint8_t aad_ccm_real_len = 0;
1364 uint8_t aad_len_field_sz = 0;
1365 uint32_t msg_len_be =
1366 rte_bswap32(op->sym->aead.data.length);
1368 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
1369 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
1370 aad_ccm_real_len = ctx->aad_len -
1371 ICP_QAT_HW_CCM_AAD_B0_LEN -
1372 ICP_QAT_HW_CCM_AAD_LEN_INFO;
1375 * aad_len not greater than 18, so no actual aad data,
1376 * then use IV after op for B0 block
1378 aad_data = rte_crypto_op_ctod_offset(op, uint8_t *,
1379 ctx->cipher_iv.offset);
1380 aad_phys_addr_aead =
1381 rte_crypto_op_ctophys_offset(op,
1382 ctx->cipher_iv.offset);
1385 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST - ctx->cipher_iv.length;
1387 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(aad_len_field_sz,
1388 ctx->digest_length, q);
1390 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
1391 memcpy(aad_data + ctx->cipher_iv.length +
1392 ICP_QAT_HW_CCM_NONCE_OFFSET
1393 + (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
1394 (uint8_t *)&msg_len_be,
1395 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
1397 memcpy(aad_data + ctx->cipher_iv.length +
1398 ICP_QAT_HW_CCM_NONCE_OFFSET,
1399 (uint8_t *)&msg_len_be
1400 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
1404 if (aad_len_field_sz > 0) {
1405 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
1406 = rte_bswap16(aad_ccm_real_len);
1408 if ((aad_ccm_real_len + aad_len_field_sz)
1409 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
1410 uint8_t pad_len = 0;
1411 uint8_t pad_idx = 0;
1413 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
1414 ((aad_ccm_real_len + aad_len_field_sz) %
1415 ICP_QAT_HW_CCM_AAD_B0_LEN);
1416 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
1417 aad_ccm_real_len + aad_len_field_sz;
1418 memset(&aad_data[pad_idx],
1424 set_cipher_iv_ccm(ctx->cipher_iv.length,
1425 ctx->cipher_iv.offset,
1426 cipher_param, op, q,
1431 cipher_len = op->sym->aead.data.length;
1432 cipher_ofs = op->sym->aead.data.offset;
1433 auth_len = op->sym->aead.data.length;
1434 auth_ofs = op->sym->aead.data.offset;
1436 auth_param->u1.aad_adr = aad_phys_addr_aead;
1437 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1438 min_ofs = op->sym->aead.data.offset;
1441 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1444 /* adjust for chain case */
1445 if (do_cipher && do_auth)
1446 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1448 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1451 if (unlikely(op->sym->m_dst != NULL)) {
1452 /* Out-of-place operation (OOP)
1453 * Don't align DMA start. DMA the minimum data-set
1454 * so as not to overwrite data in dest buffer
1457 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
1459 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
1462 /* In-place operation
1463 * Start DMA at nearest aligned address below min_ofs
1466 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
1467 & QAT_64_BTYE_ALIGN_MASK;
1469 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
1470 rte_pktmbuf_headroom(op->sym->m_src))
1472 /* alignment has pushed addr ahead of start of mbuf
1473 * so revert and take the performance hit
1476 rte_pktmbuf_iova_offset(op->sym->m_src,
1479 dst_buf_start = src_buf_start;
1482 if (do_cipher || do_aead) {
1483 cipher_param->cipher_offset =
1484 (uint32_t)rte_pktmbuf_iova_offset(
1485 op->sym->m_src, cipher_ofs) - src_buf_start;
1486 cipher_param->cipher_length = cipher_len;
1488 cipher_param->cipher_offset = 0;
1489 cipher_param->cipher_length = 0;
1492 if (do_auth || do_aead) {
1493 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
1494 op->sym->m_src, auth_ofs) - src_buf_start;
1495 auth_param->auth_len = auth_len;
1497 auth_param->auth_off = 0;
1498 auth_param->auth_len = 0;
1501 qat_req->comn_mid.dst_length =
1502 qat_req->comn_mid.src_length =
1503 (cipher_param->cipher_offset + cipher_param->cipher_length)
1504 > (auth_param->auth_off + auth_param->auth_len) ?
1505 (cipher_param->cipher_offset + cipher_param->cipher_length)
1506 : (auth_param->auth_off + auth_param->auth_len);
1510 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1511 QAT_COMN_PTR_TYPE_SGL);
1512 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1513 &qat_op_cookie->qat_sgl_list_src,
1514 qat_req->comn_mid.src_length);
1516 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1520 if (likely(op->sym->m_dst == NULL))
1521 qat_req->comn_mid.dest_data_addr =
1522 qat_req->comn_mid.src_data_addr =
1523 qat_op_cookie->qat_sgl_src_phys_addr;
1525 ret = qat_sgl_fill_array(op->sym->m_dst,
1527 &qat_op_cookie->qat_sgl_list_dst,
1528 qat_req->comn_mid.dst_length);
1531 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1536 qat_req->comn_mid.src_data_addr =
1537 qat_op_cookie->qat_sgl_src_phys_addr;
1538 qat_req->comn_mid.dest_data_addr =
1539 qat_op_cookie->qat_sgl_dst_phys_addr;
1542 qat_req->comn_mid.src_data_addr = src_buf_start;
1543 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1546 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1547 rte_hexdump(stdout, "qat_req:", qat_req,
1548 sizeof(struct icp_qat_fw_la_bulk_req));
1549 rte_hexdump(stdout, "src_data:",
1550 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1551 rte_pktmbuf_data_len(op->sym->m_src));
1553 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1555 ctx->cipher_iv.offset);
1556 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1557 ctx->cipher_iv.length);
1561 if (ctx->auth_iv.length) {
1562 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1564 ctx->auth_iv.offset);
1565 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1566 ctx->auth_iv.length);
1568 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1569 ctx->digest_length);
1573 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1574 ctx->digest_length);
1575 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1582 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1584 uint32_t div = data >> shift;
1585 uint32_t mult = div << shift;
1590 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1591 struct rte_cryptodev_stats *stats)
1594 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1596 PMD_INIT_FUNC_TRACE();
1597 if (stats == NULL) {
1598 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1601 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1602 if (qp[i] == NULL) {
1603 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1607 stats->enqueued_count += qp[i]->stats.enqueued_count;
1608 stats->dequeued_count += qp[i]->stats.dequeued_count;
1609 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1610 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1614 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1617 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1619 PMD_INIT_FUNC_TRACE();
1620 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1621 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1622 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");