4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
58 #include <rte_mempool.h>
60 #include <rte_string_fns.h>
61 #include <rte_spinlock.h>
62 #include <rte_hexdump.h>
66 #include "qat_crypto.h"
67 #include "adf_transport_access_macros.h"
71 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
73 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
75 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
77 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
94 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
96 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
98 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
115 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
117 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
119 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
136 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
138 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
140 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
156 { /* AES GCM (AUTH) */
157 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
159 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
161 .algo = RTE_CRYPTO_AUTH_AES_GCM,
181 { /* SNOW3G (UIA2) */
182 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
184 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
186 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
206 { /* AES GCM (CIPHER) */
207 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
209 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
211 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
227 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
229 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
231 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
246 { /* SNOW3G (UEA2) */
247 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
249 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
251 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
266 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
269 static inline uint32_t
270 adf_modulo(uint32_t data, uint32_t shift);
273 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
275 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
278 struct qat_session *sess = session;
279 phys_addr_t cd_paddr = sess->cd_paddr;
281 PMD_INIT_FUNC_TRACE();
283 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
285 sess->cd_paddr = cd_paddr;
290 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
293 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
294 return ICP_QAT_FW_LA_CMD_CIPHER;
296 /* Authentication Only */
297 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
298 return ICP_QAT_FW_LA_CMD_AUTH;
300 if (xform->next == NULL)
303 /* Cipher then Authenticate */
304 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
305 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
306 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
308 /* Authenticate then Cipher */
309 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
310 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
311 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
316 static struct rte_crypto_auth_xform *
317 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
320 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
329 static struct rte_crypto_cipher_xform *
330 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
333 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
334 return &xform->cipher;
342 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
343 struct rte_crypto_sym_xform *xform, void *session_private)
345 struct qat_pmd_private *internals = dev->data->dev_private;
347 struct qat_session *session = session_private;
349 struct rte_crypto_cipher_xform *cipher_xform = NULL;
351 /* Get cipher xform from crypto xform chain */
352 cipher_xform = qat_get_cipher_xform(xform);
354 switch (cipher_xform->algo) {
355 case RTE_CRYPTO_CIPHER_AES_CBC:
356 if (qat_alg_validate_aes_key(cipher_xform->key.length,
357 &session->qat_cipher_alg) != 0) {
358 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
361 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
363 case RTE_CRYPTO_CIPHER_AES_GCM:
364 if (qat_alg_validate_aes_key(cipher_xform->key.length,
365 &session->qat_cipher_alg) != 0) {
366 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
369 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
371 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
372 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
373 &session->qat_cipher_alg) != 0) {
374 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
377 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
379 case RTE_CRYPTO_CIPHER_NULL:
380 case RTE_CRYPTO_CIPHER_3DES_ECB:
381 case RTE_CRYPTO_CIPHER_3DES_CBC:
382 case RTE_CRYPTO_CIPHER_AES_ECB:
383 case RTE_CRYPTO_CIPHER_AES_CTR:
384 case RTE_CRYPTO_CIPHER_AES_CCM:
385 case RTE_CRYPTO_CIPHER_KASUMI_F8:
386 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
390 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
395 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
396 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
398 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
400 if (qat_alg_aead_session_create_content_desc_cipher(session,
401 cipher_xform->key.data,
402 cipher_xform->key.length))
408 rte_mempool_put(internals->sess_mp, session);
414 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
415 struct rte_crypto_sym_xform *xform, void *session_private)
417 struct qat_pmd_private *internals = dev->data->dev_private;
419 struct qat_session *session = session_private;
423 PMD_INIT_FUNC_TRACE();
425 /* Get requested QAT command id */
426 qat_cmd_id = qat_get_cmd_id(xform);
427 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
428 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
431 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
432 switch (session->qat_cmd) {
433 case ICP_QAT_FW_LA_CMD_CIPHER:
434 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
436 case ICP_QAT_FW_LA_CMD_AUTH:
437 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
439 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
440 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
441 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
443 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
444 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
445 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
447 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
448 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
449 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
450 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
451 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
452 case ICP_QAT_FW_LA_CMD_MGF1:
453 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
454 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
455 case ICP_QAT_FW_LA_CMD_DELIMITER:
456 PMD_DRV_LOG(ERR, "Unsupported Service %u",
460 PMD_DRV_LOG(ERR, "Unsupported Service %u",
467 rte_mempool_put(internals->sess_mp, session);
472 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
473 struct rte_crypto_sym_xform *xform,
474 struct qat_session *session_private)
477 struct qat_pmd_private *internals = dev->data->dev_private;
478 struct qat_session *session = session_private;
479 struct rte_crypto_auth_xform *auth_xform = NULL;
480 struct rte_crypto_cipher_xform *cipher_xform = NULL;
481 auth_xform = qat_get_auth_xform(xform);
483 switch (auth_xform->algo) {
484 case RTE_CRYPTO_AUTH_SHA1_HMAC:
485 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
487 case RTE_CRYPTO_AUTH_SHA256_HMAC:
488 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
490 case RTE_CRYPTO_AUTH_SHA512_HMAC:
491 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
493 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
494 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
496 case RTE_CRYPTO_AUTH_AES_GCM:
497 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
499 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
500 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
502 case RTE_CRYPTO_AUTH_NULL:
503 case RTE_CRYPTO_AUTH_SHA1:
504 case RTE_CRYPTO_AUTH_SHA256:
505 case RTE_CRYPTO_AUTH_SHA512:
506 case RTE_CRYPTO_AUTH_SHA224:
507 case RTE_CRYPTO_AUTH_SHA224_HMAC:
508 case RTE_CRYPTO_AUTH_SHA384:
509 case RTE_CRYPTO_AUTH_SHA384_HMAC:
510 case RTE_CRYPTO_AUTH_MD5:
511 case RTE_CRYPTO_AUTH_MD5_HMAC:
512 case RTE_CRYPTO_AUTH_AES_CCM:
513 case RTE_CRYPTO_AUTH_AES_GMAC:
514 case RTE_CRYPTO_AUTH_KASUMI_F9:
515 case RTE_CRYPTO_AUTH_AES_CMAC:
516 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
517 case RTE_CRYPTO_AUTH_ZUC_EIA3:
518 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
522 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
526 cipher_xform = qat_get_cipher_xform(xform);
528 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
529 (session->qat_hash_alg ==
530 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
531 if (qat_alg_aead_session_create_content_desc_auth(session,
532 cipher_xform->key.data,
533 cipher_xform->key.length,
534 auth_xform->add_auth_data_length,
535 auth_xform->digest_length))
538 if (qat_alg_aead_session_create_content_desc_auth(session,
539 auth_xform->key.data,
540 auth_xform->key.length,
541 auth_xform->add_auth_data_length,
542 auth_xform->digest_length))
548 rte_mempool_put(internals->sess_mp, session);
552 unsigned qat_crypto_sym_get_session_private_size(
553 struct rte_cryptodev *dev __rte_unused)
555 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
560 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
563 register struct qat_queue *queue;
564 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
565 register uint32_t nb_ops_sent = 0;
566 register struct rte_crypto_op **cur_op = ops;
568 uint16_t nb_ops_possible = nb_ops;
569 register uint8_t *base_addr;
570 register uint32_t tail;
573 if (unlikely(nb_ops == 0))
576 /* read params used a lot in main loop into registers */
577 queue = &(tmp_qp->tx_q);
578 base_addr = (uint8_t *)queue->base_addr;
581 /* Find how many can actually fit on the ring */
582 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
583 - queue->max_inflights;
585 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
586 nb_ops_possible = nb_ops - overflow;
587 if (nb_ops_possible == 0)
591 while (nb_ops_sent != nb_ops_possible) {
592 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
594 tmp_qp->stats.enqueue_err_count++;
595 if (nb_ops_sent == 0)
600 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
605 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
606 queue->hw_queue_number, tail);
608 tmp_qp->stats.enqueued_count += nb_ops_sent;
613 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
616 struct qat_queue *queue;
617 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
618 uint32_t msg_counter = 0;
619 struct rte_crypto_op *rx_op;
620 struct icp_qat_fw_comn_resp *resp_msg;
622 queue = &(tmp_qp->rx_q);
623 resp_msg = (struct icp_qat_fw_comn_resp *)
624 ((uint8_t *)queue->base_addr + queue->head);
626 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
627 msg_counter != nb_ops) {
628 rx_op = (struct rte_crypto_op *)(uintptr_t)
629 (resp_msg->opaque_data);
631 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
632 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
633 sizeof(struct icp_qat_fw_comn_resp));
635 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
636 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
637 resp_msg->comn_hdr.comn_status)) {
638 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
640 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
642 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
643 queue->head = adf_modulo(queue->head +
645 ADF_RING_SIZE_MODULO(queue->queue_size));
646 resp_msg = (struct icp_qat_fw_comn_resp *)
647 ((uint8_t *)queue->base_addr +
653 if (msg_counter > 0) {
654 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
655 queue->hw_bundle_number,
656 queue->hw_queue_number, queue->head);
657 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
658 tmp_qp->stats.dequeued_count += msg_counter;
664 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
666 struct qat_session *ctx;
667 struct icp_qat_fw_la_cipher_req_params *cipher_param;
668 struct icp_qat_fw_la_auth_req_params *auth_param;
669 register struct icp_qat_fw_la_bulk_req *qat_req;
671 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
672 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
673 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
674 "operation requests, op (%p) is not a "
675 "symmetric operation.", op);
679 if (unlikely(op->sym->type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
680 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
681 " requests, op (%p) is sessionless.", op);
685 if (unlikely(op->sym->session->type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
686 PMD_DRV_LOG(ERR, "Session was not created for this device");
690 ctx = (struct qat_session *)op->sym->session->_private;
691 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
692 *qat_req = ctx->fw_req;
693 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
696 * The following code assumes:
697 * - single entry buffer.
700 qat_req->comn_mid.dst_length =
701 qat_req->comn_mid.src_length =
702 rte_pktmbuf_data_len(op->sym->m_src);
703 qat_req->comn_mid.dest_data_addr =
704 qat_req->comn_mid.src_data_addr =
705 rte_pktmbuf_mtophys(op->sym->m_src);
706 cipher_param = (void *)&qat_req->serv_specif_rqpars;
707 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
709 cipher_param->cipher_length = op->sym->cipher.data.length;
710 cipher_param->cipher_offset = op->sym->cipher.data.offset;
711 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
712 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
713 (cipher_param->cipher_offset
714 % BYTE_LENGTH != 0))) {
715 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
716 "supports byte aligned values");
717 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
720 cipher_param->cipher_length >>= 3;
721 cipher_param->cipher_offset >>= 3;
724 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
725 sizeof(cipher_param->u.cipher_IV_array))) {
726 rte_memcpy(cipher_param->u.cipher_IV_array,
727 op->sym->cipher.iv.data,
728 op->sym->cipher.iv.length);
730 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
731 qat_req->comn_hdr.serv_specif_flags,
732 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
733 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
735 if (op->sym->auth.digest.phys_addr) {
736 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
737 qat_req->comn_hdr.serv_specif_flags,
738 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
739 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
741 auth_param->auth_off = op->sym->auth.data.offset;
742 auth_param->auth_len = op->sym->auth.data.length;
743 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
744 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
745 (auth_param->auth_len % BYTE_LENGTH != 0))) {
746 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
747 "supports byte aligned values");
748 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
751 auth_param->auth_off >>= 3;
752 auth_param->auth_len >>= 3;
754 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
755 /* (GCM) aad length(240 max) will be at this location after precompute */
756 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
757 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
758 struct icp_qat_hw_auth_algo_blk *hash;
760 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER)
761 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd);
763 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd +
764 sizeof(struct icp_qat_hw_cipher_algo_blk));
766 auth_param->u2.aad_sz = ALIGN_POW2_ROUNDUP(hash->sha.state1[
767 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
768 ICP_QAT_HW_GALOIS_H_SZ + 3], 16);
769 if (op->sym->cipher.iv.length == 12) {
771 * For GCM a 12 bit IV is allowed,
772 * but we need to inform the f/w
774 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
775 qat_req->comn_hdr.serv_specif_flags,
776 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
779 auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
782 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
783 rte_hexdump(stdout, "qat_req:", qat_req,
784 sizeof(struct icp_qat_fw_la_bulk_req));
785 rte_hexdump(stdout, "src_data:",
786 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
787 rte_pktmbuf_data_len(op->sym->m_src));
788 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
789 op->sym->cipher.iv.length);
790 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
791 op->sym->auth.digest.length);
792 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
793 op->sym->auth.aad.length);
798 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
800 uint32_t div = data >> shift;
801 uint32_t mult = div << shift;
806 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *priv_sess)
808 struct qat_session *s = priv_sess;
810 PMD_INIT_FUNC_TRACE();
811 s->cd_paddr = rte_mempool_virt2phy(mp, &s->cd);
814 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
816 PMD_INIT_FUNC_TRACE();
820 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
822 PMD_INIT_FUNC_TRACE();
826 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
828 PMD_INIT_FUNC_TRACE();
831 int qat_dev_close(struct rte_cryptodev *dev)
835 PMD_INIT_FUNC_TRACE();
837 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
838 ret = qat_crypto_sym_qp_release(dev, i);
846 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
847 struct rte_cryptodev_info *info)
849 struct qat_pmd_private *internals = dev->data->dev_private;
851 PMD_INIT_FUNC_TRACE();
853 info->max_nb_queue_pairs =
854 ADF_NUM_SYM_QPS_PER_BUNDLE *
855 ADF_NUM_BUNDLES_PER_DEV;
856 info->feature_flags = dev->feature_flags;
857 info->capabilities = qat_pmd_capabilities;
858 info->sym.max_nb_sessions = internals->max_nb_sessions;
859 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
863 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
864 struct rte_cryptodev_stats *stats)
867 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
869 PMD_INIT_FUNC_TRACE();
871 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
874 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
876 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
880 stats->enqueued_count += qp[i]->stats.enqueued_count;
881 stats->dequeued_count += qp[i]->stats.enqueued_count;
882 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
883 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
887 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
890 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
892 PMD_INIT_FUNC_TRACE();
893 for (i = 0; i < dev->data->nb_queue_pairs; i++)
894 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
895 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");