4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_malloc.h>
50 #include <rte_launch.h>
52 #include <rte_per_lcore.h>
53 #include <rte_lcore.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_mempool.h>
57 #include <rte_string_fns.h>
58 #include <rte_spinlock.h>
59 #include <rte_hexdump.h>
60 #include <rte_crypto_sym.h>
61 #include <rte_cryptodev_pci.h>
62 #include <openssl/evp.h>
66 #include "qat_crypto.h"
67 #include "adf_transport_access_macros.h"
72 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
73 struct qat_pmd_private *internals) {
75 const struct rte_cryptodev_capabilities *capability;
77 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
78 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
79 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
82 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
85 if (capability->sym.cipher.algo == algo)
92 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
93 struct qat_pmd_private *internals) {
95 const struct rte_cryptodev_capabilities *capability;
97 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
98 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
99 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
102 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
105 if (capability->sym.auth.algo == algo)
111 /** Encrypt a single partial block
112 * Depends on openssl libcrypto
113 * Uses ECB+XOR to do CFB encryption, same result, more performant
116 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
117 uint8_t *iv, int ivlen, int srclen,
120 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
122 uint8_t encrypted_iv[16];
125 /* ECB method: encrypt the IV, then XOR this with plaintext */
126 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
128 goto cipher_encrypt_err;
130 for (i = 0; i < srclen; i++)
131 *(dst+i) = *(src+i)^(encrypted_iv[i]);
136 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
140 /** Decrypt a single partial block
141 * Depends on openssl libcrypto
142 * Uses ECB+XOR to do CFB encryption, same result, more performant
145 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
146 uint8_t *iv, int ivlen, int srclen,
149 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
151 uint8_t encrypted_iv[16];
154 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
155 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
157 goto cipher_decrypt_err;
159 for (i = 0; i < srclen; i++)
160 *(dst+i) = *(src+i)^(encrypted_iv[i]);
165 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
169 /** Creates a context in either AES or DES in ECB mode
170 * Depends on openssl libcrypto
173 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
174 enum rte_crypto_cipher_operation direction __rte_unused,
175 uint8_t *key, void **ctx)
177 const EVP_CIPHER *algo = NULL;
179 *ctx = EVP_CIPHER_CTX_new();
186 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
187 algo = EVP_des_ecb();
189 algo = EVP_aes_128_ecb();
191 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
192 if (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {
201 EVP_CIPHER_CTX_free(*ctx);
205 /** Frees a context previously created
206 * Depends on openssl libcrypto
209 bpi_cipher_ctx_free(void *bpi_ctx)
212 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
215 static inline uint32_t
216 adf_modulo(uint32_t data, uint32_t shift);
219 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
220 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
223 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
224 struct rte_cryptodev_sym_session *sess)
226 PMD_INIT_FUNC_TRACE();
227 uint8_t index = dev->driver_id;
228 void *sess_priv = get_session_private_data(sess, index);
229 struct qat_session *s = (struct qat_session *)sess_priv;
233 bpi_cipher_ctx_free(s->bpi_ctx);
234 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
235 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
236 set_session_private_data(sess, index, NULL);
237 rte_mempool_put(sess_mp, sess_priv);
242 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
245 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
246 return ICP_QAT_FW_LA_CMD_CIPHER;
248 /* Authentication Only */
249 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
250 return ICP_QAT_FW_LA_CMD_AUTH;
253 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
254 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
255 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
257 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
260 if (xform->next == NULL)
263 /* Cipher then Authenticate */
264 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
265 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
266 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
268 /* Authenticate then Cipher */
269 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
270 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
271 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
276 static struct rte_crypto_auth_xform *
277 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
280 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
289 static struct rte_crypto_cipher_xform *
290 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
293 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
294 return &xform->cipher;
303 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
304 struct rte_crypto_sym_xform *xform,
305 struct qat_session *session)
307 struct qat_pmd_private *internals = dev->data->dev_private;
308 struct rte_crypto_cipher_xform *cipher_xform = NULL;
311 /* Get cipher xform from crypto xform chain */
312 cipher_xform = qat_get_cipher_xform(xform);
314 session->cipher_iv.offset = cipher_xform->iv.offset;
315 session->cipher_iv.length = cipher_xform->iv.length;
317 switch (cipher_xform->algo) {
318 case RTE_CRYPTO_CIPHER_AES_CBC:
319 if (qat_alg_validate_aes_key(cipher_xform->key.length,
320 &session->qat_cipher_alg) != 0) {
321 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
325 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
327 case RTE_CRYPTO_CIPHER_AES_CTR:
328 if (qat_alg_validate_aes_key(cipher_xform->key.length,
329 &session->qat_cipher_alg) != 0) {
330 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
334 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
336 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
337 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
338 &session->qat_cipher_alg) != 0) {
339 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
343 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
345 case RTE_CRYPTO_CIPHER_NULL:
346 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
348 case RTE_CRYPTO_CIPHER_KASUMI_F8:
349 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
350 &session->qat_cipher_alg) != 0) {
351 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
355 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
357 case RTE_CRYPTO_CIPHER_3DES_CBC:
358 if (qat_alg_validate_3des_key(cipher_xform->key.length,
359 &session->qat_cipher_alg) != 0) {
360 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
364 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
366 case RTE_CRYPTO_CIPHER_DES_CBC:
367 if (qat_alg_validate_des_key(cipher_xform->key.length,
368 &session->qat_cipher_alg) != 0) {
369 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
373 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
375 case RTE_CRYPTO_CIPHER_3DES_CTR:
376 if (qat_alg_validate_3des_key(cipher_xform->key.length,
377 &session->qat_cipher_alg) != 0) {
378 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
382 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
384 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
385 ret = bpi_cipher_ctx_init(
388 cipher_xform->key.data,
391 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
394 if (qat_alg_validate_des_key(cipher_xform->key.length,
395 &session->qat_cipher_alg) != 0) {
396 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
400 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
402 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
403 ret = bpi_cipher_ctx_init(
406 cipher_xform->key.data,
409 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
412 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
413 &session->qat_cipher_alg) != 0) {
414 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
418 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
420 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
421 if (!qat_is_cipher_alg_supported(
422 cipher_xform->algo, internals)) {
423 PMD_DRV_LOG(ERR, "%s not supported on this device",
424 rte_crypto_cipher_algorithm_strings
425 [cipher_xform->algo]);
429 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
430 &session->qat_cipher_alg) != 0) {
431 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
435 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
437 case RTE_CRYPTO_CIPHER_3DES_ECB:
438 case RTE_CRYPTO_CIPHER_AES_ECB:
439 case RTE_CRYPTO_CIPHER_AES_F8:
440 case RTE_CRYPTO_CIPHER_AES_XTS:
441 case RTE_CRYPTO_CIPHER_ARC4:
442 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
447 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
453 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
454 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
456 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
458 if (qat_alg_aead_session_create_content_desc_cipher(session,
459 cipher_xform->key.data,
460 cipher_xform->key.length)) {
468 if (session->bpi_ctx) {
469 bpi_cipher_ctx_free(session->bpi_ctx);
470 session->bpi_ctx = NULL;
476 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
477 struct rte_crypto_sym_xform *xform,
478 struct rte_cryptodev_sym_session *sess,
479 struct rte_mempool *mempool)
481 void *sess_private_data;
484 if (rte_mempool_get(mempool, &sess_private_data)) {
486 "Couldn't get object from session mempool");
490 ret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);
492 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
493 "session parameters");
495 /* Return session to mempool */
496 rte_mempool_put(mempool, sess_private_data);
500 set_session_private_data(sess, dev->driver_id,
507 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
508 struct rte_crypto_sym_xform *xform, void *session_private)
510 struct qat_session *session = session_private;
514 PMD_INIT_FUNC_TRACE();
516 /* Set context descriptor physical address */
517 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
518 offsetof(struct qat_session, cd);
520 session->min_qat_dev_gen = QAT_GEN1;
522 /* Get requested QAT command id */
523 qat_cmd_id = qat_get_cmd_id(xform);
524 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
525 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
528 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
529 switch (session->qat_cmd) {
530 case ICP_QAT_FW_LA_CMD_CIPHER:
531 ret = qat_crypto_sym_configure_session_cipher(dev, xform, session);
535 case ICP_QAT_FW_LA_CMD_AUTH:
536 ret = qat_crypto_sym_configure_session_auth(dev, xform, session);
540 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
541 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
542 ret = qat_crypto_sym_configure_session_aead(xform,
547 ret = qat_crypto_sym_configure_session_cipher(dev,
551 ret = qat_crypto_sym_configure_session_auth(dev,
557 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
558 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
559 ret = qat_crypto_sym_configure_session_aead(xform,
564 ret = qat_crypto_sym_configure_session_auth(dev,
568 ret = qat_crypto_sym_configure_session_cipher(dev,
574 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
575 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
576 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
577 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
578 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
579 case ICP_QAT_FW_LA_CMD_MGF1:
580 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
581 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
582 case ICP_QAT_FW_LA_CMD_DELIMITER:
583 PMD_DRV_LOG(ERR, "Unsupported Service %u",
587 PMD_DRV_LOG(ERR, "Unsupported Service %u",
596 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
597 struct rte_crypto_sym_xform *xform,
598 struct qat_session *session)
600 struct rte_crypto_auth_xform *auth_xform = NULL;
601 struct qat_pmd_private *internals = dev->data->dev_private;
602 auth_xform = qat_get_auth_xform(xform);
603 uint8_t *key_data = auth_xform->key.data;
604 uint8_t key_length = auth_xform->key.length;
606 switch (auth_xform->algo) {
607 case RTE_CRYPTO_AUTH_SHA1_HMAC:
608 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
610 case RTE_CRYPTO_AUTH_SHA224_HMAC:
611 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
613 case RTE_CRYPTO_AUTH_SHA256_HMAC:
614 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
616 case RTE_CRYPTO_AUTH_SHA384_HMAC:
617 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
619 case RTE_CRYPTO_AUTH_SHA512_HMAC:
620 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
622 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
623 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
625 case RTE_CRYPTO_AUTH_AES_GMAC:
626 if (qat_alg_validate_aes_key(auth_xform->key.length,
627 &session->qat_cipher_alg) != 0) {
628 PMD_DRV_LOG(ERR, "Invalid AES key size");
631 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
632 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
635 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
636 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
638 case RTE_CRYPTO_AUTH_MD5_HMAC:
639 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
641 case RTE_CRYPTO_AUTH_NULL:
642 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
644 case RTE_CRYPTO_AUTH_KASUMI_F9:
645 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
647 case RTE_CRYPTO_AUTH_ZUC_EIA3:
648 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
649 PMD_DRV_LOG(ERR, "%s not supported on this device",
650 rte_crypto_auth_algorithm_strings
654 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
656 case RTE_CRYPTO_AUTH_SHA1:
657 case RTE_CRYPTO_AUTH_SHA256:
658 case RTE_CRYPTO_AUTH_SHA512:
659 case RTE_CRYPTO_AUTH_SHA224:
660 case RTE_CRYPTO_AUTH_SHA384:
661 case RTE_CRYPTO_AUTH_MD5:
662 case RTE_CRYPTO_AUTH_AES_CMAC:
663 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
664 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
668 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
673 session->auth_iv.offset = auth_xform->iv.offset;
674 session->auth_iv.length = auth_xform->iv.length;
676 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
677 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
678 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
679 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
681 * It needs to create cipher desc content first,
682 * then authentication
684 if (qat_alg_aead_session_create_content_desc_cipher(session,
685 auth_xform->key.data,
686 auth_xform->key.length))
689 if (qat_alg_aead_session_create_content_desc_auth(session,
693 auth_xform->digest_length,
697 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
698 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
700 * It needs to create authentication desc content first,
703 if (qat_alg_aead_session_create_content_desc_auth(session,
707 auth_xform->digest_length,
711 if (qat_alg_aead_session_create_content_desc_cipher(session,
712 auth_xform->key.data,
713 auth_xform->key.length))
716 /* Restore to authentication only only */
717 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
719 if (qat_alg_aead_session_create_content_desc_auth(session,
723 auth_xform->digest_length,
728 session->digest_length = auth_xform->digest_length;
733 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
734 struct qat_session *session)
736 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
739 * Store AEAD IV parameters as cipher IV,
740 * to avoid unnecessary memory usage
742 session->cipher_iv.offset = xform->aead.iv.offset;
743 session->cipher_iv.length = xform->aead.iv.length;
745 switch (aead_xform->algo) {
746 case RTE_CRYPTO_AEAD_AES_GCM:
747 if (qat_alg_validate_aes_key(aead_xform->key.length,
748 &session->qat_cipher_alg) != 0) {
749 PMD_DRV_LOG(ERR, "Invalid AES key size");
752 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
753 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
755 case RTE_CRYPTO_AEAD_AES_CCM:
756 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
760 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
765 if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
766 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
768 * It needs to create cipher desc content first,
769 * then authentication
771 if (qat_alg_aead_session_create_content_desc_cipher(session,
772 aead_xform->key.data,
773 aead_xform->key.length))
776 if (qat_alg_aead_session_create_content_desc_auth(session,
777 aead_xform->key.data,
778 aead_xform->key.length,
779 aead_xform->aad_length,
780 aead_xform->digest_length,
781 RTE_CRYPTO_AUTH_OP_GENERATE))
784 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
786 * It needs to create authentication desc content first,
789 if (qat_alg_aead_session_create_content_desc_auth(session,
790 aead_xform->key.data,
791 aead_xform->key.length,
792 aead_xform->aad_length,
793 aead_xform->digest_length,
794 RTE_CRYPTO_AUTH_OP_VERIFY))
797 if (qat_alg_aead_session_create_content_desc_cipher(session,
798 aead_xform->key.data,
799 aead_xform->key.length))
803 session->digest_length = aead_xform->digest_length;
807 unsigned qat_crypto_sym_get_session_private_size(
808 struct rte_cryptodev *dev __rte_unused)
810 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
813 static inline uint32_t
814 qat_bpicipher_preprocess(struct qat_session *ctx,
815 struct rte_crypto_op *op)
817 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
818 struct rte_crypto_sym_op *sym_op = op->sym;
819 uint8_t last_block_len = block_len > 0 ?
820 sym_op->cipher.data.length % block_len : 0;
822 if (last_block_len &&
823 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
825 /* Decrypt last block */
826 uint8_t *last_block, *dst, *iv;
827 uint32_t last_block_offset = sym_op->cipher.data.offset +
828 sym_op->cipher.data.length - last_block_len;
829 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
830 uint8_t *, last_block_offset);
832 if (unlikely(sym_op->m_dst != NULL))
833 /* out-of-place operation (OOP) */
834 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
835 uint8_t *, last_block_offset);
839 if (last_block_len < sym_op->cipher.data.length)
840 /* use previous block ciphertext as IV */
841 iv = last_block - block_len;
843 /* runt block, i.e. less than one full block */
844 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
845 ctx->cipher_iv.offset);
847 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
848 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
850 if (sym_op->m_dst != NULL)
851 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
854 bpi_cipher_decrypt(last_block, dst, iv, block_len,
855 last_block_len, ctx->bpi_ctx);
856 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
857 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
859 if (sym_op->m_dst != NULL)
860 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
865 return sym_op->cipher.data.length - last_block_len;
868 static inline uint32_t
869 qat_bpicipher_postprocess(struct qat_session *ctx,
870 struct rte_crypto_op *op)
872 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
873 struct rte_crypto_sym_op *sym_op = op->sym;
874 uint8_t last_block_len = block_len > 0 ?
875 sym_op->cipher.data.length % block_len : 0;
877 if (last_block_len > 0 &&
878 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
880 /* Encrypt last block */
881 uint8_t *last_block, *dst, *iv;
882 uint32_t last_block_offset;
884 last_block_offset = sym_op->cipher.data.offset +
885 sym_op->cipher.data.length - last_block_len;
886 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
887 uint8_t *, last_block_offset);
889 if (unlikely(sym_op->m_dst != NULL))
890 /* out-of-place operation (OOP) */
891 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
892 uint8_t *, last_block_offset);
896 if (last_block_len < sym_op->cipher.data.length)
897 /* use previous block ciphertext as IV */
898 iv = dst - block_len;
900 /* runt block, i.e. less than one full block */
901 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
902 ctx->cipher_iv.offset);
904 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
905 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
907 if (sym_op->m_dst != NULL)
908 rte_hexdump(stdout, "BPI: dst before post-process:",
909 dst, last_block_len);
911 bpi_cipher_encrypt(last_block, dst, iv, block_len,
912 last_block_len, ctx->bpi_ctx);
913 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
914 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
916 if (sym_op->m_dst != NULL)
917 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
921 return sym_op->cipher.data.length - last_block_len;
925 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
926 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
927 q->hw_queue_number, q->tail);
928 q->nb_pending_requests = 0;
929 q->csr_tail = q->tail;
933 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
936 register struct qat_queue *queue;
937 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
938 register uint32_t nb_ops_sent = 0;
939 register struct rte_crypto_op **cur_op = ops;
941 uint16_t nb_ops_possible = nb_ops;
942 register uint8_t *base_addr;
943 register uint32_t tail;
946 if (unlikely(nb_ops == 0))
949 /* read params used a lot in main loop into registers */
950 queue = &(tmp_qp->tx_q);
951 base_addr = (uint8_t *)queue->base_addr;
954 /* Find how many can actually fit on the ring */
955 tmp_qp->inflights16 += nb_ops;
956 overflow = tmp_qp->inflights16 - queue->max_inflights;
958 tmp_qp->inflights16 -= overflow;
959 nb_ops_possible = nb_ops - overflow;
960 if (nb_ops_possible == 0)
964 while (nb_ops_sent != nb_ops_possible) {
965 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
966 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
968 tmp_qp->stats.enqueue_err_count++;
970 * This message cannot be enqueued,
971 * decrease number of ops that wasn't sent
973 tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
974 if (nb_ops_sent == 0)
979 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
985 tmp_qp->stats.enqueued_count += nb_ops_sent;
986 queue->nb_pending_requests += nb_ops_sent;
987 if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
988 queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
989 txq_write_tail(tmp_qp, queue);
995 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
997 uint32_t old_head, new_head;
1000 old_head = q->csr_head;
1002 max_head = qp->nb_descriptors * q->msg_size;
1004 /* write out free descriptors */
1005 void *cur_desc = (uint8_t *)q->base_addr + old_head;
1007 if (new_head < old_head) {
1008 memset(cur_desc, ADF_RING_EMPTY_SIG, max_head - old_head);
1009 memset(q->base_addr, ADF_RING_EMPTY_SIG, new_head);
1011 memset(cur_desc, ADF_RING_EMPTY_SIG, new_head - old_head);
1013 q->nb_processed_responses = 0;
1014 q->csr_head = new_head;
1016 /* write current head to CSR */
1017 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
1018 q->hw_queue_number, new_head);
1022 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
1025 struct qat_queue *rx_queue, *tx_queue;
1026 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
1027 uint32_t msg_counter = 0;
1028 struct rte_crypto_op *rx_op;
1029 struct icp_qat_fw_comn_resp *resp_msg;
1032 rx_queue = &(tmp_qp->rx_q);
1033 tx_queue = &(tmp_qp->tx_q);
1034 head = rx_queue->head;
1035 resp_msg = (struct icp_qat_fw_comn_resp *)
1036 ((uint8_t *)rx_queue->base_addr + head);
1038 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
1039 msg_counter != nb_ops) {
1040 rx_op = (struct rte_crypto_op *)(uintptr_t)
1041 (resp_msg->opaque_data);
1043 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1044 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
1045 sizeof(struct icp_qat_fw_comn_resp));
1048 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
1049 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
1050 resp_msg->comn_hdr.comn_status)) {
1051 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1053 struct qat_session *sess = (struct qat_session *)
1054 get_session_private_data(
1055 rx_op->sym->session,
1056 cryptodev_qat_driver_id);
1059 qat_bpicipher_postprocess(sess, rx_op);
1060 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1063 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
1064 resp_msg = (struct icp_qat_fw_comn_resp *)
1065 ((uint8_t *)rx_queue->base_addr + head);
1070 if (msg_counter > 0) {
1071 rx_queue->head = head;
1072 tmp_qp->stats.dequeued_count += msg_counter;
1073 rx_queue->nb_processed_responses += msg_counter;
1074 tmp_qp->inflights16 -= msg_counter;
1076 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
1077 rxq_free_desc(tmp_qp, rx_queue);
1079 /* also check if tail needs to be advanced */
1080 if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
1081 tx_queue->tail != tx_queue->csr_tail) {
1082 txq_write_tail(tmp_qp, tx_queue);
1088 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1089 struct qat_alg_buf_list *list, uint32_t data_len)
1093 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1094 buff_start + rte_pktmbuf_data_len(buf);
1096 list->bufers[0].addr = buff_start;
1097 list->bufers[0].resrvd = 0;
1098 list->bufers[0].len = buf_len;
1100 if (data_len <= buf_len) {
1101 list->num_bufs = nr;
1102 list->bufers[0].len = data_len;
1108 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1109 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1111 QAT_SGL_MAX_NUMBER);
1115 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1116 list->bufers[nr].resrvd = 0;
1117 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1119 buf_len += list->bufers[nr].len;
1122 if (buf_len > data_len) {
1123 list->bufers[nr].len -=
1129 list->num_bufs = nr;
1135 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1136 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1137 struct rte_crypto_op *op,
1138 struct icp_qat_fw_la_bulk_req *qat_req)
1140 /* copy IV into request if it fits */
1141 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1142 rte_memcpy(cipher_param->u.cipher_IV_array,
1143 rte_crypto_op_ctod_offset(op, uint8_t *,
1147 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1148 qat_req->comn_hdr.serv_specif_flags,
1149 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1150 cipher_param->u.s.cipher_IV_ptr =
1151 rte_crypto_op_ctophys_offset(op,
1157 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1158 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1161 struct qat_session *ctx;
1162 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1163 struct icp_qat_fw_la_auth_req_params *auth_param;
1164 register struct icp_qat_fw_la_bulk_req *qat_req;
1165 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1166 uint32_t cipher_len = 0, cipher_ofs = 0;
1167 uint32_t auth_len = 0, auth_ofs = 0;
1168 uint32_t min_ofs = 0;
1169 uint64_t src_buf_start = 0, dst_buf_start = 0;
1172 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1173 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1174 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1175 "operation requests, op (%p) is not a "
1176 "symmetric operation.", op);
1180 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1181 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1182 " requests, op (%p) is sessionless.", op);
1186 ctx = (struct qat_session *)get_session_private_data(
1187 op->sym->session, cryptodev_qat_driver_id);
1189 if (unlikely(ctx == NULL)) {
1190 PMD_DRV_LOG(ERR, "Session was not created for this device");
1194 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1195 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1196 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1200 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1201 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1202 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1203 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1204 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1206 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1207 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1209 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1210 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1216 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1219 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1226 if (ctx->qat_cipher_alg ==
1227 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1228 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1229 ctx->qat_cipher_alg ==
1230 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1233 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1234 || (cipher_param->cipher_offset
1235 % BYTE_LENGTH != 0))) {
1237 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1238 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1241 cipher_len = op->sym->cipher.data.length >> 3;
1242 cipher_ofs = op->sym->cipher.data.offset >> 3;
1244 } else if (ctx->bpi_ctx) {
1245 /* DOCSIS - only send complete blocks to device
1246 * Process any partial block using CFB mode.
1247 * Even if 0 complete blocks, still send this to device
1248 * to get into rx queue for post-process and dequeuing
1250 cipher_len = qat_bpicipher_preprocess(ctx, op);
1251 cipher_ofs = op->sym->cipher.data.offset;
1253 cipher_len = op->sym->cipher.data.length;
1254 cipher_ofs = op->sym->cipher.data.offset;
1257 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1258 cipher_param, op, qat_req);
1259 min_ofs = cipher_ofs;
1264 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1265 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1266 ctx->qat_hash_alg ==
1267 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1268 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1269 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1271 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1272 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1275 auth_ofs = op->sym->auth.data.offset >> 3;
1276 auth_len = op->sym->auth.data.length >> 3;
1278 auth_param->u1.aad_adr =
1279 rte_crypto_op_ctophys_offset(op,
1280 ctx->auth_iv.offset);
1282 } else if (ctx->qat_hash_alg ==
1283 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1284 ctx->qat_hash_alg ==
1285 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1287 set_cipher_iv(ctx->auth_iv.length,
1288 ctx->auth_iv.offset,
1289 cipher_param, op, qat_req);
1290 auth_ofs = op->sym->auth.data.offset;
1291 auth_len = op->sym->auth.data.length;
1293 auth_param->u1.aad_adr = 0;
1294 auth_param->u2.aad_sz = 0;
1297 * If len(iv)==12B fw computes J0
1299 if (ctx->auth_iv.length == 12) {
1300 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1301 qat_req->comn_hdr.serv_specif_flags,
1302 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1306 auth_ofs = op->sym->auth.data.offset;
1307 auth_len = op->sym->auth.data.length;
1312 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1317 if (ctx->qat_hash_alg ==
1318 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1319 ctx->qat_hash_alg ==
1320 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1322 * If len(iv)==12B fw computes J0
1324 if (ctx->cipher_iv.length == 12) {
1325 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1326 qat_req->comn_hdr.serv_specif_flags,
1327 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1332 cipher_len = op->sym->aead.data.length;
1333 cipher_ofs = op->sym->aead.data.offset;
1334 auth_len = op->sym->aead.data.length;
1335 auth_ofs = op->sym->aead.data.offset;
1337 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1338 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1339 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1340 cipher_param, op, qat_req);
1341 min_ofs = op->sym->aead.data.offset;
1344 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1347 /* adjust for chain case */
1348 if (do_cipher && do_auth)
1349 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1351 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1354 if (unlikely(op->sym->m_dst != NULL)) {
1355 /* Out-of-place operation (OOP)
1356 * Don't align DMA start. DMA the minimum data-set
1357 * so as not to overwrite data in dest buffer
1360 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1362 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1365 /* In-place operation
1366 * Start DMA at nearest aligned address below min_ofs
1369 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1370 & QAT_64_BTYE_ALIGN_MASK;
1372 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1373 rte_pktmbuf_headroom(op->sym->m_src))
1375 /* alignment has pushed addr ahead of start of mbuf
1376 * so revert and take the performance hit
1379 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1382 dst_buf_start = src_buf_start;
1385 if (do_cipher || do_aead) {
1386 cipher_param->cipher_offset =
1387 (uint32_t)rte_pktmbuf_mtophys_offset(
1388 op->sym->m_src, cipher_ofs) - src_buf_start;
1389 cipher_param->cipher_length = cipher_len;
1391 cipher_param->cipher_offset = 0;
1392 cipher_param->cipher_length = 0;
1395 if (do_auth || do_aead) {
1396 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1397 op->sym->m_src, auth_ofs) - src_buf_start;
1398 auth_param->auth_len = auth_len;
1400 auth_param->auth_off = 0;
1401 auth_param->auth_len = 0;
1404 qat_req->comn_mid.dst_length =
1405 qat_req->comn_mid.src_length =
1406 (cipher_param->cipher_offset + cipher_param->cipher_length)
1407 > (auth_param->auth_off + auth_param->auth_len) ?
1408 (cipher_param->cipher_offset + cipher_param->cipher_length)
1409 : (auth_param->auth_off + auth_param->auth_len);
1413 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1414 QAT_COMN_PTR_TYPE_SGL);
1415 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1416 &qat_op_cookie->qat_sgl_list_src,
1417 qat_req->comn_mid.src_length);
1419 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1423 if (likely(op->sym->m_dst == NULL))
1424 qat_req->comn_mid.dest_data_addr =
1425 qat_req->comn_mid.src_data_addr =
1426 qat_op_cookie->qat_sgl_src_phys_addr;
1428 ret = qat_sgl_fill_array(op->sym->m_dst,
1430 &qat_op_cookie->qat_sgl_list_dst,
1431 qat_req->comn_mid.dst_length);
1434 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1439 qat_req->comn_mid.src_data_addr =
1440 qat_op_cookie->qat_sgl_src_phys_addr;
1441 qat_req->comn_mid.dest_data_addr =
1442 qat_op_cookie->qat_sgl_dst_phys_addr;
1445 qat_req->comn_mid.src_data_addr = src_buf_start;
1446 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1449 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1450 rte_hexdump(stdout, "qat_req:", qat_req,
1451 sizeof(struct icp_qat_fw_la_bulk_req));
1452 rte_hexdump(stdout, "src_data:",
1453 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1454 rte_pktmbuf_data_len(op->sym->m_src));
1456 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1458 ctx->cipher_iv.offset);
1459 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1460 ctx->cipher_iv.length);
1464 if (ctx->auth_iv.length) {
1465 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1467 ctx->auth_iv.offset);
1468 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1469 ctx->auth_iv.length);
1471 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1472 ctx->digest_length);
1476 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1477 ctx->digest_length);
1478 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1485 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1487 uint32_t div = data >> shift;
1488 uint32_t mult = div << shift;
1493 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1494 __rte_unused struct rte_cryptodev_config *config)
1496 PMD_INIT_FUNC_TRACE();
1500 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1502 PMD_INIT_FUNC_TRACE();
1506 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1508 PMD_INIT_FUNC_TRACE();
1511 int qat_dev_close(struct rte_cryptodev *dev)
1515 PMD_INIT_FUNC_TRACE();
1517 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1518 ret = qat_crypto_sym_qp_release(dev, i);
1526 void qat_dev_info_get(struct rte_cryptodev *dev,
1527 struct rte_cryptodev_info *info)
1529 struct qat_pmd_private *internals = dev->data->dev_private;
1531 PMD_INIT_FUNC_TRACE();
1533 info->max_nb_queue_pairs =
1534 ADF_NUM_SYM_QPS_PER_BUNDLE *
1535 ADF_NUM_BUNDLES_PER_DEV;
1536 info->feature_flags = dev->feature_flags;
1537 info->capabilities = internals->qat_dev_capabilities;
1538 info->sym.max_nb_sessions = internals->max_nb_sessions;
1539 info->driver_id = cryptodev_qat_driver_id;
1540 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1544 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1545 struct rte_cryptodev_stats *stats)
1548 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1550 PMD_INIT_FUNC_TRACE();
1551 if (stats == NULL) {
1552 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1555 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1556 if (qp[i] == NULL) {
1557 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1561 stats->enqueued_count += qp[i]->stats.enqueued_count;
1562 stats->dequeued_count += qp[i]->stats.dequeued_count;
1563 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1564 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1568 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1571 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1573 PMD_INIT_FUNC_TRACE();
1574 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1575 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1576 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");