4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_malloc.h>
50 #include <rte_launch.h>
52 #include <rte_per_lcore.h>
53 #include <rte_lcore.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_mempool.h>
57 #include <rte_string_fns.h>
58 #include <rte_spinlock.h>
59 #include <rte_hexdump.h>
60 #include <rte_crypto_sym.h>
61 #include <rte_cryptodev_pci.h>
62 #include <rte_byteorder.h>
63 #include <openssl/evp.h>
67 #include "qat_crypto.h"
68 #include "adf_transport_access_macros.h"
73 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
74 struct qat_pmd_private *internals) {
76 const struct rte_cryptodev_capabilities *capability;
78 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
79 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
80 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
83 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
86 if (capability->sym.cipher.algo == algo)
93 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
94 struct qat_pmd_private *internals) {
96 const struct rte_cryptodev_capabilities *capability;
98 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
99 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
100 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
103 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
106 if (capability->sym.auth.algo == algo)
112 /** Encrypt a single partial block
113 * Depends on openssl libcrypto
114 * Uses ECB+XOR to do CFB encryption, same result, more performant
117 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
118 uint8_t *iv, int ivlen, int srclen,
121 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
123 uint8_t encrypted_iv[16];
126 /* ECB method: encrypt the IV, then XOR this with plaintext */
127 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
129 goto cipher_encrypt_err;
131 for (i = 0; i < srclen; i++)
132 *(dst+i) = *(src+i)^(encrypted_iv[i]);
137 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
141 /** Decrypt a single partial block
142 * Depends on openssl libcrypto
143 * Uses ECB+XOR to do CFB encryption, same result, more performant
146 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
147 uint8_t *iv, int ivlen, int srclen,
150 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
152 uint8_t encrypted_iv[16];
155 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
156 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
158 goto cipher_decrypt_err;
160 for (i = 0; i < srclen; i++)
161 *(dst+i) = *(src+i)^(encrypted_iv[i]);
166 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
170 /** Creates a context in either AES or DES in ECB mode
171 * Depends on openssl libcrypto
174 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
175 enum rte_crypto_cipher_operation direction __rte_unused,
176 uint8_t *key, void **ctx)
178 const EVP_CIPHER *algo = NULL;
180 *ctx = EVP_CIPHER_CTX_new();
187 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
188 algo = EVP_des_ecb();
190 algo = EVP_aes_128_ecb();
192 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
193 if (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {
202 EVP_CIPHER_CTX_free(*ctx);
206 /** Frees a context previously created
207 * Depends on openssl libcrypto
210 bpi_cipher_ctx_free(void *bpi_ctx)
213 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
216 static inline uint32_t
217 adf_modulo(uint32_t data, uint32_t shift);
220 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
221 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
224 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
225 struct rte_cryptodev_sym_session *sess)
227 PMD_INIT_FUNC_TRACE();
228 uint8_t index = dev->driver_id;
229 void *sess_priv = get_session_private_data(sess, index);
230 struct qat_session *s = (struct qat_session *)sess_priv;
234 bpi_cipher_ctx_free(s->bpi_ctx);
235 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
236 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
237 set_session_private_data(sess, index, NULL);
238 rte_mempool_put(sess_mp, sess_priv);
243 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
247 return ICP_QAT_FW_LA_CMD_CIPHER;
249 /* Authentication Only */
250 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
251 return ICP_QAT_FW_LA_CMD_AUTH;
254 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
255 /* AES-GCM and AES-CCM works with different direction
256 * GCM first encrypts and generate hash where AES-CCM
257 * first generate hash and encrypts. Similar relation
258 * applies to decryption.
260 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
261 if (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)
262 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
264 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
266 if (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)
267 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
269 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
272 if (xform->next == NULL)
275 /* Cipher then Authenticate */
276 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
277 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
278 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
280 /* Authenticate then Cipher */
281 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
282 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
283 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
288 static struct rte_crypto_auth_xform *
289 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
292 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
301 static struct rte_crypto_cipher_xform *
302 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
305 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
306 return &xform->cipher;
315 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
316 struct rte_crypto_sym_xform *xform,
317 struct qat_session *session)
319 struct qat_pmd_private *internals = dev->data->dev_private;
320 struct rte_crypto_cipher_xform *cipher_xform = NULL;
323 /* Get cipher xform from crypto xform chain */
324 cipher_xform = qat_get_cipher_xform(xform);
326 session->cipher_iv.offset = cipher_xform->iv.offset;
327 session->cipher_iv.length = cipher_xform->iv.length;
329 switch (cipher_xform->algo) {
330 case RTE_CRYPTO_CIPHER_AES_CBC:
331 if (qat_alg_validate_aes_key(cipher_xform->key.length,
332 &session->qat_cipher_alg) != 0) {
333 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
337 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
339 case RTE_CRYPTO_CIPHER_AES_CTR:
340 if (qat_alg_validate_aes_key(cipher_xform->key.length,
341 &session->qat_cipher_alg) != 0) {
342 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
346 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
348 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
349 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
350 &session->qat_cipher_alg) != 0) {
351 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
355 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
357 case RTE_CRYPTO_CIPHER_NULL:
358 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
360 case RTE_CRYPTO_CIPHER_KASUMI_F8:
361 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
362 &session->qat_cipher_alg) != 0) {
363 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
367 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
369 case RTE_CRYPTO_CIPHER_3DES_CBC:
370 if (qat_alg_validate_3des_key(cipher_xform->key.length,
371 &session->qat_cipher_alg) != 0) {
372 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
376 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
378 case RTE_CRYPTO_CIPHER_DES_CBC:
379 if (qat_alg_validate_des_key(cipher_xform->key.length,
380 &session->qat_cipher_alg) != 0) {
381 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
385 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
387 case RTE_CRYPTO_CIPHER_3DES_CTR:
388 if (qat_alg_validate_3des_key(cipher_xform->key.length,
389 &session->qat_cipher_alg) != 0) {
390 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
394 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
396 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
397 ret = bpi_cipher_ctx_init(
400 cipher_xform->key.data,
403 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
406 if (qat_alg_validate_des_key(cipher_xform->key.length,
407 &session->qat_cipher_alg) != 0) {
408 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
412 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
414 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
415 ret = bpi_cipher_ctx_init(
418 cipher_xform->key.data,
421 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
424 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
425 &session->qat_cipher_alg) != 0) {
426 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
430 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
432 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
433 if (!qat_is_cipher_alg_supported(
434 cipher_xform->algo, internals)) {
435 PMD_DRV_LOG(ERR, "%s not supported on this device",
436 rte_crypto_cipher_algorithm_strings
437 [cipher_xform->algo]);
441 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
442 &session->qat_cipher_alg) != 0) {
443 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
447 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
449 case RTE_CRYPTO_CIPHER_3DES_ECB:
450 case RTE_CRYPTO_CIPHER_AES_ECB:
451 case RTE_CRYPTO_CIPHER_AES_F8:
452 case RTE_CRYPTO_CIPHER_AES_XTS:
453 case RTE_CRYPTO_CIPHER_ARC4:
454 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
459 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
465 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
466 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
468 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
470 if (qat_alg_aead_session_create_content_desc_cipher(session,
471 cipher_xform->key.data,
472 cipher_xform->key.length)) {
480 if (session->bpi_ctx) {
481 bpi_cipher_ctx_free(session->bpi_ctx);
482 session->bpi_ctx = NULL;
488 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
489 struct rte_crypto_sym_xform *xform,
490 struct rte_cryptodev_sym_session *sess,
491 struct rte_mempool *mempool)
493 void *sess_private_data;
496 if (rte_mempool_get(mempool, &sess_private_data)) {
498 "Couldn't get object from session mempool");
502 ret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);
504 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
505 "session parameters");
507 /* Return session to mempool */
508 rte_mempool_put(mempool, sess_private_data);
512 set_session_private_data(sess, dev->driver_id,
519 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
520 struct rte_crypto_sym_xform *xform, void *session_private)
522 struct qat_session *session = session_private;
526 PMD_INIT_FUNC_TRACE();
528 /* Set context descriptor physical address */
529 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
530 offsetof(struct qat_session, cd);
532 session->min_qat_dev_gen = QAT_GEN1;
534 /* Get requested QAT command id */
535 qat_cmd_id = qat_get_cmd_id(xform);
536 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
537 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
540 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
541 switch (session->qat_cmd) {
542 case ICP_QAT_FW_LA_CMD_CIPHER:
543 ret = qat_crypto_sym_configure_session_cipher(dev, xform, session);
547 case ICP_QAT_FW_LA_CMD_AUTH:
548 ret = qat_crypto_sym_configure_session_auth(dev, xform, session);
552 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
553 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
554 ret = qat_crypto_sym_configure_session_aead(xform,
559 ret = qat_crypto_sym_configure_session_cipher(dev,
563 ret = qat_crypto_sym_configure_session_auth(dev,
569 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
570 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
571 ret = qat_crypto_sym_configure_session_aead(xform,
576 ret = qat_crypto_sym_configure_session_auth(dev,
580 ret = qat_crypto_sym_configure_session_cipher(dev,
586 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
587 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
588 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
589 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
590 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
591 case ICP_QAT_FW_LA_CMD_MGF1:
592 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
593 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
594 case ICP_QAT_FW_LA_CMD_DELIMITER:
595 PMD_DRV_LOG(ERR, "Unsupported Service %u",
599 PMD_DRV_LOG(ERR, "Unsupported Service %u",
608 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
609 struct rte_crypto_sym_xform *xform,
610 struct qat_session *session)
612 struct rte_crypto_auth_xform *auth_xform = NULL;
613 struct qat_pmd_private *internals = dev->data->dev_private;
614 auth_xform = qat_get_auth_xform(xform);
615 uint8_t *key_data = auth_xform->key.data;
616 uint8_t key_length = auth_xform->key.length;
618 switch (auth_xform->algo) {
619 case RTE_CRYPTO_AUTH_SHA1_HMAC:
620 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
622 case RTE_CRYPTO_AUTH_SHA224_HMAC:
623 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
625 case RTE_CRYPTO_AUTH_SHA256_HMAC:
626 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
628 case RTE_CRYPTO_AUTH_SHA384_HMAC:
629 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
631 case RTE_CRYPTO_AUTH_SHA512_HMAC:
632 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
634 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
635 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
637 case RTE_CRYPTO_AUTH_AES_GMAC:
638 if (qat_alg_validate_aes_key(auth_xform->key.length,
639 &session->qat_cipher_alg) != 0) {
640 PMD_DRV_LOG(ERR, "Invalid AES key size");
643 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
644 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
647 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
648 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
650 case RTE_CRYPTO_AUTH_MD5_HMAC:
651 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
653 case RTE_CRYPTO_AUTH_NULL:
654 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
656 case RTE_CRYPTO_AUTH_KASUMI_F9:
657 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
659 case RTE_CRYPTO_AUTH_ZUC_EIA3:
660 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
661 PMD_DRV_LOG(ERR, "%s not supported on this device",
662 rte_crypto_auth_algorithm_strings
666 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
668 case RTE_CRYPTO_AUTH_SHA1:
669 case RTE_CRYPTO_AUTH_SHA256:
670 case RTE_CRYPTO_AUTH_SHA512:
671 case RTE_CRYPTO_AUTH_SHA224:
672 case RTE_CRYPTO_AUTH_SHA384:
673 case RTE_CRYPTO_AUTH_MD5:
674 case RTE_CRYPTO_AUTH_AES_CMAC:
675 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
676 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
680 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
685 session->auth_iv.offset = auth_xform->iv.offset;
686 session->auth_iv.length = auth_xform->iv.length;
688 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
689 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
690 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
691 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
693 * It needs to create cipher desc content first,
694 * then authentication
696 if (qat_alg_aead_session_create_content_desc_cipher(session,
697 auth_xform->key.data,
698 auth_xform->key.length))
701 if (qat_alg_aead_session_create_content_desc_auth(session,
705 auth_xform->digest_length,
709 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
710 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
712 * It needs to create authentication desc content first,
715 if (qat_alg_aead_session_create_content_desc_auth(session,
719 auth_xform->digest_length,
723 if (qat_alg_aead_session_create_content_desc_cipher(session,
724 auth_xform->key.data,
725 auth_xform->key.length))
728 /* Restore to authentication only only */
729 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
731 if (qat_alg_aead_session_create_content_desc_auth(session,
735 auth_xform->digest_length,
740 session->digest_length = auth_xform->digest_length;
745 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
746 struct qat_session *session)
748 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
749 enum rte_crypto_auth_operation crypto_operation;
752 * Store AEAD IV parameters as cipher IV,
753 * to avoid unnecessary memory usage
755 session->cipher_iv.offset = xform->aead.iv.offset;
756 session->cipher_iv.length = xform->aead.iv.length;
758 switch (aead_xform->algo) {
759 case RTE_CRYPTO_AEAD_AES_GCM:
760 if (qat_alg_validate_aes_key(aead_xform->key.length,
761 &session->qat_cipher_alg) != 0) {
762 PMD_DRV_LOG(ERR, "Invalid AES key size");
765 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
766 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
768 case RTE_CRYPTO_AEAD_AES_CCM:
769 if (qat_alg_validate_aes_key(aead_xform->key.length,
770 &session->qat_cipher_alg) != 0) {
771 PMD_DRV_LOG(ERR, "Invalid AES key size");
774 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
775 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;
778 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
783 if ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
784 aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||
785 (aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
786 aead_xform->algo == RTE_CRYPTO_AEAD_AES_CCM)) {
787 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
789 * It needs to create cipher desc content first,
790 * then authentication
793 crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
794 RTE_CRYPTO_AUTH_OP_GENERATE : RTE_CRYPTO_AUTH_OP_VERIFY;
796 if (qat_alg_aead_session_create_content_desc_cipher(session,
797 aead_xform->key.data,
798 aead_xform->key.length))
801 if (qat_alg_aead_session_create_content_desc_auth(session,
802 aead_xform->key.data,
803 aead_xform->key.length,
804 aead_xform->aad_length,
805 aead_xform->digest_length,
809 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
811 * It needs to create authentication desc content first,
815 crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
816 RTE_CRYPTO_AUTH_OP_VERIFY : RTE_CRYPTO_AUTH_OP_GENERATE;
818 if (qat_alg_aead_session_create_content_desc_auth(session,
819 aead_xform->key.data,
820 aead_xform->key.length,
821 aead_xform->aad_length,
822 aead_xform->digest_length,
826 if (qat_alg_aead_session_create_content_desc_cipher(session,
827 aead_xform->key.data,
828 aead_xform->key.length))
832 session->digest_length = aead_xform->digest_length;
836 unsigned qat_crypto_sym_get_session_private_size(
837 struct rte_cryptodev *dev __rte_unused)
839 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
842 static inline uint32_t
843 qat_bpicipher_preprocess(struct qat_session *ctx,
844 struct rte_crypto_op *op)
846 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
847 struct rte_crypto_sym_op *sym_op = op->sym;
848 uint8_t last_block_len = block_len > 0 ?
849 sym_op->cipher.data.length % block_len : 0;
851 if (last_block_len &&
852 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
854 /* Decrypt last block */
855 uint8_t *last_block, *dst, *iv;
856 uint32_t last_block_offset = sym_op->cipher.data.offset +
857 sym_op->cipher.data.length - last_block_len;
858 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
859 uint8_t *, last_block_offset);
861 if (unlikely(sym_op->m_dst != NULL))
862 /* out-of-place operation (OOP) */
863 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
864 uint8_t *, last_block_offset);
868 if (last_block_len < sym_op->cipher.data.length)
869 /* use previous block ciphertext as IV */
870 iv = last_block - block_len;
872 /* runt block, i.e. less than one full block */
873 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
874 ctx->cipher_iv.offset);
876 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
877 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
879 if (sym_op->m_dst != NULL)
880 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
883 bpi_cipher_decrypt(last_block, dst, iv, block_len,
884 last_block_len, ctx->bpi_ctx);
885 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
886 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
888 if (sym_op->m_dst != NULL)
889 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
894 return sym_op->cipher.data.length - last_block_len;
897 static inline uint32_t
898 qat_bpicipher_postprocess(struct qat_session *ctx,
899 struct rte_crypto_op *op)
901 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
902 struct rte_crypto_sym_op *sym_op = op->sym;
903 uint8_t last_block_len = block_len > 0 ?
904 sym_op->cipher.data.length % block_len : 0;
906 if (last_block_len > 0 &&
907 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
909 /* Encrypt last block */
910 uint8_t *last_block, *dst, *iv;
911 uint32_t last_block_offset;
913 last_block_offset = sym_op->cipher.data.offset +
914 sym_op->cipher.data.length - last_block_len;
915 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
916 uint8_t *, last_block_offset);
918 if (unlikely(sym_op->m_dst != NULL))
919 /* out-of-place operation (OOP) */
920 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
921 uint8_t *, last_block_offset);
925 if (last_block_len < sym_op->cipher.data.length)
926 /* use previous block ciphertext as IV */
927 iv = dst - block_len;
929 /* runt block, i.e. less than one full block */
930 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
931 ctx->cipher_iv.offset);
933 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
934 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
936 if (sym_op->m_dst != NULL)
937 rte_hexdump(stdout, "BPI: dst before post-process:",
938 dst, last_block_len);
940 bpi_cipher_encrypt(last_block, dst, iv, block_len,
941 last_block_len, ctx->bpi_ctx);
942 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
943 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
945 if (sym_op->m_dst != NULL)
946 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
950 return sym_op->cipher.data.length - last_block_len;
954 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
955 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
956 q->hw_queue_number, q->tail);
957 q->nb_pending_requests = 0;
958 q->csr_tail = q->tail;
962 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
965 register struct qat_queue *queue;
966 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
967 register uint32_t nb_ops_sent = 0;
968 register struct rte_crypto_op **cur_op = ops;
970 uint16_t nb_ops_possible = nb_ops;
971 register uint8_t *base_addr;
972 register uint32_t tail;
975 if (unlikely(nb_ops == 0))
978 /* read params used a lot in main loop into registers */
979 queue = &(tmp_qp->tx_q);
980 base_addr = (uint8_t *)queue->base_addr;
983 /* Find how many can actually fit on the ring */
984 tmp_qp->inflights16 += nb_ops;
985 overflow = tmp_qp->inflights16 - queue->max_inflights;
987 tmp_qp->inflights16 -= overflow;
988 nb_ops_possible = nb_ops - overflow;
989 if (nb_ops_possible == 0)
993 while (nb_ops_sent != nb_ops_possible) {
994 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
995 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
997 tmp_qp->stats.enqueue_err_count++;
999 * This message cannot be enqueued,
1000 * decrease number of ops that wasn't sent
1002 tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
1003 if (nb_ops_sent == 0)
1008 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
1014 tmp_qp->stats.enqueued_count += nb_ops_sent;
1015 queue->nb_pending_requests += nb_ops_sent;
1016 if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
1017 queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
1018 txq_write_tail(tmp_qp, queue);
1024 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
1026 uint32_t old_head, new_head;
1029 old_head = q->csr_head;
1031 max_head = qp->nb_descriptors * q->msg_size;
1033 /* write out free descriptors */
1034 void *cur_desc = (uint8_t *)q->base_addr + old_head;
1036 if (new_head < old_head) {
1037 memset(cur_desc, ADF_RING_EMPTY_SIG, max_head - old_head);
1038 memset(q->base_addr, ADF_RING_EMPTY_SIG, new_head);
1040 memset(cur_desc, ADF_RING_EMPTY_SIG, new_head - old_head);
1042 q->nb_processed_responses = 0;
1043 q->csr_head = new_head;
1045 /* write current head to CSR */
1046 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
1047 q->hw_queue_number, new_head);
1051 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
1054 struct qat_queue *rx_queue, *tx_queue;
1055 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
1056 uint32_t msg_counter = 0;
1057 struct rte_crypto_op *rx_op;
1058 struct icp_qat_fw_comn_resp *resp_msg;
1061 rx_queue = &(tmp_qp->rx_q);
1062 tx_queue = &(tmp_qp->tx_q);
1063 head = rx_queue->head;
1064 resp_msg = (struct icp_qat_fw_comn_resp *)
1065 ((uint8_t *)rx_queue->base_addr + head);
1067 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
1068 msg_counter != nb_ops) {
1069 rx_op = (struct rte_crypto_op *)(uintptr_t)
1070 (resp_msg->opaque_data);
1072 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1073 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
1074 sizeof(struct icp_qat_fw_comn_resp));
1076 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
1077 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
1078 resp_msg->comn_hdr.comn_status)) {
1079 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1081 struct qat_session *sess = (struct qat_session *)
1082 get_session_private_data(
1083 rx_op->sym->session,
1084 cryptodev_qat_driver_id);
1087 qat_bpicipher_postprocess(sess, rx_op);
1088 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1091 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
1092 resp_msg = (struct icp_qat_fw_comn_resp *)
1093 ((uint8_t *)rx_queue->base_addr + head);
1098 if (msg_counter > 0) {
1099 rx_queue->head = head;
1100 tmp_qp->stats.dequeued_count += msg_counter;
1101 rx_queue->nb_processed_responses += msg_counter;
1102 tmp_qp->inflights16 -= msg_counter;
1104 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
1105 rxq_free_desc(tmp_qp, rx_queue);
1107 /* also check if tail needs to be advanced */
1108 if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
1109 tx_queue->tail != tx_queue->csr_tail) {
1110 txq_write_tail(tmp_qp, tx_queue);
1116 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1117 struct qat_alg_buf_list *list, uint32_t data_len)
1121 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1122 buff_start + rte_pktmbuf_data_len(buf);
1124 list->bufers[0].addr = buff_start;
1125 list->bufers[0].resrvd = 0;
1126 list->bufers[0].len = buf_len;
1128 if (data_len <= buf_len) {
1129 list->num_bufs = nr;
1130 list->bufers[0].len = data_len;
1136 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1137 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1139 QAT_SGL_MAX_NUMBER);
1143 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1144 list->bufers[nr].resrvd = 0;
1145 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1147 buf_len += list->bufers[nr].len;
1150 if (buf_len > data_len) {
1151 list->bufers[nr].len -=
1157 list->num_bufs = nr;
1163 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1164 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1165 struct rte_crypto_op *op,
1166 struct icp_qat_fw_la_bulk_req *qat_req)
1168 /* copy IV into request if it fits */
1169 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1170 rte_memcpy(cipher_param->u.cipher_IV_array,
1171 rte_crypto_op_ctod_offset(op, uint8_t *,
1175 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1176 qat_req->comn_hdr.serv_specif_flags,
1177 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1178 cipher_param->u.s.cipher_IV_ptr =
1179 rte_crypto_op_ctophys_offset(op,
1184 /** Set IV for CCM is special case, 0th byte is set to q-1
1185 * where q is padding of nonce in 16 byte block
1188 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
1189 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1190 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
1192 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
1193 ICP_QAT_HW_CCM_NONCE_OFFSET,
1194 rte_crypto_op_ctod_offset(op, uint8_t *,
1195 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
1197 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
1198 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
1200 if (aad_len_field_sz)
1201 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
1202 rte_crypto_op_ctod_offset(op, uint8_t *,
1203 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
1208 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1209 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1212 struct qat_session *ctx;
1213 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1214 struct icp_qat_fw_la_auth_req_params *auth_param;
1215 register struct icp_qat_fw_la_bulk_req *qat_req;
1216 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1217 uint32_t cipher_len = 0, cipher_ofs = 0;
1218 uint32_t auth_len = 0, auth_ofs = 0;
1219 uint32_t min_ofs = 0;
1220 uint64_t src_buf_start = 0, dst_buf_start = 0;
1223 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1224 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1225 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1226 "operation requests, op (%p) is not a "
1227 "symmetric operation.", op);
1231 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1232 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1233 " requests, op (%p) is sessionless.", op);
1237 ctx = (struct qat_session *)get_session_private_data(
1238 op->sym->session, cryptodev_qat_driver_id);
1240 if (unlikely(ctx == NULL)) {
1241 PMD_DRV_LOG(ERR, "Session was not created for this device");
1245 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1246 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1247 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1253 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1254 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1255 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1256 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1257 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1259 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1260 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1261 /* AES-GCM or AES-CCM */
1262 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1263 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
1264 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
1265 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
1266 && ctx->qat_hash_alg ==
1267 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
1273 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1276 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1283 if (ctx->qat_cipher_alg ==
1284 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1285 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1286 ctx->qat_cipher_alg ==
1287 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1290 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1291 || (cipher_param->cipher_offset
1292 % BYTE_LENGTH != 0))) {
1294 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1295 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1298 cipher_len = op->sym->cipher.data.length >> 3;
1299 cipher_ofs = op->sym->cipher.data.offset >> 3;
1301 } else if (ctx->bpi_ctx) {
1302 /* DOCSIS - only send complete blocks to device
1303 * Process any partial block using CFB mode.
1304 * Even if 0 complete blocks, still send this to device
1305 * to get into rx queue for post-process and dequeuing
1307 cipher_len = qat_bpicipher_preprocess(ctx, op);
1308 cipher_ofs = op->sym->cipher.data.offset;
1310 cipher_len = op->sym->cipher.data.length;
1311 cipher_ofs = op->sym->cipher.data.offset;
1314 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1315 cipher_param, op, qat_req);
1316 min_ofs = cipher_ofs;
1321 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1322 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1323 ctx->qat_hash_alg ==
1324 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1325 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1326 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1328 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1329 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1332 auth_ofs = op->sym->auth.data.offset >> 3;
1333 auth_len = op->sym->auth.data.length >> 3;
1335 auth_param->u1.aad_adr =
1336 rte_crypto_op_ctophys_offset(op,
1337 ctx->auth_iv.offset);
1339 } else if (ctx->qat_hash_alg ==
1340 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1341 ctx->qat_hash_alg ==
1342 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1344 set_cipher_iv(ctx->auth_iv.length,
1345 ctx->auth_iv.offset,
1346 cipher_param, op, qat_req);
1347 auth_ofs = op->sym->auth.data.offset;
1348 auth_len = op->sym->auth.data.length;
1350 auth_param->u1.aad_adr = 0;
1351 auth_param->u2.aad_sz = 0;
1354 * If len(iv)==12B fw computes J0
1356 if (ctx->auth_iv.length == 12) {
1357 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1358 qat_req->comn_hdr.serv_specif_flags,
1359 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1363 auth_ofs = op->sym->auth.data.offset;
1364 auth_len = op->sym->auth.data.length;
1369 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1375 * This address may used for setting AAD physical pointer
1376 * into IV offset from op
1378 phys_addr_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
1379 if (ctx->qat_hash_alg ==
1380 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1381 ctx->qat_hash_alg ==
1382 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1384 * If len(iv)==12B fw computes J0
1386 if (ctx->cipher_iv.length == 12) {
1387 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1388 qat_req->comn_hdr.serv_specif_flags,
1389 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1392 set_cipher_iv(ctx->cipher_iv.length,
1393 ctx->cipher_iv.offset,
1394 cipher_param, op, qat_req);
1396 } else if (ctx->qat_hash_alg ==
1397 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
1399 /* In case of AES-CCM this may point to user selected memory
1400 * or iv offset in cypto_op
1402 uint8_t *aad_data = op->sym->aead.aad.data;
1403 /* This is true AAD length, it not includes 18 bytes of
1406 uint8_t aad_ccm_real_len = 0;
1408 uint8_t aad_len_field_sz = 0;
1409 uint32_t msg_len_be =
1410 rte_bswap32(op->sym->aead.data.length);
1412 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
1413 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
1414 aad_ccm_real_len = ctx->aad_len -
1415 ICP_QAT_HW_CCM_AAD_B0_LEN -
1416 ICP_QAT_HW_CCM_AAD_LEN_INFO;
1419 * aad_len not greater than 18, so no actual aad data,
1420 * then use IV after op for B0 block
1422 aad_data = rte_crypto_op_ctod_offset(op, uint8_t *,
1423 ctx->cipher_iv.offset);
1424 aad_phys_addr_aead =
1425 rte_crypto_op_ctophys_offset(op,
1426 ctx->cipher_iv.offset);
1429 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST - ctx->cipher_iv.length;
1431 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(aad_len_field_sz,
1432 ctx->digest_length, q);
1434 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
1435 memcpy(aad_data + ctx->cipher_iv.length +
1436 ICP_QAT_HW_CCM_NONCE_OFFSET
1437 + (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
1438 (uint8_t *)&msg_len_be,
1439 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
1441 memcpy(aad_data + ctx->cipher_iv.length +
1442 ICP_QAT_HW_CCM_NONCE_OFFSET,
1443 (uint8_t *)&msg_len_be
1444 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
1448 if (aad_len_field_sz > 0) {
1449 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
1450 = rte_bswap16(aad_ccm_real_len);
1452 if ((aad_ccm_real_len + aad_len_field_sz)
1453 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
1454 uint8_t pad_len = 0;
1455 uint8_t pad_idx = 0;
1457 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
1458 ((aad_ccm_real_len + aad_len_field_sz) %
1459 ICP_QAT_HW_CCM_AAD_B0_LEN);
1460 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
1461 aad_ccm_real_len + aad_len_field_sz;
1462 memset(&aad_data[pad_idx],
1468 set_cipher_iv_ccm(ctx->cipher_iv.length,
1469 ctx->cipher_iv.offset,
1470 cipher_param, op, q,
1475 cipher_len = op->sym->aead.data.length;
1476 cipher_ofs = op->sym->aead.data.offset;
1477 auth_len = op->sym->aead.data.length;
1478 auth_ofs = op->sym->aead.data.offset;
1480 auth_param->u1.aad_adr = aad_phys_addr_aead;
1481 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1482 min_ofs = op->sym->aead.data.offset;
1485 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1488 /* adjust for chain case */
1489 if (do_cipher && do_auth)
1490 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1492 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1495 if (unlikely(op->sym->m_dst != NULL)) {
1496 /* Out-of-place operation (OOP)
1497 * Don't align DMA start. DMA the minimum data-set
1498 * so as not to overwrite data in dest buffer
1501 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1503 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1506 /* In-place operation
1507 * Start DMA at nearest aligned address below min_ofs
1510 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1511 & QAT_64_BTYE_ALIGN_MASK;
1513 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1514 rte_pktmbuf_headroom(op->sym->m_src))
1516 /* alignment has pushed addr ahead of start of mbuf
1517 * so revert and take the performance hit
1520 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1523 dst_buf_start = src_buf_start;
1526 if (do_cipher || do_aead) {
1527 cipher_param->cipher_offset =
1528 (uint32_t)rte_pktmbuf_mtophys_offset(
1529 op->sym->m_src, cipher_ofs) - src_buf_start;
1530 cipher_param->cipher_length = cipher_len;
1532 cipher_param->cipher_offset = 0;
1533 cipher_param->cipher_length = 0;
1536 if (do_auth || do_aead) {
1537 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1538 op->sym->m_src, auth_ofs) - src_buf_start;
1539 auth_param->auth_len = auth_len;
1541 auth_param->auth_off = 0;
1542 auth_param->auth_len = 0;
1545 qat_req->comn_mid.dst_length =
1546 qat_req->comn_mid.src_length =
1547 (cipher_param->cipher_offset + cipher_param->cipher_length)
1548 > (auth_param->auth_off + auth_param->auth_len) ?
1549 (cipher_param->cipher_offset + cipher_param->cipher_length)
1550 : (auth_param->auth_off + auth_param->auth_len);
1554 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1555 QAT_COMN_PTR_TYPE_SGL);
1556 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1557 &qat_op_cookie->qat_sgl_list_src,
1558 qat_req->comn_mid.src_length);
1560 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1564 if (likely(op->sym->m_dst == NULL))
1565 qat_req->comn_mid.dest_data_addr =
1566 qat_req->comn_mid.src_data_addr =
1567 qat_op_cookie->qat_sgl_src_phys_addr;
1569 ret = qat_sgl_fill_array(op->sym->m_dst,
1571 &qat_op_cookie->qat_sgl_list_dst,
1572 qat_req->comn_mid.dst_length);
1575 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1580 qat_req->comn_mid.src_data_addr =
1581 qat_op_cookie->qat_sgl_src_phys_addr;
1582 qat_req->comn_mid.dest_data_addr =
1583 qat_op_cookie->qat_sgl_dst_phys_addr;
1586 qat_req->comn_mid.src_data_addr = src_buf_start;
1587 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1590 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1591 rte_hexdump(stdout, "qat_req:", qat_req,
1592 sizeof(struct icp_qat_fw_la_bulk_req));
1593 rte_hexdump(stdout, "src_data:",
1594 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1595 rte_pktmbuf_data_len(op->sym->m_src));
1597 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1599 ctx->cipher_iv.offset);
1600 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1601 ctx->cipher_iv.length);
1605 if (ctx->auth_iv.length) {
1606 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1608 ctx->auth_iv.offset);
1609 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1610 ctx->auth_iv.length);
1612 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1613 ctx->digest_length);
1617 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1618 ctx->digest_length);
1619 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1626 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1628 uint32_t div = data >> shift;
1629 uint32_t mult = div << shift;
1634 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1635 __rte_unused struct rte_cryptodev_config *config)
1637 PMD_INIT_FUNC_TRACE();
1641 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1643 PMD_INIT_FUNC_TRACE();
1647 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1649 PMD_INIT_FUNC_TRACE();
1652 int qat_dev_close(struct rte_cryptodev *dev)
1656 PMD_INIT_FUNC_TRACE();
1658 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1659 ret = qat_crypto_sym_qp_release(dev, i);
1667 void qat_dev_info_get(struct rte_cryptodev *dev,
1668 struct rte_cryptodev_info *info)
1670 struct qat_pmd_private *internals = dev->data->dev_private;
1672 PMD_INIT_FUNC_TRACE();
1674 info->max_nb_queue_pairs =
1675 ADF_NUM_SYM_QPS_PER_BUNDLE *
1676 ADF_NUM_BUNDLES_PER_DEV;
1677 info->feature_flags = dev->feature_flags;
1678 info->capabilities = internals->qat_dev_capabilities;
1679 info->sym.max_nb_sessions = internals->max_nb_sessions;
1680 info->driver_id = cryptodev_qat_driver_id;
1681 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1685 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1686 struct rte_cryptodev_stats *stats)
1689 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1691 PMD_INIT_FUNC_TRACE();
1692 if (stats == NULL) {
1693 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1696 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1697 if (qp[i] == NULL) {
1698 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1702 stats->enqueued_count += qp[i]->stats.enqueued_count;
1703 stats->dequeued_count += qp[i]->stats.dequeued_count;
1704 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1705 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1709 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1712 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1714 PMD_INIT_FUNC_TRACE();
1715 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1716 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1717 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");