4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
155 { /* AES GCM (AUTH) */
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_AES_GCM,
180 { /* SNOW3G (UIA2) */
181 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
183 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
185 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
205 { /* AES GCM (CIPHER) */
206 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
208 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
210 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
226 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
228 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
230 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
245 { /* SNOW3G (UEA2) */
246 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
248 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
250 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
266 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
268 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
270 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
285 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
288 static inline uint32_t
289 adf_modulo(uint32_t data, uint32_t shift);
292 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
294 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
297 struct qat_session *sess = session;
298 phys_addr_t cd_paddr;
300 PMD_INIT_FUNC_TRACE();
302 cd_paddr = sess->cd_paddr;
303 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
304 sess->cd_paddr = cd_paddr;
306 PMD_DRV_LOG(ERR, "NULL session");
310 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
313 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
314 return ICP_QAT_FW_LA_CMD_CIPHER;
316 /* Authentication Only */
317 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
318 return ICP_QAT_FW_LA_CMD_AUTH;
320 if (xform->next == NULL)
323 /* Cipher then Authenticate */
324 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
325 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
326 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
328 /* Authenticate then Cipher */
329 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
330 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
331 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
336 static struct rte_crypto_auth_xform *
337 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
340 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
349 static struct rte_crypto_cipher_xform *
350 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
353 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
354 return &xform->cipher;
362 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
363 struct rte_crypto_sym_xform *xform, void *session_private)
365 struct qat_pmd_private *internals = dev->data->dev_private;
367 struct qat_session *session = session_private;
369 struct rte_crypto_cipher_xform *cipher_xform = NULL;
371 /* Get cipher xform from crypto xform chain */
372 cipher_xform = qat_get_cipher_xform(xform);
374 switch (cipher_xform->algo) {
375 case RTE_CRYPTO_CIPHER_AES_CBC:
376 if (qat_alg_validate_aes_key(cipher_xform->key.length,
377 &session->qat_cipher_alg) != 0) {
378 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
381 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
383 case RTE_CRYPTO_CIPHER_AES_GCM:
384 if (qat_alg_validate_aes_key(cipher_xform->key.length,
385 &session->qat_cipher_alg) != 0) {
386 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
389 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
391 case RTE_CRYPTO_CIPHER_AES_CTR:
392 if (qat_alg_validate_aes_key(cipher_xform->key.length,
393 &session->qat_cipher_alg) != 0) {
394 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
397 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
399 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
400 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
401 &session->qat_cipher_alg) != 0) {
402 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
405 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
407 case RTE_CRYPTO_CIPHER_NULL:
408 case RTE_CRYPTO_CIPHER_3DES_ECB:
409 case RTE_CRYPTO_CIPHER_3DES_CBC:
410 case RTE_CRYPTO_CIPHER_AES_ECB:
411 case RTE_CRYPTO_CIPHER_AES_CCM:
412 case RTE_CRYPTO_CIPHER_KASUMI_F8:
413 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
417 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
422 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
423 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
425 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
427 if (qat_alg_aead_session_create_content_desc_cipher(session,
428 cipher_xform->key.data,
429 cipher_xform->key.length))
435 rte_mempool_put(internals->sess_mp, session);
441 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
442 struct rte_crypto_sym_xform *xform, void *session_private)
444 struct qat_pmd_private *internals = dev->data->dev_private;
446 struct qat_session *session = session_private;
450 PMD_INIT_FUNC_TRACE();
452 /* Get requested QAT command id */
453 qat_cmd_id = qat_get_cmd_id(xform);
454 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
455 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
458 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
459 switch (session->qat_cmd) {
460 case ICP_QAT_FW_LA_CMD_CIPHER:
461 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
463 case ICP_QAT_FW_LA_CMD_AUTH:
464 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
466 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
467 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
468 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
470 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
471 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
472 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
474 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
475 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
476 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
477 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
478 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
479 case ICP_QAT_FW_LA_CMD_MGF1:
480 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
481 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
482 case ICP_QAT_FW_LA_CMD_DELIMITER:
483 PMD_DRV_LOG(ERR, "Unsupported Service %u",
487 PMD_DRV_LOG(ERR, "Unsupported Service %u",
494 rte_mempool_put(internals->sess_mp, session);
499 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
500 struct rte_crypto_sym_xform *xform,
501 struct qat_session *session_private)
504 struct qat_pmd_private *internals = dev->data->dev_private;
505 struct qat_session *session = session_private;
506 struct rte_crypto_auth_xform *auth_xform = NULL;
507 struct rte_crypto_cipher_xform *cipher_xform = NULL;
508 auth_xform = qat_get_auth_xform(xform);
510 switch (auth_xform->algo) {
511 case RTE_CRYPTO_AUTH_SHA1_HMAC:
512 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
514 case RTE_CRYPTO_AUTH_SHA256_HMAC:
515 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
517 case RTE_CRYPTO_AUTH_SHA512_HMAC:
518 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
520 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
521 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
523 case RTE_CRYPTO_AUTH_AES_GCM:
524 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
526 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
527 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
529 case RTE_CRYPTO_AUTH_NULL:
530 case RTE_CRYPTO_AUTH_SHA1:
531 case RTE_CRYPTO_AUTH_SHA256:
532 case RTE_CRYPTO_AUTH_SHA512:
533 case RTE_CRYPTO_AUTH_SHA224:
534 case RTE_CRYPTO_AUTH_SHA224_HMAC:
535 case RTE_CRYPTO_AUTH_SHA384:
536 case RTE_CRYPTO_AUTH_SHA384_HMAC:
537 case RTE_CRYPTO_AUTH_MD5:
538 case RTE_CRYPTO_AUTH_MD5_HMAC:
539 case RTE_CRYPTO_AUTH_AES_CCM:
540 case RTE_CRYPTO_AUTH_AES_GMAC:
541 case RTE_CRYPTO_AUTH_KASUMI_F9:
542 case RTE_CRYPTO_AUTH_AES_CMAC:
543 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
544 case RTE_CRYPTO_AUTH_ZUC_EIA3:
545 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
549 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
553 cipher_xform = qat_get_cipher_xform(xform);
555 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
556 (session->qat_hash_alg ==
557 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
558 if (qat_alg_aead_session_create_content_desc_auth(session,
559 cipher_xform->key.data,
560 cipher_xform->key.length,
561 auth_xform->add_auth_data_length,
562 auth_xform->digest_length,
566 if (qat_alg_aead_session_create_content_desc_auth(session,
567 auth_xform->key.data,
568 auth_xform->key.length,
569 auth_xform->add_auth_data_length,
570 auth_xform->digest_length,
577 rte_mempool_put(internals->sess_mp, session);
581 unsigned qat_crypto_sym_get_session_private_size(
582 struct rte_cryptodev *dev __rte_unused)
584 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
589 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
592 register struct qat_queue *queue;
593 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
594 register uint32_t nb_ops_sent = 0;
595 register struct rte_crypto_op **cur_op = ops;
597 uint16_t nb_ops_possible = nb_ops;
598 register uint8_t *base_addr;
599 register uint32_t tail;
602 if (unlikely(nb_ops == 0))
605 /* read params used a lot in main loop into registers */
606 queue = &(tmp_qp->tx_q);
607 base_addr = (uint8_t *)queue->base_addr;
610 /* Find how many can actually fit on the ring */
611 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
612 - queue->max_inflights;
614 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
615 nb_ops_possible = nb_ops - overflow;
616 if (nb_ops_possible == 0)
620 while (nb_ops_sent != nb_ops_possible) {
621 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
623 tmp_qp->stats.enqueue_err_count++;
624 if (nb_ops_sent == 0)
629 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
634 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
635 queue->hw_queue_number, tail);
637 tmp_qp->stats.enqueued_count += nb_ops_sent;
642 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
645 struct qat_queue *queue;
646 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
647 uint32_t msg_counter = 0;
648 struct rte_crypto_op *rx_op;
649 struct icp_qat_fw_comn_resp *resp_msg;
651 queue = &(tmp_qp->rx_q);
652 resp_msg = (struct icp_qat_fw_comn_resp *)
653 ((uint8_t *)queue->base_addr + queue->head);
655 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
656 msg_counter != nb_ops) {
657 rx_op = (struct rte_crypto_op *)(uintptr_t)
658 (resp_msg->opaque_data);
660 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
661 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
662 sizeof(struct icp_qat_fw_comn_resp));
664 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
665 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
666 resp_msg->comn_hdr.comn_status)) {
667 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
669 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
671 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
672 queue->head = adf_modulo(queue->head +
674 ADF_RING_SIZE_MODULO(queue->queue_size));
675 resp_msg = (struct icp_qat_fw_comn_resp *)
676 ((uint8_t *)queue->base_addr +
682 if (msg_counter > 0) {
683 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
684 queue->hw_bundle_number,
685 queue->hw_queue_number, queue->head);
686 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
687 tmp_qp->stats.dequeued_count += msg_counter;
693 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
695 struct qat_session *ctx;
696 struct icp_qat_fw_la_cipher_req_params *cipher_param;
697 struct icp_qat_fw_la_auth_req_params *auth_param;
698 register struct icp_qat_fw_la_bulk_req *qat_req;
700 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
701 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
702 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
703 "operation requests, op (%p) is not a "
704 "symmetric operation.", op);
708 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
709 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
710 " requests, op (%p) is sessionless.", op);
714 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
715 PMD_DRV_LOG(ERR, "Session was not created for this device");
719 ctx = (struct qat_session *)op->sym->session->_private;
720 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
721 *qat_req = ctx->fw_req;
722 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
724 qat_req->comn_mid.dst_length =
725 qat_req->comn_mid.src_length =
726 rte_pktmbuf_data_len(op->sym->m_src);
728 qat_req->comn_mid.dest_data_addr =
729 qat_req->comn_mid.src_data_addr =
730 rte_pktmbuf_mtophys(op->sym->m_src);
732 if (unlikely(op->sym->m_dst != NULL)) {
733 qat_req->comn_mid.dest_data_addr =
734 rte_pktmbuf_mtophys(op->sym->m_dst);
735 qat_req->comn_mid.dst_length =
736 rte_pktmbuf_data_len(op->sym->m_dst);
739 cipher_param = (void *)&qat_req->serv_specif_rqpars;
740 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
742 cipher_param->cipher_length = op->sym->cipher.data.length;
743 cipher_param->cipher_offset = op->sym->cipher.data.offset;
744 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
745 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
746 (cipher_param->cipher_offset
747 % BYTE_LENGTH != 0))) {
748 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
749 "supports byte aligned values");
750 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
753 cipher_param->cipher_length >>= 3;
754 cipher_param->cipher_offset >>= 3;
757 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
758 sizeof(cipher_param->u.cipher_IV_array))) {
759 rte_memcpy(cipher_param->u.cipher_IV_array,
760 op->sym->cipher.iv.data,
761 op->sym->cipher.iv.length);
763 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
764 qat_req->comn_hdr.serv_specif_flags,
765 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
766 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
768 if (op->sym->auth.digest.phys_addr) {
769 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
770 qat_req->comn_hdr.serv_specif_flags,
771 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
772 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
774 auth_param->auth_off = op->sym->auth.data.offset;
775 auth_param->auth_len = op->sym->auth.data.length;
776 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
777 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
778 (auth_param->auth_len % BYTE_LENGTH != 0))) {
779 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
780 "supports byte aligned values");
781 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
784 auth_param->auth_off >>= 3;
785 auth_param->auth_len >>= 3;
787 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
788 /* (GCM) aad length(240 max) will be at this location after precompute */
789 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
790 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
791 struct icp_qat_hw_auth_algo_blk *hash;
793 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER)
794 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd);
796 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd +
797 sizeof(struct icp_qat_hw_cipher_algo_blk));
799 auth_param->u2.aad_sz = ALIGN_POW2_ROUNDUP(hash->sha.state1[
800 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
801 ICP_QAT_HW_GALOIS_H_SZ + 3], 16);
802 if (op->sym->cipher.iv.length == 12) {
804 * For GCM a 12 bit IV is allowed,
805 * but we need to inform the f/w
807 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
808 qat_req->comn_hdr.serv_specif_flags,
809 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
812 auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
815 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
816 rte_hexdump(stdout, "qat_req:", qat_req,
817 sizeof(struct icp_qat_fw_la_bulk_req));
818 rte_hexdump(stdout, "src_data:",
819 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
820 rte_pktmbuf_data_len(op->sym->m_src));
821 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
822 op->sym->cipher.iv.length);
823 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
824 op->sym->auth.digest.length);
825 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
826 op->sym->auth.aad.length);
831 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
833 uint32_t div = data >> shift;
834 uint32_t mult = div << shift;
839 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
841 struct rte_cryptodev_sym_session *sess = sym_sess;
842 struct qat_session *s = (void *)sess->_private;
844 PMD_INIT_FUNC_TRACE();
845 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
846 offsetof(struct qat_session, cd) +
847 offsetof(struct rte_cryptodev_sym_session, _private);
850 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
852 PMD_INIT_FUNC_TRACE();
856 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
858 PMD_INIT_FUNC_TRACE();
862 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
864 PMD_INIT_FUNC_TRACE();
867 int qat_dev_close(struct rte_cryptodev *dev)
871 PMD_INIT_FUNC_TRACE();
873 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
874 ret = qat_crypto_sym_qp_release(dev, i);
882 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
883 struct rte_cryptodev_info *info)
885 struct qat_pmd_private *internals = dev->data->dev_private;
887 PMD_INIT_FUNC_TRACE();
889 info->max_nb_queue_pairs =
890 ADF_NUM_SYM_QPS_PER_BUNDLE *
891 ADF_NUM_BUNDLES_PER_DEV;
892 info->feature_flags = dev->feature_flags;
893 info->capabilities = qat_pmd_capabilities;
894 info->sym.max_nb_sessions = internals->max_nb_sessions;
895 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
899 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
900 struct rte_cryptodev_stats *stats)
903 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
905 PMD_INIT_FUNC_TRACE();
907 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
910 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
912 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
916 stats->enqueued_count += qp[i]->stats.enqueued_count;
917 stats->dequeued_count += qp[i]->stats.enqueued_count;
918 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
919 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
923 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
926 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
928 PMD_INIT_FUNC_TRACE();
929 for (i = 0; i < dev->data->nb_queue_pairs; i++)
930 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
931 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");