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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
176 { /* AES GCM (AUTH) */
177 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
179 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
181 .algo = RTE_CRYPTO_AUTH_AES_GCM,
201 { /* SNOW3G (UIA2) */
202 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
204 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
206 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
226 { /* AES GCM (CIPHER) */
227 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
229 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
231 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
247 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
249 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
251 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
266 { /* SNOW3G (UEA2) */
267 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
269 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
271 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
287 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
289 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
291 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
306 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
309 static inline uint32_t
310 adf_modulo(uint32_t data, uint32_t shift);
313 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
315 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
318 struct qat_session *sess = session;
319 phys_addr_t cd_paddr;
321 PMD_INIT_FUNC_TRACE();
323 cd_paddr = sess->cd_paddr;
324 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
325 sess->cd_paddr = cd_paddr;
327 PMD_DRV_LOG(ERR, "NULL session");
331 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
334 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
335 return ICP_QAT_FW_LA_CMD_CIPHER;
337 /* Authentication Only */
338 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
339 return ICP_QAT_FW_LA_CMD_AUTH;
341 if (xform->next == NULL)
344 /* Cipher then Authenticate */
345 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
346 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
347 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
349 /* Authenticate then Cipher */
350 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
351 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
352 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
357 static struct rte_crypto_auth_xform *
358 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
361 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
370 static struct rte_crypto_cipher_xform *
371 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
374 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
375 return &xform->cipher;
383 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
384 struct rte_crypto_sym_xform *xform, void *session_private)
386 struct qat_pmd_private *internals = dev->data->dev_private;
388 struct qat_session *session = session_private;
390 struct rte_crypto_cipher_xform *cipher_xform = NULL;
392 /* Get cipher xform from crypto xform chain */
393 cipher_xform = qat_get_cipher_xform(xform);
395 switch (cipher_xform->algo) {
396 case RTE_CRYPTO_CIPHER_AES_CBC:
397 if (qat_alg_validate_aes_key(cipher_xform->key.length,
398 &session->qat_cipher_alg) != 0) {
399 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
402 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
404 case RTE_CRYPTO_CIPHER_AES_GCM:
405 if (qat_alg_validate_aes_key(cipher_xform->key.length,
406 &session->qat_cipher_alg) != 0) {
407 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
410 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
412 case RTE_CRYPTO_CIPHER_AES_CTR:
413 if (qat_alg_validate_aes_key(cipher_xform->key.length,
414 &session->qat_cipher_alg) != 0) {
415 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
418 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
420 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
421 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
422 &session->qat_cipher_alg) != 0) {
423 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
426 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
428 case RTE_CRYPTO_CIPHER_NULL:
429 case RTE_CRYPTO_CIPHER_3DES_ECB:
430 case RTE_CRYPTO_CIPHER_3DES_CBC:
431 case RTE_CRYPTO_CIPHER_AES_ECB:
432 case RTE_CRYPTO_CIPHER_AES_CCM:
433 case RTE_CRYPTO_CIPHER_KASUMI_F8:
434 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
438 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
443 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
444 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
446 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
448 if (qat_alg_aead_session_create_content_desc_cipher(session,
449 cipher_xform->key.data,
450 cipher_xform->key.length))
456 rte_mempool_put(internals->sess_mp, session);
462 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
463 struct rte_crypto_sym_xform *xform, void *session_private)
465 struct qat_pmd_private *internals = dev->data->dev_private;
467 struct qat_session *session = session_private;
471 PMD_INIT_FUNC_TRACE();
473 /* Get requested QAT command id */
474 qat_cmd_id = qat_get_cmd_id(xform);
475 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
476 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
479 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
480 switch (session->qat_cmd) {
481 case ICP_QAT_FW_LA_CMD_CIPHER:
482 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
484 case ICP_QAT_FW_LA_CMD_AUTH:
485 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
487 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
488 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
489 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
491 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
492 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
493 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
495 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
496 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
497 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
498 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
499 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
500 case ICP_QAT_FW_LA_CMD_MGF1:
501 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
502 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
503 case ICP_QAT_FW_LA_CMD_DELIMITER:
504 PMD_DRV_LOG(ERR, "Unsupported Service %u",
508 PMD_DRV_LOG(ERR, "Unsupported Service %u",
515 rte_mempool_put(internals->sess_mp, session);
520 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
521 struct rte_crypto_sym_xform *xform,
522 struct qat_session *session_private)
525 struct qat_pmd_private *internals = dev->data->dev_private;
526 struct qat_session *session = session_private;
527 struct rte_crypto_auth_xform *auth_xform = NULL;
528 struct rte_crypto_cipher_xform *cipher_xform = NULL;
529 auth_xform = qat_get_auth_xform(xform);
531 switch (auth_xform->algo) {
532 case RTE_CRYPTO_AUTH_SHA1_HMAC:
533 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
535 case RTE_CRYPTO_AUTH_SHA256_HMAC:
536 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
538 case RTE_CRYPTO_AUTH_SHA512_HMAC:
539 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
541 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
542 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
544 case RTE_CRYPTO_AUTH_AES_GCM:
545 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
547 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
548 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
550 case RTE_CRYPTO_AUTH_MD5_HMAC:
551 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
553 case RTE_CRYPTO_AUTH_NULL:
554 case RTE_CRYPTO_AUTH_SHA1:
555 case RTE_CRYPTO_AUTH_SHA256:
556 case RTE_CRYPTO_AUTH_SHA512:
557 case RTE_CRYPTO_AUTH_SHA224:
558 case RTE_CRYPTO_AUTH_SHA224_HMAC:
559 case RTE_CRYPTO_AUTH_SHA384:
560 case RTE_CRYPTO_AUTH_SHA384_HMAC:
561 case RTE_CRYPTO_AUTH_MD5:
562 case RTE_CRYPTO_AUTH_AES_CCM:
563 case RTE_CRYPTO_AUTH_AES_GMAC:
564 case RTE_CRYPTO_AUTH_KASUMI_F9:
565 case RTE_CRYPTO_AUTH_AES_CMAC:
566 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
567 case RTE_CRYPTO_AUTH_ZUC_EIA3:
568 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
572 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
576 cipher_xform = qat_get_cipher_xform(xform);
578 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
579 (session->qat_hash_alg ==
580 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
581 if (qat_alg_aead_session_create_content_desc_auth(session,
582 cipher_xform->key.data,
583 cipher_xform->key.length,
584 auth_xform->add_auth_data_length,
585 auth_xform->digest_length,
589 if (qat_alg_aead_session_create_content_desc_auth(session,
590 auth_xform->key.data,
591 auth_xform->key.length,
592 auth_xform->add_auth_data_length,
593 auth_xform->digest_length,
600 if (internals->sess_mp != NULL)
601 rte_mempool_put(internals->sess_mp, session);
605 unsigned qat_crypto_sym_get_session_private_size(
606 struct rte_cryptodev *dev __rte_unused)
608 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
613 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
616 register struct qat_queue *queue;
617 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
618 register uint32_t nb_ops_sent = 0;
619 register struct rte_crypto_op **cur_op = ops;
621 uint16_t nb_ops_possible = nb_ops;
622 register uint8_t *base_addr;
623 register uint32_t tail;
626 if (unlikely(nb_ops == 0))
629 /* read params used a lot in main loop into registers */
630 queue = &(tmp_qp->tx_q);
631 base_addr = (uint8_t *)queue->base_addr;
634 /* Find how many can actually fit on the ring */
635 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
636 - queue->max_inflights;
638 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
639 nb_ops_possible = nb_ops - overflow;
640 if (nb_ops_possible == 0)
644 while (nb_ops_sent != nb_ops_possible) {
645 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
647 tmp_qp->stats.enqueue_err_count++;
648 if (nb_ops_sent == 0)
653 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
658 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
659 queue->hw_queue_number, tail);
661 tmp_qp->stats.enqueued_count += nb_ops_sent;
666 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
669 struct qat_queue *queue;
670 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
671 uint32_t msg_counter = 0;
672 struct rte_crypto_op *rx_op;
673 struct icp_qat_fw_comn_resp *resp_msg;
675 queue = &(tmp_qp->rx_q);
676 resp_msg = (struct icp_qat_fw_comn_resp *)
677 ((uint8_t *)queue->base_addr + queue->head);
679 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
680 msg_counter != nb_ops) {
681 rx_op = (struct rte_crypto_op *)(uintptr_t)
682 (resp_msg->opaque_data);
684 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
685 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
686 sizeof(struct icp_qat_fw_comn_resp));
688 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
689 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
690 resp_msg->comn_hdr.comn_status)) {
691 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
693 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
695 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
696 queue->head = adf_modulo(queue->head +
698 ADF_RING_SIZE_MODULO(queue->queue_size));
699 resp_msg = (struct icp_qat_fw_comn_resp *)
700 ((uint8_t *)queue->base_addr +
706 if (msg_counter > 0) {
707 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
708 queue->hw_bundle_number,
709 queue->hw_queue_number, queue->head);
710 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
711 tmp_qp->stats.dequeued_count += msg_counter;
717 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
719 struct qat_session *ctx;
720 struct icp_qat_fw_la_cipher_req_params *cipher_param;
721 struct icp_qat_fw_la_auth_req_params *auth_param;
722 register struct icp_qat_fw_la_bulk_req *qat_req;
724 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
725 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
726 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
727 "operation requests, op (%p) is not a "
728 "symmetric operation.", op);
732 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
733 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
734 " requests, op (%p) is sessionless.", op);
738 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
739 PMD_DRV_LOG(ERR, "Session was not created for this device");
743 ctx = (struct qat_session *)op->sym->session->_private;
744 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
745 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
746 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
748 qat_req->comn_mid.dst_length =
749 qat_req->comn_mid.src_length =
750 rte_pktmbuf_data_len(op->sym->m_src);
752 qat_req->comn_mid.dest_data_addr =
753 qat_req->comn_mid.src_data_addr =
754 rte_pktmbuf_mtophys(op->sym->m_src);
756 if (unlikely(op->sym->m_dst != NULL)) {
757 qat_req->comn_mid.dest_data_addr =
758 rte_pktmbuf_mtophys(op->sym->m_dst);
759 qat_req->comn_mid.dst_length =
760 rte_pktmbuf_data_len(op->sym->m_dst);
763 cipher_param = (void *)&qat_req->serv_specif_rqpars;
764 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
766 cipher_param->cipher_length = op->sym->cipher.data.length;
767 cipher_param->cipher_offset = op->sym->cipher.data.offset;
768 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
769 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
770 (cipher_param->cipher_offset
771 % BYTE_LENGTH != 0))) {
772 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
773 "supports byte aligned values");
774 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
777 cipher_param->cipher_length >>= 3;
778 cipher_param->cipher_offset >>= 3;
781 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
782 sizeof(cipher_param->u.cipher_IV_array))) {
783 rte_memcpy(cipher_param->u.cipher_IV_array,
784 op->sym->cipher.iv.data,
785 op->sym->cipher.iv.length);
787 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
788 qat_req->comn_hdr.serv_specif_flags,
789 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
790 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
792 if (op->sym->auth.digest.phys_addr) {
793 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
794 qat_req->comn_hdr.serv_specif_flags,
795 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
796 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
798 auth_param->auth_off = op->sym->auth.data.offset;
799 auth_param->auth_len = op->sym->auth.data.length;
800 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
801 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
802 (auth_param->auth_len % BYTE_LENGTH != 0))) {
803 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
804 "supports byte aligned values");
805 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
808 auth_param->auth_off >>= 3;
809 auth_param->auth_len >>= 3;
811 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
813 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
814 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
815 if (op->sym->cipher.iv.length == 12) {
817 * For GCM a 12 bit IV is allowed,
818 * but we need to inform the f/w
820 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
821 qat_req->comn_hdr.serv_specif_flags,
822 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
826 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
827 rte_hexdump(stdout, "qat_req:", qat_req,
828 sizeof(struct icp_qat_fw_la_bulk_req));
829 rte_hexdump(stdout, "src_data:",
830 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
831 rte_pktmbuf_data_len(op->sym->m_src));
832 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
833 op->sym->cipher.iv.length);
834 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
835 op->sym->auth.digest.length);
836 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
837 op->sym->auth.aad.length);
842 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
844 uint32_t div = data >> shift;
845 uint32_t mult = div << shift;
850 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
852 struct rte_cryptodev_sym_session *sess = sym_sess;
853 struct qat_session *s = (void *)sess->_private;
855 PMD_INIT_FUNC_TRACE();
856 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
857 offsetof(struct qat_session, cd) +
858 offsetof(struct rte_cryptodev_sym_session, _private);
861 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
863 PMD_INIT_FUNC_TRACE();
867 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
869 PMD_INIT_FUNC_TRACE();
873 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
875 PMD_INIT_FUNC_TRACE();
878 int qat_dev_close(struct rte_cryptodev *dev)
882 PMD_INIT_FUNC_TRACE();
884 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
885 ret = qat_crypto_sym_qp_release(dev, i);
893 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
894 struct rte_cryptodev_info *info)
896 struct qat_pmd_private *internals = dev->data->dev_private;
898 PMD_INIT_FUNC_TRACE();
900 info->max_nb_queue_pairs =
901 ADF_NUM_SYM_QPS_PER_BUNDLE *
902 ADF_NUM_BUNDLES_PER_DEV;
903 info->feature_flags = dev->feature_flags;
904 info->capabilities = qat_pmd_capabilities;
905 info->sym.max_nb_sessions = internals->max_nb_sessions;
906 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
910 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
911 struct rte_cryptodev_stats *stats)
914 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
916 PMD_INIT_FUNC_TRACE();
918 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
921 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
923 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
927 stats->enqueued_count += qp[i]->stats.enqueued_count;
928 stats->dequeued_count += qp[i]->stats.enqueued_count;
929 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
930 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
934 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
937 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
939 PMD_INIT_FUNC_TRACE();
940 for (i = 0; i < dev->data->nb_queue_pairs; i++)
941 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
942 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");