4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
58 #include <rte_mempool.h>
60 #include <rte_string_fns.h>
61 #include <rte_spinlock.h>
62 #include <rte_hexdump.h>
66 #include "qat_crypto.h"
67 #include "adf_transport_access_macros.h"
71 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
73 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
75 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
77 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
94 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
96 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
98 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
115 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
117 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
119 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
136 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
138 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
140 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
156 { /* AES GCM (AUTH) */
157 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
159 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
161 .algo = RTE_CRYPTO_AUTH_AES_GCM,
181 { /* SNOW3G (UIA2) */
182 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
184 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
186 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
206 { /* AES GCM (CIPHER) */
207 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
209 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
211 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
227 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
229 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
231 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
246 { /* SNOW3G (UEA2) */
247 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
249 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
251 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
267 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
269 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
271 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
286 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
289 static inline uint32_t
290 adf_modulo(uint32_t data, uint32_t shift);
293 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
295 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
298 struct qat_session *sess = session;
299 phys_addr_t cd_paddr;
301 PMD_INIT_FUNC_TRACE();
303 cd_paddr = sess->cd_paddr;
304 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
305 sess->cd_paddr = cd_paddr;
307 PMD_DRV_LOG(ERR, "NULL session");
311 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
314 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
315 return ICP_QAT_FW_LA_CMD_CIPHER;
317 /* Authentication Only */
318 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
319 return ICP_QAT_FW_LA_CMD_AUTH;
321 if (xform->next == NULL)
324 /* Cipher then Authenticate */
325 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
326 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
327 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
329 /* Authenticate then Cipher */
330 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
331 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
332 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
337 static struct rte_crypto_auth_xform *
338 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
341 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
350 static struct rte_crypto_cipher_xform *
351 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
354 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
355 return &xform->cipher;
363 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
364 struct rte_crypto_sym_xform *xform, void *session_private)
366 struct qat_pmd_private *internals = dev->data->dev_private;
368 struct qat_session *session = session_private;
370 struct rte_crypto_cipher_xform *cipher_xform = NULL;
372 /* Get cipher xform from crypto xform chain */
373 cipher_xform = qat_get_cipher_xform(xform);
375 switch (cipher_xform->algo) {
376 case RTE_CRYPTO_CIPHER_AES_CBC:
377 if (qat_alg_validate_aes_key(cipher_xform->key.length,
378 &session->qat_cipher_alg) != 0) {
379 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
382 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
384 case RTE_CRYPTO_CIPHER_AES_GCM:
385 if (qat_alg_validate_aes_key(cipher_xform->key.length,
386 &session->qat_cipher_alg) != 0) {
387 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
390 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
392 case RTE_CRYPTO_CIPHER_AES_CTR:
393 if (qat_alg_validate_aes_key(cipher_xform->key.length,
394 &session->qat_cipher_alg) != 0) {
395 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
398 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
400 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
401 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
402 &session->qat_cipher_alg) != 0) {
403 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
406 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
408 case RTE_CRYPTO_CIPHER_NULL:
409 case RTE_CRYPTO_CIPHER_3DES_ECB:
410 case RTE_CRYPTO_CIPHER_3DES_CBC:
411 case RTE_CRYPTO_CIPHER_AES_ECB:
412 case RTE_CRYPTO_CIPHER_AES_CCM:
413 case RTE_CRYPTO_CIPHER_KASUMI_F8:
414 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
418 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
423 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
424 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
426 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
428 if (qat_alg_aead_session_create_content_desc_cipher(session,
429 cipher_xform->key.data,
430 cipher_xform->key.length))
436 rte_mempool_put(internals->sess_mp, session);
442 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
443 struct rte_crypto_sym_xform *xform, void *session_private)
445 struct qat_pmd_private *internals = dev->data->dev_private;
447 struct qat_session *session = session_private;
451 PMD_INIT_FUNC_TRACE();
453 /* Get requested QAT command id */
454 qat_cmd_id = qat_get_cmd_id(xform);
455 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
456 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
459 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
460 switch (session->qat_cmd) {
461 case ICP_QAT_FW_LA_CMD_CIPHER:
462 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
464 case ICP_QAT_FW_LA_CMD_AUTH:
465 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
467 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
468 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
469 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
471 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
472 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
473 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
475 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
476 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
477 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
478 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
479 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
480 case ICP_QAT_FW_LA_CMD_MGF1:
481 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
482 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
483 case ICP_QAT_FW_LA_CMD_DELIMITER:
484 PMD_DRV_LOG(ERR, "Unsupported Service %u",
488 PMD_DRV_LOG(ERR, "Unsupported Service %u",
495 rte_mempool_put(internals->sess_mp, session);
500 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
501 struct rte_crypto_sym_xform *xform,
502 struct qat_session *session_private)
505 struct qat_pmd_private *internals = dev->data->dev_private;
506 struct qat_session *session = session_private;
507 struct rte_crypto_auth_xform *auth_xform = NULL;
508 struct rte_crypto_cipher_xform *cipher_xform = NULL;
509 auth_xform = qat_get_auth_xform(xform);
511 switch (auth_xform->algo) {
512 case RTE_CRYPTO_AUTH_SHA1_HMAC:
513 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
515 case RTE_CRYPTO_AUTH_SHA256_HMAC:
516 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
518 case RTE_CRYPTO_AUTH_SHA512_HMAC:
519 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
521 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
522 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
524 case RTE_CRYPTO_AUTH_AES_GCM:
525 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
527 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
528 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
530 case RTE_CRYPTO_AUTH_NULL:
531 case RTE_CRYPTO_AUTH_SHA1:
532 case RTE_CRYPTO_AUTH_SHA256:
533 case RTE_CRYPTO_AUTH_SHA512:
534 case RTE_CRYPTO_AUTH_SHA224:
535 case RTE_CRYPTO_AUTH_SHA224_HMAC:
536 case RTE_CRYPTO_AUTH_SHA384:
537 case RTE_CRYPTO_AUTH_SHA384_HMAC:
538 case RTE_CRYPTO_AUTH_MD5:
539 case RTE_CRYPTO_AUTH_MD5_HMAC:
540 case RTE_CRYPTO_AUTH_AES_CCM:
541 case RTE_CRYPTO_AUTH_AES_GMAC:
542 case RTE_CRYPTO_AUTH_KASUMI_F9:
543 case RTE_CRYPTO_AUTH_AES_CMAC:
544 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
545 case RTE_CRYPTO_AUTH_ZUC_EIA3:
546 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
550 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
554 cipher_xform = qat_get_cipher_xform(xform);
556 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
557 (session->qat_hash_alg ==
558 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
559 if (qat_alg_aead_session_create_content_desc_auth(session,
560 cipher_xform->key.data,
561 cipher_xform->key.length,
562 auth_xform->add_auth_data_length,
563 auth_xform->digest_length,
567 if (qat_alg_aead_session_create_content_desc_auth(session,
568 auth_xform->key.data,
569 auth_xform->key.length,
570 auth_xform->add_auth_data_length,
571 auth_xform->digest_length,
578 rte_mempool_put(internals->sess_mp, session);
582 unsigned qat_crypto_sym_get_session_private_size(
583 struct rte_cryptodev *dev __rte_unused)
585 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
590 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
593 register struct qat_queue *queue;
594 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
595 register uint32_t nb_ops_sent = 0;
596 register struct rte_crypto_op **cur_op = ops;
598 uint16_t nb_ops_possible = nb_ops;
599 register uint8_t *base_addr;
600 register uint32_t tail;
603 if (unlikely(nb_ops == 0))
606 /* read params used a lot in main loop into registers */
607 queue = &(tmp_qp->tx_q);
608 base_addr = (uint8_t *)queue->base_addr;
611 /* Find how many can actually fit on the ring */
612 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
613 - queue->max_inflights;
615 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
616 nb_ops_possible = nb_ops - overflow;
617 if (nb_ops_possible == 0)
621 while (nb_ops_sent != nb_ops_possible) {
622 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
624 tmp_qp->stats.enqueue_err_count++;
625 if (nb_ops_sent == 0)
630 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
635 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
636 queue->hw_queue_number, tail);
638 tmp_qp->stats.enqueued_count += nb_ops_sent;
643 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
646 struct qat_queue *queue;
647 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
648 uint32_t msg_counter = 0;
649 struct rte_crypto_op *rx_op;
650 struct icp_qat_fw_comn_resp *resp_msg;
652 queue = &(tmp_qp->rx_q);
653 resp_msg = (struct icp_qat_fw_comn_resp *)
654 ((uint8_t *)queue->base_addr + queue->head);
656 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
657 msg_counter != nb_ops) {
658 rx_op = (struct rte_crypto_op *)(uintptr_t)
659 (resp_msg->opaque_data);
661 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
662 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
663 sizeof(struct icp_qat_fw_comn_resp));
665 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
666 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
667 resp_msg->comn_hdr.comn_status)) {
668 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
670 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
672 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
673 queue->head = adf_modulo(queue->head +
675 ADF_RING_SIZE_MODULO(queue->queue_size));
676 resp_msg = (struct icp_qat_fw_comn_resp *)
677 ((uint8_t *)queue->base_addr +
683 if (msg_counter > 0) {
684 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
685 queue->hw_bundle_number,
686 queue->hw_queue_number, queue->head);
687 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
688 tmp_qp->stats.dequeued_count += msg_counter;
694 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
696 struct qat_session *ctx;
697 struct icp_qat_fw_la_cipher_req_params *cipher_param;
698 struct icp_qat_fw_la_auth_req_params *auth_param;
699 register struct icp_qat_fw_la_bulk_req *qat_req;
701 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
702 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
703 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
704 "operation requests, op (%p) is not a "
705 "symmetric operation.", op);
709 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
710 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
711 " requests, op (%p) is sessionless.", op);
715 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
716 PMD_DRV_LOG(ERR, "Session was not created for this device");
720 ctx = (struct qat_session *)op->sym->session->_private;
721 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
722 *qat_req = ctx->fw_req;
723 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
725 qat_req->comn_mid.dst_length =
726 qat_req->comn_mid.src_length =
727 rte_pktmbuf_data_len(op->sym->m_src);
729 qat_req->comn_mid.dest_data_addr =
730 qat_req->comn_mid.src_data_addr =
731 rte_pktmbuf_mtophys(op->sym->m_src);
733 if (unlikely(op->sym->m_dst != NULL)) {
734 qat_req->comn_mid.dest_data_addr =
735 rte_pktmbuf_mtophys(op->sym->m_dst);
736 qat_req->comn_mid.dst_length =
737 rte_pktmbuf_data_len(op->sym->m_dst);
740 cipher_param = (void *)&qat_req->serv_specif_rqpars;
741 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
743 cipher_param->cipher_length = op->sym->cipher.data.length;
744 cipher_param->cipher_offset = op->sym->cipher.data.offset;
745 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
746 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
747 (cipher_param->cipher_offset
748 % BYTE_LENGTH != 0))) {
749 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
750 "supports byte aligned values");
751 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
754 cipher_param->cipher_length >>= 3;
755 cipher_param->cipher_offset >>= 3;
758 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
759 sizeof(cipher_param->u.cipher_IV_array))) {
760 rte_memcpy(cipher_param->u.cipher_IV_array,
761 op->sym->cipher.iv.data,
762 op->sym->cipher.iv.length);
764 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
765 qat_req->comn_hdr.serv_specif_flags,
766 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
767 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
769 if (op->sym->auth.digest.phys_addr) {
770 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
771 qat_req->comn_hdr.serv_specif_flags,
772 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
773 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
775 auth_param->auth_off = op->sym->auth.data.offset;
776 auth_param->auth_len = op->sym->auth.data.length;
777 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
778 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
779 (auth_param->auth_len % BYTE_LENGTH != 0))) {
780 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
781 "supports byte aligned values");
782 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
785 auth_param->auth_off >>= 3;
786 auth_param->auth_len >>= 3;
788 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
789 /* (GCM) aad length(240 max) will be at this location after precompute */
790 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
791 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
792 struct icp_qat_hw_auth_algo_blk *hash;
794 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER)
795 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd);
797 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd +
798 sizeof(struct icp_qat_hw_cipher_algo_blk));
800 auth_param->u2.aad_sz = ALIGN_POW2_ROUNDUP(hash->sha.state1[
801 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
802 ICP_QAT_HW_GALOIS_H_SZ + 3], 16);
803 if (op->sym->cipher.iv.length == 12) {
805 * For GCM a 12 bit IV is allowed,
806 * but we need to inform the f/w
808 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
809 qat_req->comn_hdr.serv_specif_flags,
810 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
813 auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
816 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
817 rte_hexdump(stdout, "qat_req:", qat_req,
818 sizeof(struct icp_qat_fw_la_bulk_req));
819 rte_hexdump(stdout, "src_data:",
820 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
821 rte_pktmbuf_data_len(op->sym->m_src));
822 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
823 op->sym->cipher.iv.length);
824 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
825 op->sym->auth.digest.length);
826 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
827 op->sym->auth.aad.length);
832 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
834 uint32_t div = data >> shift;
835 uint32_t mult = div << shift;
840 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
842 struct rte_cryptodev_sym_session *sess = sym_sess;
843 struct qat_session *s = (void *)sess->_private;
845 PMD_INIT_FUNC_TRACE();
846 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
847 offsetof(struct qat_session, cd) +
848 offsetof(struct rte_cryptodev_sym_session, _private);
851 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
853 PMD_INIT_FUNC_TRACE();
857 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
859 PMD_INIT_FUNC_TRACE();
863 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
865 PMD_INIT_FUNC_TRACE();
868 int qat_dev_close(struct rte_cryptodev *dev)
872 PMD_INIT_FUNC_TRACE();
874 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
875 ret = qat_crypto_sym_qp_release(dev, i);
883 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
884 struct rte_cryptodev_info *info)
886 struct qat_pmd_private *internals = dev->data->dev_private;
888 PMD_INIT_FUNC_TRACE();
890 info->max_nb_queue_pairs =
891 ADF_NUM_SYM_QPS_PER_BUNDLE *
892 ADF_NUM_BUNDLES_PER_DEV;
893 info->feature_flags = dev->feature_flags;
894 info->capabilities = qat_pmd_capabilities;
895 info->sym.max_nb_sessions = internals->max_nb_sessions;
896 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
900 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
901 struct rte_cryptodev_stats *stats)
904 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
906 PMD_INIT_FUNC_TRACE();
908 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
911 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
913 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
917 stats->enqueued_count += qp[i]->stats.enqueued_count;
918 stats->dequeued_count += qp[i]->stats.enqueued_count;
919 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
920 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
924 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
927 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
929 PMD_INIT_FUNC_TRACE();
930 for (i = 0; i < dev->data->nb_queue_pairs; i++)
931 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
932 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");