4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <rte_cryptodev_pci.h>
64 #include <openssl/evp.h>
68 #include "qat_crypto.h"
69 #include "adf_transport_access_macros.h"
74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
75 struct qat_pmd_private *internals) {
77 const struct rte_cryptodev_capabilities *capability;
79 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
80 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
81 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
84 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
87 if (capability->sym.cipher.algo == algo)
94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
95 struct qat_pmd_private *internals) {
97 const struct rte_cryptodev_capabilities *capability;
99 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
100 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
101 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
104 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
107 if (capability->sym.auth.algo == algo)
113 /** Encrypt a single partial block
114 * Depends on openssl libcrypto
115 * Uses ECB+XOR to do CFB encryption, same result, more performant
118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
119 uint8_t *iv, int ivlen, int srclen,
122 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
124 uint8_t encrypted_iv[16];
127 /* ECB method: encrypt the IV, then XOR this with plaintext */
128 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
130 goto cipher_encrypt_err;
132 for (i = 0; i < srclen; i++)
133 *(dst+i) = *(src+i)^(encrypted_iv[i]);
138 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
142 /** Decrypt a single partial block
143 * Depends on openssl libcrypto
144 * Uses ECB+XOR to do CFB encryption, same result, more performant
147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
148 uint8_t *iv, int ivlen, int srclen,
151 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
153 uint8_t encrypted_iv[16];
156 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
157 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
159 goto cipher_decrypt_err;
161 for (i = 0; i < srclen; i++)
162 *(dst+i) = *(src+i)^(encrypted_iv[i]);
167 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
171 /** Creates a context in either AES or DES in ECB mode
172 * Depends on openssl libcrypto
175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
176 enum rte_crypto_cipher_operation direction __rte_unused,
179 const EVP_CIPHER *algo = NULL;
180 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
185 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
186 algo = EVP_des_ecb();
188 algo = EVP_aes_128_ecb();
190 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
191 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
198 EVP_CIPHER_CTX_free(ctx);
202 /** Frees a context previously created
203 * Depends on openssl libcrypto
206 bpi_cipher_ctx_free(void *bpi_ctx)
209 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
212 static inline uint32_t
213 adf_modulo(uint32_t data, uint32_t shift);
216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
217 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
220 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
221 struct rte_cryptodev_sym_session *sess)
223 PMD_INIT_FUNC_TRACE();
224 uint8_t index = dev->driver_id;
225 void *sess_priv = get_session_private_data(sess, index);
226 struct qat_session *s = (struct qat_session *)sess_priv;
230 bpi_cipher_ctx_free(s->bpi_ctx);
231 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
232 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
233 set_session_private_data(sess, index, NULL);
234 rte_mempool_put(sess_mp, sess_priv);
239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
242 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
243 return ICP_QAT_FW_LA_CMD_CIPHER;
245 /* Authentication Only */
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
247 return ICP_QAT_FW_LA_CMD_AUTH;
250 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
251 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
252 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
254 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
257 if (xform->next == NULL)
260 /* Cipher then Authenticate */
261 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
262 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
263 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
265 /* Authenticate then Cipher */
266 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
267 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
268 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
273 static struct rte_crypto_auth_xform *
274 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
277 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
286 static struct rte_crypto_cipher_xform *
287 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
290 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
291 return &xform->cipher;
300 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
301 struct rte_crypto_sym_xform *xform,
302 struct qat_session *session)
304 struct qat_pmd_private *internals = dev->data->dev_private;
305 struct rte_crypto_cipher_xform *cipher_xform = NULL;
307 /* Get cipher xform from crypto xform chain */
308 cipher_xform = qat_get_cipher_xform(xform);
310 session->cipher_iv.offset = cipher_xform->iv.offset;
311 session->cipher_iv.length = cipher_xform->iv.length;
313 switch (cipher_xform->algo) {
314 case RTE_CRYPTO_CIPHER_AES_CBC:
315 if (qat_alg_validate_aes_key(cipher_xform->key.length,
316 &session->qat_cipher_alg) != 0) {
317 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
320 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
322 case RTE_CRYPTO_CIPHER_AES_CTR:
323 if (qat_alg_validate_aes_key(cipher_xform->key.length,
324 &session->qat_cipher_alg) != 0) {
325 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
328 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
330 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
331 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
332 &session->qat_cipher_alg) != 0) {
333 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
336 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
338 case RTE_CRYPTO_CIPHER_NULL:
339 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
341 case RTE_CRYPTO_CIPHER_KASUMI_F8:
342 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
343 &session->qat_cipher_alg) != 0) {
344 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
347 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
349 case RTE_CRYPTO_CIPHER_3DES_CBC:
350 if (qat_alg_validate_3des_key(cipher_xform->key.length,
351 &session->qat_cipher_alg) != 0) {
352 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
355 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
357 case RTE_CRYPTO_CIPHER_DES_CBC:
358 if (qat_alg_validate_des_key(cipher_xform->key.length,
359 &session->qat_cipher_alg) != 0) {
360 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
363 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
365 case RTE_CRYPTO_CIPHER_3DES_CTR:
366 if (qat_alg_validate_3des_key(cipher_xform->key.length,
367 &session->qat_cipher_alg) != 0) {
368 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
371 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
373 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
374 session->bpi_ctx = bpi_cipher_ctx_init(
377 cipher_xform->key.data);
378 if (session->bpi_ctx == NULL) {
379 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
382 if (qat_alg_validate_des_key(cipher_xform->key.length,
383 &session->qat_cipher_alg) != 0) {
384 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
387 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
389 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
390 session->bpi_ctx = bpi_cipher_ctx_init(
393 cipher_xform->key.data);
394 if (session->bpi_ctx == NULL) {
395 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
398 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
399 &session->qat_cipher_alg) != 0) {
400 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
403 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
405 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
406 if (!qat_is_cipher_alg_supported(
407 cipher_xform->algo, internals)) {
408 PMD_DRV_LOG(ERR, "%s not supported on this device",
409 rte_crypto_cipher_algorithm_strings
410 [cipher_xform->algo]);
413 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
414 &session->qat_cipher_alg) != 0) {
415 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
418 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
420 case RTE_CRYPTO_CIPHER_3DES_ECB:
421 case RTE_CRYPTO_CIPHER_AES_ECB:
422 case RTE_CRYPTO_CIPHER_AES_F8:
423 case RTE_CRYPTO_CIPHER_AES_XTS:
424 case RTE_CRYPTO_CIPHER_ARC4:
425 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
429 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
434 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
435 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
437 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
439 if (qat_alg_aead_session_create_content_desc_cipher(session,
440 cipher_xform->key.data,
441 cipher_xform->key.length))
447 if (session->bpi_ctx) {
448 bpi_cipher_ctx_free(session->bpi_ctx);
449 session->bpi_ctx = NULL;
455 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
456 struct rte_crypto_sym_xform *xform,
457 struct rte_cryptodev_sym_session *sess,
458 struct rte_mempool *mempool)
460 void *sess_private_data;
462 if (rte_mempool_get(mempool, &sess_private_data)) {
464 "Couldn't get object from session mempool");
468 if (qat_crypto_set_session_parameters(dev, xform, sess_private_data) != 0) {
469 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
470 "session parameters");
472 /* Return session to mempool */
473 rte_mempool_put(mempool, sess_private_data);
477 set_session_private_data(sess, dev->driver_id,
484 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
485 struct rte_crypto_sym_xform *xform, void *session_private)
487 struct qat_session *session = session_private;
490 PMD_INIT_FUNC_TRACE();
492 /* Set context descriptor physical address */
493 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
494 offsetof(struct qat_session, cd);
496 session->min_qat_dev_gen = QAT_GEN1;
498 /* Get requested QAT command id */
499 qat_cmd_id = qat_get_cmd_id(xform);
500 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
501 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
504 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
505 switch (session->qat_cmd) {
506 case ICP_QAT_FW_LA_CMD_CIPHER:
507 if (qat_crypto_sym_configure_session_cipher(dev, xform, session) < 0)
510 case ICP_QAT_FW_LA_CMD_AUTH:
511 if (qat_crypto_sym_configure_session_auth(dev, xform, session) < 0)
514 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
515 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
516 if (qat_crypto_sym_configure_session_aead(xform,
520 if (qat_crypto_sym_configure_session_cipher(dev,
523 if (qat_crypto_sym_configure_session_auth(dev,
528 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
529 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
530 if (qat_crypto_sym_configure_session_aead(xform,
534 if (qat_crypto_sym_configure_session_auth(dev,
537 if (qat_crypto_sym_configure_session_cipher(dev,
542 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
543 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
544 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
545 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
546 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
547 case ICP_QAT_FW_LA_CMD_MGF1:
548 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
549 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
550 case ICP_QAT_FW_LA_CMD_DELIMITER:
551 PMD_DRV_LOG(ERR, "Unsupported Service %u",
555 PMD_DRV_LOG(ERR, "Unsupported Service %u",
564 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
565 struct rte_crypto_sym_xform *xform,
566 struct qat_session *session)
568 struct rte_crypto_auth_xform *auth_xform = NULL;
569 struct qat_pmd_private *internals = dev->data->dev_private;
570 auth_xform = qat_get_auth_xform(xform);
571 uint8_t *key_data = auth_xform->key.data;
572 uint8_t key_length = auth_xform->key.length;
574 switch (auth_xform->algo) {
575 case RTE_CRYPTO_AUTH_SHA1_HMAC:
576 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
578 case RTE_CRYPTO_AUTH_SHA224_HMAC:
579 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
581 case RTE_CRYPTO_AUTH_SHA256_HMAC:
582 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
584 case RTE_CRYPTO_AUTH_SHA384_HMAC:
585 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
587 case RTE_CRYPTO_AUTH_SHA512_HMAC:
588 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
590 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
591 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
593 case RTE_CRYPTO_AUTH_AES_GMAC:
594 if (qat_alg_validate_aes_key(auth_xform->key.length,
595 &session->qat_cipher_alg) != 0) {
596 PMD_DRV_LOG(ERR, "Invalid AES key size");
599 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
600 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
603 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
604 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
606 case RTE_CRYPTO_AUTH_MD5_HMAC:
607 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
609 case RTE_CRYPTO_AUTH_NULL:
610 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
612 case RTE_CRYPTO_AUTH_KASUMI_F9:
613 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
615 case RTE_CRYPTO_AUTH_ZUC_EIA3:
616 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
617 PMD_DRV_LOG(ERR, "%s not supported on this device",
618 rte_crypto_auth_algorithm_strings
622 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
624 case RTE_CRYPTO_AUTH_SHA1:
625 case RTE_CRYPTO_AUTH_SHA256:
626 case RTE_CRYPTO_AUTH_SHA512:
627 case RTE_CRYPTO_AUTH_SHA224:
628 case RTE_CRYPTO_AUTH_SHA384:
629 case RTE_CRYPTO_AUTH_MD5:
630 case RTE_CRYPTO_AUTH_AES_CMAC:
631 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
632 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
636 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
641 session->auth_iv.offset = auth_xform->iv.offset;
642 session->auth_iv.length = auth_xform->iv.length;
644 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
645 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
646 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
647 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
649 * It needs to create cipher desc content first,
650 * then authentication
652 if (qat_alg_aead_session_create_content_desc_cipher(session,
653 auth_xform->key.data,
654 auth_xform->key.length))
657 if (qat_alg_aead_session_create_content_desc_auth(session,
661 auth_xform->digest_length,
665 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
666 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
668 * It needs to create authentication desc content first,
671 if (qat_alg_aead_session_create_content_desc_auth(session,
675 auth_xform->digest_length,
679 if (qat_alg_aead_session_create_content_desc_cipher(session,
680 auth_xform->key.data,
681 auth_xform->key.length))
684 /* Restore to authentication only only */
685 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
687 if (qat_alg_aead_session_create_content_desc_auth(session,
691 auth_xform->digest_length,
696 session->digest_length = auth_xform->digest_length;
704 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
705 struct qat_session *session)
707 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
710 * Store AEAD IV parameters as cipher IV,
711 * to avoid unnecessary memory usage
713 session->cipher_iv.offset = xform->aead.iv.offset;
714 session->cipher_iv.length = xform->aead.iv.length;
716 switch (aead_xform->algo) {
717 case RTE_CRYPTO_AEAD_AES_GCM:
718 if (qat_alg_validate_aes_key(aead_xform->key.length,
719 &session->qat_cipher_alg) != 0) {
720 PMD_DRV_LOG(ERR, "Invalid AES key size");
723 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
724 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
726 case RTE_CRYPTO_AEAD_AES_CCM:
727 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
731 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
736 if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
737 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
739 * It needs to create cipher desc content first,
740 * then authentication
742 if (qat_alg_aead_session_create_content_desc_cipher(session,
743 aead_xform->key.data,
744 aead_xform->key.length))
747 if (qat_alg_aead_session_create_content_desc_auth(session,
748 aead_xform->key.data,
749 aead_xform->key.length,
750 aead_xform->aad_length,
751 aead_xform->digest_length,
752 RTE_CRYPTO_AUTH_OP_GENERATE))
755 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
757 * It needs to create authentication desc content first,
760 if (qat_alg_aead_session_create_content_desc_auth(session,
761 aead_xform->key.data,
762 aead_xform->key.length,
763 aead_xform->aad_length,
764 aead_xform->digest_length,
765 RTE_CRYPTO_AUTH_OP_VERIFY))
768 if (qat_alg_aead_session_create_content_desc_cipher(session,
769 aead_xform->key.data,
770 aead_xform->key.length))
774 session->digest_length = aead_xform->digest_length;
781 unsigned qat_crypto_sym_get_session_private_size(
782 struct rte_cryptodev *dev __rte_unused)
784 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
787 static inline uint32_t
788 qat_bpicipher_preprocess(struct qat_session *ctx,
789 struct rte_crypto_op *op)
791 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
792 struct rte_crypto_sym_op *sym_op = op->sym;
793 uint8_t last_block_len = block_len > 0 ?
794 sym_op->cipher.data.length % block_len : 0;
796 if (last_block_len &&
797 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
799 /* Decrypt last block */
800 uint8_t *last_block, *dst, *iv;
801 uint32_t last_block_offset = sym_op->cipher.data.offset +
802 sym_op->cipher.data.length - last_block_len;
803 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
804 uint8_t *, last_block_offset);
806 if (unlikely(sym_op->m_dst != NULL))
807 /* out-of-place operation (OOP) */
808 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
809 uint8_t *, last_block_offset);
813 if (last_block_len < sym_op->cipher.data.length)
814 /* use previous block ciphertext as IV */
815 iv = last_block - block_len;
817 /* runt block, i.e. less than one full block */
818 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
819 ctx->cipher_iv.offset);
821 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
822 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
824 if (sym_op->m_dst != NULL)
825 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
828 bpi_cipher_decrypt(last_block, dst, iv, block_len,
829 last_block_len, ctx->bpi_ctx);
830 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
831 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
833 if (sym_op->m_dst != NULL)
834 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
839 return sym_op->cipher.data.length - last_block_len;
842 static inline uint32_t
843 qat_bpicipher_postprocess(struct qat_session *ctx,
844 struct rte_crypto_op *op)
846 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
847 struct rte_crypto_sym_op *sym_op = op->sym;
848 uint8_t last_block_len = block_len > 0 ?
849 sym_op->cipher.data.length % block_len : 0;
851 if (last_block_len > 0 &&
852 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
854 /* Encrypt last block */
855 uint8_t *last_block, *dst, *iv;
856 uint32_t last_block_offset;
858 last_block_offset = sym_op->cipher.data.offset +
859 sym_op->cipher.data.length - last_block_len;
860 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
861 uint8_t *, last_block_offset);
863 if (unlikely(sym_op->m_dst != NULL))
864 /* out-of-place operation (OOP) */
865 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
866 uint8_t *, last_block_offset);
870 if (last_block_len < sym_op->cipher.data.length)
871 /* use previous block ciphertext as IV */
872 iv = dst - block_len;
874 /* runt block, i.e. less than one full block */
875 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
876 ctx->cipher_iv.offset);
878 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
879 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
881 if (sym_op->m_dst != NULL)
882 rte_hexdump(stdout, "BPI: dst before post-process:",
883 dst, last_block_len);
885 bpi_cipher_encrypt(last_block, dst, iv, block_len,
886 last_block_len, ctx->bpi_ctx);
887 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
888 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
890 if (sym_op->m_dst != NULL)
891 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
895 return sym_op->cipher.data.length - last_block_len;
899 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
902 register struct qat_queue *queue;
903 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
904 register uint32_t nb_ops_sent = 0;
905 register struct rte_crypto_op **cur_op = ops;
907 uint16_t nb_ops_possible = nb_ops;
908 register uint8_t *base_addr;
909 register uint32_t tail;
912 if (unlikely(nb_ops == 0))
915 /* read params used a lot in main loop into registers */
916 queue = &(tmp_qp->tx_q);
917 base_addr = (uint8_t *)queue->base_addr;
920 /* Find how many can actually fit on the ring */
921 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
922 - queue->max_inflights;
924 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
925 nb_ops_possible = nb_ops - overflow;
926 if (nb_ops_possible == 0)
930 while (nb_ops_sent != nb_ops_possible) {
931 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
932 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
934 tmp_qp->stats.enqueue_err_count++;
936 * This message cannot be enqueued,
937 * decrease number of ops that wasn't sent
939 rte_atomic16_sub(&tmp_qp->inflights16,
940 nb_ops_possible - nb_ops_sent);
941 if (nb_ops_sent == 0)
946 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
951 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
952 queue->hw_queue_number, tail);
954 tmp_qp->stats.enqueued_count += nb_ops_sent;
959 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
962 struct qat_queue *queue;
963 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
964 uint32_t msg_counter = 0;
965 struct rte_crypto_op *rx_op;
966 struct icp_qat_fw_comn_resp *resp_msg;
968 queue = &(tmp_qp->rx_q);
969 resp_msg = (struct icp_qat_fw_comn_resp *)
970 ((uint8_t *)queue->base_addr + queue->head);
972 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
973 msg_counter != nb_ops) {
974 rx_op = (struct rte_crypto_op *)(uintptr_t)
975 (resp_msg->opaque_data);
977 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
978 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
979 sizeof(struct icp_qat_fw_comn_resp));
982 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
983 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
984 resp_msg->comn_hdr.comn_status)) {
985 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
987 struct qat_session *sess = (struct qat_session *)
988 get_session_private_data(
990 cryptodev_qat_driver_id);
993 qat_bpicipher_postprocess(sess, rx_op);
994 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
997 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
998 queue->head = adf_modulo(queue->head +
1000 ADF_RING_SIZE_MODULO(queue->queue_size));
1001 resp_msg = (struct icp_qat_fw_comn_resp *)
1002 ((uint8_t *)queue->base_addr +
1008 if (msg_counter > 0) {
1009 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
1010 queue->hw_bundle_number,
1011 queue->hw_queue_number, queue->head);
1012 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
1013 tmp_qp->stats.dequeued_count += msg_counter;
1019 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1020 struct qat_alg_buf_list *list, uint32_t data_len)
1024 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1025 buff_start + rte_pktmbuf_data_len(buf);
1027 list->bufers[0].addr = buff_start;
1028 list->bufers[0].resrvd = 0;
1029 list->bufers[0].len = buf_len;
1031 if (data_len <= buf_len) {
1032 list->num_bufs = nr;
1033 list->bufers[0].len = data_len;
1039 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1040 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1042 QAT_SGL_MAX_NUMBER);
1046 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1047 list->bufers[nr].resrvd = 0;
1048 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1050 buf_len += list->bufers[nr].len;
1053 if (buf_len > data_len) {
1054 list->bufers[nr].len -=
1060 list->num_bufs = nr;
1066 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1067 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1068 struct rte_crypto_op *op,
1069 struct icp_qat_fw_la_bulk_req *qat_req)
1071 /* copy IV into request if it fits */
1072 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1073 rte_memcpy(cipher_param->u.cipher_IV_array,
1074 rte_crypto_op_ctod_offset(op, uint8_t *,
1078 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1079 qat_req->comn_hdr.serv_specif_flags,
1080 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1081 cipher_param->u.s.cipher_IV_ptr =
1082 rte_crypto_op_ctophys_offset(op,
1088 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1089 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1092 struct qat_session *ctx;
1093 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1094 struct icp_qat_fw_la_auth_req_params *auth_param;
1095 register struct icp_qat_fw_la_bulk_req *qat_req;
1096 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1097 uint32_t cipher_len = 0, cipher_ofs = 0;
1098 uint32_t auth_len = 0, auth_ofs = 0;
1099 uint32_t min_ofs = 0;
1100 uint64_t src_buf_start = 0, dst_buf_start = 0;
1103 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1104 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1105 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1106 "operation requests, op (%p) is not a "
1107 "symmetric operation.", op);
1111 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1112 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1113 " requests, op (%p) is sessionless.", op);
1117 ctx = (struct qat_session *)get_session_private_data(
1118 op->sym->session, cryptodev_qat_driver_id);
1120 if (unlikely(ctx == NULL)) {
1121 PMD_DRV_LOG(ERR, "Session was not created for this device");
1125 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1126 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1127 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1131 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1132 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1133 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1134 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1135 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1137 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1138 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1140 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1141 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1147 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1150 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1157 if (ctx->qat_cipher_alg ==
1158 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1159 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1160 ctx->qat_cipher_alg ==
1161 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1164 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1165 || (cipher_param->cipher_offset
1166 % BYTE_LENGTH != 0))) {
1168 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1169 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1172 cipher_len = op->sym->cipher.data.length >> 3;
1173 cipher_ofs = op->sym->cipher.data.offset >> 3;
1175 } else if (ctx->bpi_ctx) {
1176 /* DOCSIS - only send complete blocks to device
1177 * Process any partial block using CFB mode.
1178 * Even if 0 complete blocks, still send this to device
1179 * to get into rx queue for post-process and dequeuing
1181 cipher_len = qat_bpicipher_preprocess(ctx, op);
1182 cipher_ofs = op->sym->cipher.data.offset;
1184 cipher_len = op->sym->cipher.data.length;
1185 cipher_ofs = op->sym->cipher.data.offset;
1188 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1189 cipher_param, op, qat_req);
1190 min_ofs = cipher_ofs;
1195 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1196 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1197 ctx->qat_hash_alg ==
1198 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1199 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1200 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1202 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1203 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1206 auth_ofs = op->sym->auth.data.offset >> 3;
1207 auth_len = op->sym->auth.data.length >> 3;
1209 auth_param->u1.aad_adr =
1210 rte_crypto_op_ctophys_offset(op,
1211 ctx->auth_iv.offset);
1213 } else if (ctx->qat_hash_alg ==
1214 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1215 ctx->qat_hash_alg ==
1216 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1218 set_cipher_iv(ctx->auth_iv.length,
1219 ctx->auth_iv.offset,
1220 cipher_param, op, qat_req);
1221 auth_ofs = op->sym->auth.data.offset;
1222 auth_len = op->sym->auth.data.length;
1224 auth_param->u1.aad_adr = 0;
1225 auth_param->u2.aad_sz = 0;
1228 * If len(iv)==12B fw computes J0
1230 if (ctx->auth_iv.length == 12) {
1231 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1232 qat_req->comn_hdr.serv_specif_flags,
1233 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1237 auth_ofs = op->sym->auth.data.offset;
1238 auth_len = op->sym->auth.data.length;
1243 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1248 if (ctx->qat_hash_alg ==
1249 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1250 ctx->qat_hash_alg ==
1251 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1253 * If len(iv)==12B fw computes J0
1255 if (ctx->cipher_iv.length == 12) {
1256 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1257 qat_req->comn_hdr.serv_specif_flags,
1258 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1263 cipher_len = op->sym->aead.data.length;
1264 cipher_ofs = op->sym->aead.data.offset;
1265 auth_len = op->sym->aead.data.length;
1266 auth_ofs = op->sym->aead.data.offset;
1268 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1269 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1270 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1271 cipher_param, op, qat_req);
1272 min_ofs = op->sym->aead.data.offset;
1275 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1278 /* adjust for chain case */
1279 if (do_cipher && do_auth)
1280 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1282 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1285 if (unlikely(op->sym->m_dst != NULL)) {
1286 /* Out-of-place operation (OOP)
1287 * Don't align DMA start. DMA the minimum data-set
1288 * so as not to overwrite data in dest buffer
1291 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1293 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1296 /* In-place operation
1297 * Start DMA at nearest aligned address below min_ofs
1300 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1301 & QAT_64_BTYE_ALIGN_MASK;
1303 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1304 rte_pktmbuf_headroom(op->sym->m_src))
1306 /* alignment has pushed addr ahead of start of mbuf
1307 * so revert and take the performance hit
1310 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1313 dst_buf_start = src_buf_start;
1316 if (do_cipher || do_aead) {
1317 cipher_param->cipher_offset =
1318 (uint32_t)rte_pktmbuf_mtophys_offset(
1319 op->sym->m_src, cipher_ofs) - src_buf_start;
1320 cipher_param->cipher_length = cipher_len;
1322 cipher_param->cipher_offset = 0;
1323 cipher_param->cipher_length = 0;
1326 if (do_auth || do_aead) {
1327 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1328 op->sym->m_src, auth_ofs) - src_buf_start;
1329 auth_param->auth_len = auth_len;
1331 auth_param->auth_off = 0;
1332 auth_param->auth_len = 0;
1335 qat_req->comn_mid.dst_length =
1336 qat_req->comn_mid.src_length =
1337 (cipher_param->cipher_offset + cipher_param->cipher_length)
1338 > (auth_param->auth_off + auth_param->auth_len) ?
1339 (cipher_param->cipher_offset + cipher_param->cipher_length)
1340 : (auth_param->auth_off + auth_param->auth_len);
1344 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1345 QAT_COMN_PTR_TYPE_SGL);
1346 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1347 &qat_op_cookie->qat_sgl_list_src,
1348 qat_req->comn_mid.src_length);
1350 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1354 if (likely(op->sym->m_dst == NULL))
1355 qat_req->comn_mid.dest_data_addr =
1356 qat_req->comn_mid.src_data_addr =
1357 qat_op_cookie->qat_sgl_src_phys_addr;
1359 ret = qat_sgl_fill_array(op->sym->m_dst,
1361 &qat_op_cookie->qat_sgl_list_dst,
1362 qat_req->comn_mid.dst_length);
1365 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1370 qat_req->comn_mid.src_data_addr =
1371 qat_op_cookie->qat_sgl_src_phys_addr;
1372 qat_req->comn_mid.dest_data_addr =
1373 qat_op_cookie->qat_sgl_dst_phys_addr;
1376 qat_req->comn_mid.src_data_addr = src_buf_start;
1377 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1380 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1381 rte_hexdump(stdout, "qat_req:", qat_req,
1382 sizeof(struct icp_qat_fw_la_bulk_req));
1383 rte_hexdump(stdout, "src_data:",
1384 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1385 rte_pktmbuf_data_len(op->sym->m_src));
1387 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1389 ctx->cipher_iv.offset);
1390 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1391 ctx->cipher_iv.length);
1395 if (ctx->auth_iv.length) {
1396 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1398 ctx->auth_iv.offset);
1399 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1400 ctx->auth_iv.length);
1402 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1403 ctx->digest_length);
1407 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1408 ctx->digest_length);
1409 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1416 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1418 uint32_t div = data >> shift;
1419 uint32_t mult = div << shift;
1424 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1425 __rte_unused struct rte_cryptodev_config *config)
1427 PMD_INIT_FUNC_TRACE();
1431 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1433 PMD_INIT_FUNC_TRACE();
1437 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1439 PMD_INIT_FUNC_TRACE();
1442 int qat_dev_close(struct rte_cryptodev *dev)
1446 PMD_INIT_FUNC_TRACE();
1448 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1449 ret = qat_crypto_sym_qp_release(dev, i);
1457 void qat_dev_info_get(struct rte_cryptodev *dev,
1458 struct rte_cryptodev_info *info)
1460 struct qat_pmd_private *internals = dev->data->dev_private;
1462 PMD_INIT_FUNC_TRACE();
1464 info->max_nb_queue_pairs =
1465 ADF_NUM_SYM_QPS_PER_BUNDLE *
1466 ADF_NUM_BUNDLES_PER_DEV;
1467 info->feature_flags = dev->feature_flags;
1468 info->capabilities = internals->qat_dev_capabilities;
1469 info->sym.max_nb_sessions = internals->max_nb_sessions;
1470 info->driver_id = cryptodev_qat_driver_id;
1471 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1475 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1476 struct rte_cryptodev_stats *stats)
1479 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1481 PMD_INIT_FUNC_TRACE();
1482 if (stats == NULL) {
1483 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1486 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1487 if (qp[i] == NULL) {
1488 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1492 stats->enqueued_count += qp[i]->stats.enqueued_count;
1493 stats->dequeued_count += qp[i]->stats.dequeued_count;
1494 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1495 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1499 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1502 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1504 PMD_INIT_FUNC_TRACE();
1505 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1506 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1507 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");