4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <rte_cryptodev_pci.h>
64 #include <openssl/evp.h>
68 #include "qat_crypto.h"
69 #include "adf_transport_access_macros.h"
74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
75 struct qat_pmd_private *internals) {
77 const struct rte_cryptodev_capabilities *capability;
79 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
80 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
81 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
84 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
87 if (capability->sym.cipher.algo == algo)
94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
95 struct qat_pmd_private *internals) {
97 const struct rte_cryptodev_capabilities *capability;
99 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
100 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
101 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
104 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
107 if (capability->sym.auth.algo == algo)
113 /** Encrypt a single partial block
114 * Depends on openssl libcrypto
115 * Uses ECB+XOR to do CFB encryption, same result, more performant
118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
119 uint8_t *iv, int ivlen, int srclen,
122 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
124 uint8_t encrypted_iv[16];
127 /* ECB method: encrypt the IV, then XOR this with plaintext */
128 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
130 goto cipher_encrypt_err;
132 for (i = 0; i < srclen; i++)
133 *(dst+i) = *(src+i)^(encrypted_iv[i]);
138 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
142 /** Decrypt a single partial block
143 * Depends on openssl libcrypto
144 * Uses ECB+XOR to do CFB encryption, same result, more performant
147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
148 uint8_t *iv, int ivlen, int srclen,
151 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
153 uint8_t encrypted_iv[16];
156 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
157 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
159 goto cipher_decrypt_err;
161 for (i = 0; i < srclen; i++)
162 *(dst+i) = *(src+i)^(encrypted_iv[i]);
167 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
171 /** Creates a context in either AES or DES in ECB mode
172 * Depends on openssl libcrypto
175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
176 enum rte_crypto_cipher_operation direction __rte_unused,
179 const EVP_CIPHER *algo = NULL;
180 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
185 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
186 algo = EVP_des_ecb();
188 algo = EVP_aes_128_ecb();
190 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
191 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
198 EVP_CIPHER_CTX_free(ctx);
202 /** Frees a context previously created
203 * Depends on openssl libcrypto
206 bpi_cipher_ctx_free(void *bpi_ctx)
209 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
212 static inline uint32_t
213 adf_modulo(uint32_t data, uint32_t shift);
216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
217 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
220 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
221 struct rte_cryptodev_sym_session *sess)
223 PMD_INIT_FUNC_TRACE();
224 uint8_t index = dev->driver_id;
225 void *sess_priv = get_session_private_data(sess, index);
226 struct qat_session *s = (struct qat_session *)sess_priv;
230 bpi_cipher_ctx_free(s->bpi_ctx);
231 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
232 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
233 set_session_private_data(sess, index, NULL);
234 rte_mempool_put(sess_mp, sess_priv);
239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
242 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
243 return ICP_QAT_FW_LA_CMD_CIPHER;
245 /* Authentication Only */
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
247 return ICP_QAT_FW_LA_CMD_AUTH;
250 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
251 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
252 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
254 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
257 if (xform->next == NULL)
260 /* Cipher then Authenticate */
261 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
262 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
263 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
265 /* Authenticate then Cipher */
266 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
267 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
268 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
273 static struct rte_crypto_auth_xform *
274 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
277 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
286 static struct rte_crypto_cipher_xform *
287 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
290 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
291 return &xform->cipher;
299 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
300 struct rte_crypto_sym_xform *xform, void *session_private)
302 struct qat_session *session = session_private;
303 struct qat_pmd_private *internals = dev->data->dev_private;
304 struct rte_crypto_cipher_xform *cipher_xform = NULL;
306 /* Get cipher xform from crypto xform chain */
307 cipher_xform = qat_get_cipher_xform(xform);
309 session->cipher_iv.offset = cipher_xform->iv.offset;
310 session->cipher_iv.length = cipher_xform->iv.length;
312 switch (cipher_xform->algo) {
313 case RTE_CRYPTO_CIPHER_AES_CBC:
314 if (qat_alg_validate_aes_key(cipher_xform->key.length,
315 &session->qat_cipher_alg) != 0) {
316 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
319 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
321 case RTE_CRYPTO_CIPHER_AES_CTR:
322 if (qat_alg_validate_aes_key(cipher_xform->key.length,
323 &session->qat_cipher_alg) != 0) {
324 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
327 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
329 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
330 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
331 &session->qat_cipher_alg) != 0) {
332 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
335 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
337 case RTE_CRYPTO_CIPHER_NULL:
338 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
340 case RTE_CRYPTO_CIPHER_KASUMI_F8:
341 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
342 &session->qat_cipher_alg) != 0) {
343 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
346 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
348 case RTE_CRYPTO_CIPHER_3DES_CBC:
349 if (qat_alg_validate_3des_key(cipher_xform->key.length,
350 &session->qat_cipher_alg) != 0) {
351 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
354 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
356 case RTE_CRYPTO_CIPHER_DES_CBC:
357 if (qat_alg_validate_des_key(cipher_xform->key.length,
358 &session->qat_cipher_alg) != 0) {
359 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
362 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
364 case RTE_CRYPTO_CIPHER_3DES_CTR:
365 if (qat_alg_validate_3des_key(cipher_xform->key.length,
366 &session->qat_cipher_alg) != 0) {
367 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
370 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
372 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
373 session->bpi_ctx = bpi_cipher_ctx_init(
376 cipher_xform->key.data);
377 if (session->bpi_ctx == NULL) {
378 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
381 if (qat_alg_validate_des_key(cipher_xform->key.length,
382 &session->qat_cipher_alg) != 0) {
383 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
386 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
388 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
389 session->bpi_ctx = bpi_cipher_ctx_init(
392 cipher_xform->key.data);
393 if (session->bpi_ctx == NULL) {
394 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
397 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
398 &session->qat_cipher_alg) != 0) {
399 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
402 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
404 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
405 if (!qat_is_cipher_alg_supported(
406 cipher_xform->algo, internals)) {
407 PMD_DRV_LOG(ERR, "%s not supported on this device",
408 rte_crypto_cipher_algorithm_strings
409 [cipher_xform->algo]);
412 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
413 &session->qat_cipher_alg) != 0) {
414 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
417 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
419 case RTE_CRYPTO_CIPHER_3DES_ECB:
420 case RTE_CRYPTO_CIPHER_AES_ECB:
421 case RTE_CRYPTO_CIPHER_AES_F8:
422 case RTE_CRYPTO_CIPHER_AES_XTS:
423 case RTE_CRYPTO_CIPHER_ARC4:
424 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
428 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
433 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
434 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
436 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
438 if (qat_alg_aead_session_create_content_desc_cipher(session,
439 cipher_xform->key.data,
440 cipher_xform->key.length))
446 if (session->bpi_ctx) {
447 bpi_cipher_ctx_free(session->bpi_ctx);
448 session->bpi_ctx = NULL;
454 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
455 struct rte_crypto_sym_xform *xform,
456 struct rte_cryptodev_sym_session *sess,
457 struct rte_mempool *mempool)
459 void *sess_private_data;
461 if (rte_mempool_get(mempool, &sess_private_data)) {
463 "Couldn't get object from session mempool");
467 if (qat_crypto_set_session_parameters(dev, xform, sess_private_data) != 0) {
468 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
469 "session parameters");
471 /* Return session to mempool */
472 rte_mempool_put(mempool, sess_private_data);
476 set_session_private_data(sess, dev->driver_id,
483 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
484 struct rte_crypto_sym_xform *xform, void *session_private)
486 struct qat_session *session = session_private;
489 PMD_INIT_FUNC_TRACE();
491 /* Set context descriptor physical address */
492 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
493 offsetof(struct qat_session, cd);
495 session->min_qat_dev_gen = QAT_GEN1;
497 /* Get requested QAT command id */
498 qat_cmd_id = qat_get_cmd_id(xform);
499 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
500 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
503 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
504 switch (session->qat_cmd) {
505 case ICP_QAT_FW_LA_CMD_CIPHER:
506 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
508 case ICP_QAT_FW_LA_CMD_AUTH:
509 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
511 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
512 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
513 session = qat_crypto_sym_configure_session_aead(xform,
516 session = qat_crypto_sym_configure_session_cipher(dev,
518 session = qat_crypto_sym_configure_session_auth(dev,
522 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
523 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)
524 session = qat_crypto_sym_configure_session_aead(xform,
527 session = qat_crypto_sym_configure_session_auth(dev,
529 session = qat_crypto_sym_configure_session_cipher(dev,
533 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
534 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
535 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
536 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
537 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
538 case ICP_QAT_FW_LA_CMD_MGF1:
539 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
540 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
541 case ICP_QAT_FW_LA_CMD_DELIMITER:
542 PMD_DRV_LOG(ERR, "Unsupported Service %u",
546 PMD_DRV_LOG(ERR, "Unsupported Service %u",
558 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
559 struct rte_crypto_sym_xform *xform,
560 struct qat_session *session_private)
563 struct qat_session *session = session_private;
564 struct rte_crypto_auth_xform *auth_xform = NULL;
565 struct qat_pmd_private *internals = dev->data->dev_private;
566 auth_xform = qat_get_auth_xform(xform);
567 uint8_t *key_data = auth_xform->key.data;
568 uint8_t key_length = auth_xform->key.length;
570 switch (auth_xform->algo) {
571 case RTE_CRYPTO_AUTH_SHA1_HMAC:
572 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
574 case RTE_CRYPTO_AUTH_SHA224_HMAC:
575 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
577 case RTE_CRYPTO_AUTH_SHA256_HMAC:
578 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
580 case RTE_CRYPTO_AUTH_SHA384_HMAC:
581 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
583 case RTE_CRYPTO_AUTH_SHA512_HMAC:
584 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
586 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
587 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
589 case RTE_CRYPTO_AUTH_AES_GMAC:
590 if (qat_alg_validate_aes_key(auth_xform->key.length,
591 &session->qat_cipher_alg) != 0) {
592 PMD_DRV_LOG(ERR, "Invalid AES key size");
595 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
596 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
599 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
600 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
602 case RTE_CRYPTO_AUTH_MD5_HMAC:
603 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
605 case RTE_CRYPTO_AUTH_NULL:
606 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
608 case RTE_CRYPTO_AUTH_KASUMI_F9:
609 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
611 case RTE_CRYPTO_AUTH_ZUC_EIA3:
612 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
613 PMD_DRV_LOG(ERR, "%s not supported on this device",
614 rte_crypto_auth_algorithm_strings
618 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
620 case RTE_CRYPTO_AUTH_SHA1:
621 case RTE_CRYPTO_AUTH_SHA256:
622 case RTE_CRYPTO_AUTH_SHA512:
623 case RTE_CRYPTO_AUTH_SHA224:
624 case RTE_CRYPTO_AUTH_SHA384:
625 case RTE_CRYPTO_AUTH_MD5:
626 case RTE_CRYPTO_AUTH_AES_CMAC:
627 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
628 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
632 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
637 session->auth_iv.offset = auth_xform->iv.offset;
638 session->auth_iv.length = auth_xform->iv.length;
640 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
641 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
642 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
643 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
645 * It needs to create cipher desc content first,
646 * then authentication
648 if (qat_alg_aead_session_create_content_desc_cipher(session,
649 auth_xform->key.data,
650 auth_xform->key.length))
653 if (qat_alg_aead_session_create_content_desc_auth(session,
657 auth_xform->digest_length,
661 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
662 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
664 * It needs to create authentication desc content first,
667 if (qat_alg_aead_session_create_content_desc_auth(session,
671 auth_xform->digest_length,
675 if (qat_alg_aead_session_create_content_desc_cipher(session,
676 auth_xform->key.data,
677 auth_xform->key.length))
680 /* Restore to authentication only only */
681 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
683 if (qat_alg_aead_session_create_content_desc_auth(session,
687 auth_xform->digest_length,
692 session->digest_length = auth_xform->digest_length;
700 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
701 struct qat_session *session_private)
703 struct qat_session *session = session_private;
704 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
707 * Store AEAD IV parameters as cipher IV,
708 * to avoid unnecessary memory usage
710 session->cipher_iv.offset = xform->aead.iv.offset;
711 session->cipher_iv.length = xform->aead.iv.length;
713 switch (aead_xform->algo) {
714 case RTE_CRYPTO_AEAD_AES_GCM:
715 if (qat_alg_validate_aes_key(aead_xform->key.length,
716 &session->qat_cipher_alg) != 0) {
717 PMD_DRV_LOG(ERR, "Invalid AES key size");
720 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
721 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
723 case RTE_CRYPTO_AEAD_AES_CCM:
724 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
728 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
733 if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
734 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
736 * It needs to create cipher desc content first,
737 * then authentication
739 if (qat_alg_aead_session_create_content_desc_cipher(session,
740 aead_xform->key.data,
741 aead_xform->key.length))
744 if (qat_alg_aead_session_create_content_desc_auth(session,
745 aead_xform->key.data,
746 aead_xform->key.length,
747 aead_xform->aad_length,
748 aead_xform->digest_length,
749 RTE_CRYPTO_AUTH_OP_GENERATE))
752 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
754 * It needs to create authentication desc content first,
757 if (qat_alg_aead_session_create_content_desc_auth(session,
758 aead_xform->key.data,
759 aead_xform->key.length,
760 aead_xform->aad_length,
761 aead_xform->digest_length,
762 RTE_CRYPTO_AUTH_OP_VERIFY))
765 if (qat_alg_aead_session_create_content_desc_cipher(session,
766 aead_xform->key.data,
767 aead_xform->key.length))
771 session->digest_length = aead_xform->digest_length;
778 unsigned qat_crypto_sym_get_session_private_size(
779 struct rte_cryptodev *dev __rte_unused)
781 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
784 static inline uint32_t
785 qat_bpicipher_preprocess(struct qat_session *ctx,
786 struct rte_crypto_op *op)
788 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
789 struct rte_crypto_sym_op *sym_op = op->sym;
790 uint8_t last_block_len = block_len > 0 ?
791 sym_op->cipher.data.length % block_len : 0;
793 if (last_block_len &&
794 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
796 /* Decrypt last block */
797 uint8_t *last_block, *dst, *iv;
798 uint32_t last_block_offset = sym_op->cipher.data.offset +
799 sym_op->cipher.data.length - last_block_len;
800 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
801 uint8_t *, last_block_offset);
803 if (unlikely(sym_op->m_dst != NULL))
804 /* out-of-place operation (OOP) */
805 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
806 uint8_t *, last_block_offset);
810 if (last_block_len < sym_op->cipher.data.length)
811 /* use previous block ciphertext as IV */
812 iv = last_block - block_len;
814 /* runt block, i.e. less than one full block */
815 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
816 ctx->cipher_iv.offset);
818 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
819 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
821 if (sym_op->m_dst != NULL)
822 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
825 bpi_cipher_decrypt(last_block, dst, iv, block_len,
826 last_block_len, ctx->bpi_ctx);
827 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
828 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
830 if (sym_op->m_dst != NULL)
831 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
836 return sym_op->cipher.data.length - last_block_len;
839 static inline uint32_t
840 qat_bpicipher_postprocess(struct qat_session *ctx,
841 struct rte_crypto_op *op)
843 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
844 struct rte_crypto_sym_op *sym_op = op->sym;
845 uint8_t last_block_len = block_len > 0 ?
846 sym_op->cipher.data.length % block_len : 0;
848 if (last_block_len > 0 &&
849 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
851 /* Encrypt last block */
852 uint8_t *last_block, *dst, *iv;
853 uint32_t last_block_offset;
855 last_block_offset = sym_op->cipher.data.offset +
856 sym_op->cipher.data.length - last_block_len;
857 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
858 uint8_t *, last_block_offset);
860 if (unlikely(sym_op->m_dst != NULL))
861 /* out-of-place operation (OOP) */
862 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
863 uint8_t *, last_block_offset);
867 if (last_block_len < sym_op->cipher.data.length)
868 /* use previous block ciphertext as IV */
869 iv = dst - block_len;
871 /* runt block, i.e. less than one full block */
872 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
873 ctx->cipher_iv.offset);
875 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
876 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
878 if (sym_op->m_dst != NULL)
879 rte_hexdump(stdout, "BPI: dst before post-process:",
880 dst, last_block_len);
882 bpi_cipher_encrypt(last_block, dst, iv, block_len,
883 last_block_len, ctx->bpi_ctx);
884 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
885 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
887 if (sym_op->m_dst != NULL)
888 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
892 return sym_op->cipher.data.length - last_block_len;
896 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
899 register struct qat_queue *queue;
900 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
901 register uint32_t nb_ops_sent = 0;
902 register struct rte_crypto_op **cur_op = ops;
904 uint16_t nb_ops_possible = nb_ops;
905 register uint8_t *base_addr;
906 register uint32_t tail;
909 if (unlikely(nb_ops == 0))
912 /* read params used a lot in main loop into registers */
913 queue = &(tmp_qp->tx_q);
914 base_addr = (uint8_t *)queue->base_addr;
917 /* Find how many can actually fit on the ring */
918 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
919 - queue->max_inflights;
921 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
922 nb_ops_possible = nb_ops - overflow;
923 if (nb_ops_possible == 0)
927 while (nb_ops_sent != nb_ops_possible) {
928 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
929 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
931 tmp_qp->stats.enqueue_err_count++;
933 * This message cannot be enqueued,
934 * decrease number of ops that wasn't sent
936 rte_atomic16_sub(&tmp_qp->inflights16,
937 nb_ops_possible - nb_ops_sent);
938 if (nb_ops_sent == 0)
943 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
948 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
949 queue->hw_queue_number, tail);
951 tmp_qp->stats.enqueued_count += nb_ops_sent;
956 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
959 struct qat_queue *queue;
960 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
961 uint32_t msg_counter = 0;
962 struct rte_crypto_op *rx_op;
963 struct icp_qat_fw_comn_resp *resp_msg;
965 queue = &(tmp_qp->rx_q);
966 resp_msg = (struct icp_qat_fw_comn_resp *)
967 ((uint8_t *)queue->base_addr + queue->head);
969 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
970 msg_counter != nb_ops) {
971 rx_op = (struct rte_crypto_op *)(uintptr_t)
972 (resp_msg->opaque_data);
974 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
975 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
976 sizeof(struct icp_qat_fw_comn_resp));
979 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
980 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
981 resp_msg->comn_hdr.comn_status)) {
982 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
984 struct qat_session *sess = (struct qat_session *)
985 get_session_private_data(
987 cryptodev_qat_driver_id);
990 qat_bpicipher_postprocess(sess, rx_op);
991 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
994 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
995 queue->head = adf_modulo(queue->head +
997 ADF_RING_SIZE_MODULO(queue->queue_size));
998 resp_msg = (struct icp_qat_fw_comn_resp *)
999 ((uint8_t *)queue->base_addr +
1005 if (msg_counter > 0) {
1006 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
1007 queue->hw_bundle_number,
1008 queue->hw_queue_number, queue->head);
1009 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
1010 tmp_qp->stats.dequeued_count += msg_counter;
1016 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1017 struct qat_alg_buf_list *list, uint32_t data_len)
1021 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1022 buff_start + rte_pktmbuf_data_len(buf);
1024 list->bufers[0].addr = buff_start;
1025 list->bufers[0].resrvd = 0;
1026 list->bufers[0].len = buf_len;
1028 if (data_len <= buf_len) {
1029 list->num_bufs = nr;
1030 list->bufers[0].len = data_len;
1036 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1037 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1039 QAT_SGL_MAX_NUMBER);
1043 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1044 list->bufers[nr].resrvd = 0;
1045 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1047 buf_len += list->bufers[nr].len;
1050 if (buf_len > data_len) {
1051 list->bufers[nr].len -=
1057 list->num_bufs = nr;
1063 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1064 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1065 struct rte_crypto_op *op,
1066 struct icp_qat_fw_la_bulk_req *qat_req)
1068 /* copy IV into request if it fits */
1069 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1070 rte_memcpy(cipher_param->u.cipher_IV_array,
1071 rte_crypto_op_ctod_offset(op, uint8_t *,
1075 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1076 qat_req->comn_hdr.serv_specif_flags,
1077 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1078 cipher_param->u.s.cipher_IV_ptr =
1079 rte_crypto_op_ctophys_offset(op,
1085 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1086 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1089 struct qat_session *ctx;
1090 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1091 struct icp_qat_fw_la_auth_req_params *auth_param;
1092 register struct icp_qat_fw_la_bulk_req *qat_req;
1093 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1094 uint32_t cipher_len = 0, cipher_ofs = 0;
1095 uint32_t auth_len = 0, auth_ofs = 0;
1096 uint32_t min_ofs = 0;
1097 uint64_t src_buf_start = 0, dst_buf_start = 0;
1100 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1101 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1102 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1103 "operation requests, op (%p) is not a "
1104 "symmetric operation.", op);
1108 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1109 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1110 " requests, op (%p) is sessionless.", op);
1114 ctx = (struct qat_session *)get_session_private_data(
1115 op->sym->session, cryptodev_qat_driver_id);
1117 if (unlikely(ctx == NULL)) {
1118 PMD_DRV_LOG(ERR, "Session was not created for this device");
1122 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1123 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1124 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1128 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1129 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1130 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1131 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1132 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1134 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1135 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1137 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1138 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1144 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1147 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1154 if (ctx->qat_cipher_alg ==
1155 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1156 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1157 ctx->qat_cipher_alg ==
1158 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1161 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1162 || (cipher_param->cipher_offset
1163 % BYTE_LENGTH != 0))) {
1165 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1166 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1169 cipher_len = op->sym->cipher.data.length >> 3;
1170 cipher_ofs = op->sym->cipher.data.offset >> 3;
1172 } else if (ctx->bpi_ctx) {
1173 /* DOCSIS - only send complete blocks to device
1174 * Process any partial block using CFB mode.
1175 * Even if 0 complete blocks, still send this to device
1176 * to get into rx queue for post-process and dequeuing
1178 cipher_len = qat_bpicipher_preprocess(ctx, op);
1179 cipher_ofs = op->sym->cipher.data.offset;
1181 cipher_len = op->sym->cipher.data.length;
1182 cipher_ofs = op->sym->cipher.data.offset;
1185 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1186 cipher_param, op, qat_req);
1187 min_ofs = cipher_ofs;
1192 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1193 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1194 ctx->qat_hash_alg ==
1195 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1196 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1197 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1199 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1200 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1203 auth_ofs = op->sym->auth.data.offset >> 3;
1204 auth_len = op->sym->auth.data.length >> 3;
1206 auth_param->u1.aad_adr =
1207 rte_crypto_op_ctophys_offset(op,
1208 ctx->auth_iv.offset);
1210 } else if (ctx->qat_hash_alg ==
1211 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1212 ctx->qat_hash_alg ==
1213 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1215 set_cipher_iv(ctx->auth_iv.length,
1216 ctx->auth_iv.offset,
1217 cipher_param, op, qat_req);
1218 auth_ofs = op->sym->auth.data.offset;
1219 auth_len = op->sym->auth.data.length;
1221 auth_param->u1.aad_adr = 0;
1222 auth_param->u2.aad_sz = 0;
1225 * If len(iv)==12B fw computes J0
1227 if (ctx->auth_iv.length == 12) {
1228 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1229 qat_req->comn_hdr.serv_specif_flags,
1230 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1234 auth_ofs = op->sym->auth.data.offset;
1235 auth_len = op->sym->auth.data.length;
1240 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1245 if (ctx->qat_hash_alg ==
1246 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1247 ctx->qat_hash_alg ==
1248 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1250 * If len(iv)==12B fw computes J0
1252 if (ctx->cipher_iv.length == 12) {
1253 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1254 qat_req->comn_hdr.serv_specif_flags,
1255 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1260 cipher_len = op->sym->aead.data.length;
1261 cipher_ofs = op->sym->aead.data.offset;
1262 auth_len = op->sym->aead.data.length;
1263 auth_ofs = op->sym->aead.data.offset;
1265 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1266 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1267 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1268 cipher_param, op, qat_req);
1269 min_ofs = op->sym->aead.data.offset;
1272 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1275 /* adjust for chain case */
1276 if (do_cipher && do_auth)
1277 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1279 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1282 if (unlikely(op->sym->m_dst != NULL)) {
1283 /* Out-of-place operation (OOP)
1284 * Don't align DMA start. DMA the minimum data-set
1285 * so as not to overwrite data in dest buffer
1288 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1290 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1293 /* In-place operation
1294 * Start DMA at nearest aligned address below min_ofs
1297 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1298 & QAT_64_BTYE_ALIGN_MASK;
1300 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1301 rte_pktmbuf_headroom(op->sym->m_src))
1303 /* alignment has pushed addr ahead of start of mbuf
1304 * so revert and take the performance hit
1307 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1310 dst_buf_start = src_buf_start;
1313 if (do_cipher || do_aead) {
1314 cipher_param->cipher_offset =
1315 (uint32_t)rte_pktmbuf_mtophys_offset(
1316 op->sym->m_src, cipher_ofs) - src_buf_start;
1317 cipher_param->cipher_length = cipher_len;
1319 cipher_param->cipher_offset = 0;
1320 cipher_param->cipher_length = 0;
1323 if (do_auth || do_aead) {
1324 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1325 op->sym->m_src, auth_ofs) - src_buf_start;
1326 auth_param->auth_len = auth_len;
1328 auth_param->auth_off = 0;
1329 auth_param->auth_len = 0;
1332 qat_req->comn_mid.dst_length =
1333 qat_req->comn_mid.src_length =
1334 (cipher_param->cipher_offset + cipher_param->cipher_length)
1335 > (auth_param->auth_off + auth_param->auth_len) ?
1336 (cipher_param->cipher_offset + cipher_param->cipher_length)
1337 : (auth_param->auth_off + auth_param->auth_len);
1341 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1342 QAT_COMN_PTR_TYPE_SGL);
1343 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1344 &qat_op_cookie->qat_sgl_list_src,
1345 qat_req->comn_mid.src_length);
1347 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1351 if (likely(op->sym->m_dst == NULL))
1352 qat_req->comn_mid.dest_data_addr =
1353 qat_req->comn_mid.src_data_addr =
1354 qat_op_cookie->qat_sgl_src_phys_addr;
1356 ret = qat_sgl_fill_array(op->sym->m_dst,
1358 &qat_op_cookie->qat_sgl_list_dst,
1359 qat_req->comn_mid.dst_length);
1362 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1367 qat_req->comn_mid.src_data_addr =
1368 qat_op_cookie->qat_sgl_src_phys_addr;
1369 qat_req->comn_mid.dest_data_addr =
1370 qat_op_cookie->qat_sgl_dst_phys_addr;
1373 qat_req->comn_mid.src_data_addr = src_buf_start;
1374 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1377 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1378 rte_hexdump(stdout, "qat_req:", qat_req,
1379 sizeof(struct icp_qat_fw_la_bulk_req));
1380 rte_hexdump(stdout, "src_data:",
1381 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1382 rte_pktmbuf_data_len(op->sym->m_src));
1384 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1386 ctx->cipher_iv.offset);
1387 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1388 ctx->cipher_iv.length);
1392 if (ctx->auth_iv.length) {
1393 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1395 ctx->auth_iv.offset);
1396 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1397 ctx->auth_iv.length);
1399 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1400 ctx->digest_length);
1404 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1405 ctx->digest_length);
1406 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1413 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1415 uint32_t div = data >> shift;
1416 uint32_t mult = div << shift;
1421 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1422 __rte_unused struct rte_cryptodev_config *config)
1424 PMD_INIT_FUNC_TRACE();
1428 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1430 PMD_INIT_FUNC_TRACE();
1434 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1436 PMD_INIT_FUNC_TRACE();
1439 int qat_dev_close(struct rte_cryptodev *dev)
1443 PMD_INIT_FUNC_TRACE();
1445 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1446 ret = qat_crypto_sym_qp_release(dev, i);
1454 void qat_dev_info_get(struct rte_cryptodev *dev,
1455 struct rte_cryptodev_info *info)
1457 struct qat_pmd_private *internals = dev->data->dev_private;
1459 PMD_INIT_FUNC_TRACE();
1461 info->max_nb_queue_pairs =
1462 ADF_NUM_SYM_QPS_PER_BUNDLE *
1463 ADF_NUM_BUNDLES_PER_DEV;
1464 info->feature_flags = dev->feature_flags;
1465 info->capabilities = internals->qat_dev_capabilities;
1466 info->sym.max_nb_sessions = internals->max_nb_sessions;
1467 info->driver_id = cryptodev_qat_driver_id;
1468 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1472 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1473 struct rte_cryptodev_stats *stats)
1476 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1478 PMD_INIT_FUNC_TRACE();
1479 if (stats == NULL) {
1480 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1483 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1484 if (qp[i] == NULL) {
1485 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1489 stats->enqueued_count += qp[i]->stats.enqueued_count;
1490 stats->dequeued_count += qp[i]->stats.dequeued_count;
1491 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1492 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1496 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1499 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1501 PMD_INIT_FUNC_TRACE();
1502 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1503 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1504 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");