4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
58 #include <rte_mempool.h>
60 #include <rte_string_fns.h>
61 #include <rte_spinlock.h>
62 #include <rte_hexdump.h>
66 #include "qat_crypto.h"
67 #include "adf_transport_access_macros.h"
71 static inline uint32_t
72 adf_modulo(uint32_t data, uint32_t shift);
75 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
77 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
80 struct qat_session *sess = session;
81 phys_addr_t cd_paddr = sess->cd_paddr;
83 PMD_INIT_FUNC_TRACE();
85 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
87 sess->cd_paddr = cd_paddr;
92 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
95 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
96 return ICP_QAT_FW_LA_CMD_CIPHER;
98 /* Authentication Only */
99 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
100 return ICP_QAT_FW_LA_CMD_AUTH;
102 if (xform->next == NULL)
105 /* Cipher then Authenticate */
106 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
107 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
108 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
110 /* Authenticate then Cipher */
111 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
112 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
113 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
118 static struct rte_crypto_auth_xform *
119 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
122 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
131 static struct rte_crypto_cipher_xform *
132 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
135 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
136 return &xform->cipher;
144 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
145 struct rte_crypto_sym_xform *xform, void *session_private)
147 struct qat_pmd_private *internals = dev->data->dev_private;
149 struct qat_session *session = session_private;
151 struct rte_crypto_cipher_xform *cipher_xform = NULL;
153 /* Get cipher xform from crypto xform chain */
154 cipher_xform = qat_get_cipher_xform(xform);
156 switch (cipher_xform->algo) {
157 case RTE_CRYPTO_CIPHER_AES_CBC:
158 if (qat_alg_validate_aes_key(cipher_xform->key.length,
159 &session->qat_cipher_alg) != 0) {
160 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
163 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
165 case RTE_CRYPTO_CIPHER_AES_GCM:
166 if (qat_alg_validate_aes_key(cipher_xform->key.length,
167 &session->qat_cipher_alg) != 0) {
168 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
171 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
173 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
174 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
175 &session->qat_cipher_alg) != 0) {
176 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
179 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
181 case RTE_CRYPTO_CIPHER_NULL:
182 case RTE_CRYPTO_CIPHER_3DES_ECB:
183 case RTE_CRYPTO_CIPHER_3DES_CBC:
184 case RTE_CRYPTO_CIPHER_AES_ECB:
185 case RTE_CRYPTO_CIPHER_AES_CTR:
186 case RTE_CRYPTO_CIPHER_AES_CCM:
187 case RTE_CRYPTO_CIPHER_KASUMI_F8:
188 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
192 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
197 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
198 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
200 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
202 if (qat_alg_aead_session_create_content_desc_cipher(session,
203 cipher_xform->key.data,
204 cipher_xform->key.length))
210 rte_mempool_put(internals->sess_mp, session);
216 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
217 struct rte_crypto_sym_xform *xform, void *session_private)
219 struct qat_pmd_private *internals = dev->data->dev_private;
221 struct qat_session *session = session_private;
225 PMD_INIT_FUNC_TRACE();
227 /* Get requested QAT command id */
228 qat_cmd_id = qat_get_cmd_id(xform);
229 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
230 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
233 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
234 switch (session->qat_cmd) {
235 case ICP_QAT_FW_LA_CMD_CIPHER:
236 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
238 case ICP_QAT_FW_LA_CMD_AUTH:
239 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
241 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
242 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
243 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
245 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
246 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
247 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
249 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
250 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
251 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
252 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
253 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
254 case ICP_QAT_FW_LA_CMD_MGF1:
255 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
256 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
257 case ICP_QAT_FW_LA_CMD_DELIMITER:
258 PMD_DRV_LOG(ERR, "Unsupported Service %u",
262 PMD_DRV_LOG(ERR, "Unsupported Service %u",
269 rte_mempool_put(internals->sess_mp, session);
274 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
275 struct rte_crypto_sym_xform *xform,
276 struct qat_session *session_private)
279 struct qat_pmd_private *internals = dev->data->dev_private;
280 struct qat_session *session = session_private;
281 struct rte_crypto_auth_xform *auth_xform = NULL;
282 struct rte_crypto_cipher_xform *cipher_xform = NULL;
283 auth_xform = qat_get_auth_xform(xform);
285 switch (auth_xform->algo) {
286 case RTE_CRYPTO_AUTH_SHA1_HMAC:
287 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
289 case RTE_CRYPTO_AUTH_SHA256_HMAC:
290 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
292 case RTE_CRYPTO_AUTH_SHA512_HMAC:
293 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
295 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
296 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
298 case RTE_CRYPTO_AUTH_AES_GCM:
299 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
301 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
302 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
304 case RTE_CRYPTO_AUTH_NULL:
305 case RTE_CRYPTO_AUTH_SHA1:
306 case RTE_CRYPTO_AUTH_SHA256:
307 case RTE_CRYPTO_AUTH_SHA512:
308 case RTE_CRYPTO_AUTH_SHA224:
309 case RTE_CRYPTO_AUTH_SHA224_HMAC:
310 case RTE_CRYPTO_AUTH_SHA384:
311 case RTE_CRYPTO_AUTH_SHA384_HMAC:
312 case RTE_CRYPTO_AUTH_MD5:
313 case RTE_CRYPTO_AUTH_MD5_HMAC:
314 case RTE_CRYPTO_AUTH_AES_CCM:
315 case RTE_CRYPTO_AUTH_AES_GMAC:
316 case RTE_CRYPTO_AUTH_KASUMI_F9:
317 case RTE_CRYPTO_AUTH_AES_CMAC:
318 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
319 case RTE_CRYPTO_AUTH_ZUC_EIA3:
320 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
324 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
328 cipher_xform = qat_get_cipher_xform(xform);
330 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
331 (session->qat_hash_alg ==
332 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
333 if (qat_alg_aead_session_create_content_desc_auth(session,
334 cipher_xform->key.data,
335 cipher_xform->key.length,
336 auth_xform->add_auth_data_length,
337 auth_xform->digest_length))
340 if (qat_alg_aead_session_create_content_desc_auth(session,
341 auth_xform->key.data,
342 auth_xform->key.length,
343 auth_xform->add_auth_data_length,
344 auth_xform->digest_length))
350 rte_mempool_put(internals->sess_mp, session);
354 unsigned qat_crypto_sym_get_session_private_size(
355 struct rte_cryptodev *dev __rte_unused)
357 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
362 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
365 register struct qat_queue *queue;
366 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
367 register uint32_t nb_ops_sent = 0;
368 register struct rte_crypto_op **cur_op = ops;
370 uint16_t nb_ops_possible = nb_ops;
371 register uint8_t *base_addr;
372 register uint32_t tail;
375 /* read params used a lot in main loop into registers */
376 queue = &(tmp_qp->tx_q);
377 base_addr = (uint8_t *)queue->base_addr;
380 /* Find how many can actually fit on the ring */
381 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
382 - queue->max_inflights;
384 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
385 nb_ops_possible = nb_ops - overflow;
386 if (nb_ops_possible == 0)
390 while (nb_ops_sent != nb_ops_possible) {
391 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
393 tmp_qp->stats.enqueue_err_count++;
394 if (nb_ops_sent == 0)
399 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
404 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
405 queue->hw_queue_number, tail);
407 tmp_qp->stats.enqueued_count += nb_ops_sent;
412 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
415 struct qat_queue *queue;
416 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
417 uint32_t msg_counter = 0;
418 struct rte_crypto_op *rx_op;
419 struct icp_qat_fw_comn_resp *resp_msg;
421 queue = &(tmp_qp->rx_q);
422 resp_msg = (struct icp_qat_fw_comn_resp *)
423 ((uint8_t *)queue->base_addr + queue->head);
425 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
426 msg_counter != nb_ops) {
427 rx_op = (struct rte_crypto_op *)(uintptr_t)
428 (resp_msg->opaque_data);
430 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
431 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
432 sizeof(struct icp_qat_fw_comn_resp));
434 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
435 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
436 resp_msg->comn_hdr.comn_status)) {
437 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
439 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
441 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
442 queue->head = adf_modulo(queue->head +
444 ADF_RING_SIZE_MODULO(queue->queue_size));
445 resp_msg = (struct icp_qat_fw_comn_resp *)
446 ((uint8_t *)queue->base_addr +
452 if (msg_counter > 0) {
453 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
454 queue->hw_bundle_number,
455 queue->hw_queue_number, queue->head);
456 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
457 tmp_qp->stats.dequeued_count += msg_counter;
463 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
465 struct qat_session *ctx;
466 struct icp_qat_fw_la_cipher_req_params *cipher_param;
467 struct icp_qat_fw_la_auth_req_params *auth_param;
468 register struct icp_qat_fw_la_bulk_req *qat_req;
470 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
471 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
472 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
473 "operation requests, op (%p) is not a "
474 "symmetric operation.", op);
478 if (unlikely(op->sym->type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
479 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
480 " requests, op (%p) is sessionless.", op);
484 if (unlikely(op->sym->session->type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
485 PMD_DRV_LOG(ERR, "Session was not created for this device");
489 ctx = (struct qat_session *)op->sym->session->_private;
490 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
491 *qat_req = ctx->fw_req;
492 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
495 * The following code assumes:
496 * - single entry buffer.
499 qat_req->comn_mid.dst_length =
500 qat_req->comn_mid.src_length =
501 rte_pktmbuf_data_len(op->sym->m_src);
502 qat_req->comn_mid.dest_data_addr =
503 qat_req->comn_mid.src_data_addr =
504 rte_pktmbuf_mtophys(op->sym->m_src);
505 cipher_param = (void *)&qat_req->serv_specif_rqpars;
506 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
508 cipher_param->cipher_length = op->sym->cipher.data.length;
509 cipher_param->cipher_offset = op->sym->cipher.data.offset;
510 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
511 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
512 (cipher_param->cipher_offset
513 % BYTE_LENGTH != 0))) {
514 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
515 "supports byte aligned values");
516 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
519 cipher_param->cipher_length >>= 3;
520 cipher_param->cipher_offset >>= 3;
523 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
524 sizeof(cipher_param->u.cipher_IV_array))) {
525 rte_memcpy(cipher_param->u.cipher_IV_array,
526 op->sym->cipher.iv.data,
527 op->sym->cipher.iv.length);
529 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
530 qat_req->comn_hdr.serv_specif_flags,
531 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
532 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
534 if (op->sym->auth.digest.phys_addr) {
535 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
536 qat_req->comn_hdr.serv_specif_flags,
537 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
538 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
540 auth_param->auth_off = op->sym->auth.data.offset;
541 auth_param->auth_len = op->sym->auth.data.length;
542 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
543 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
544 (auth_param->auth_len % BYTE_LENGTH != 0))) {
545 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
546 "supports byte aligned values");
547 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
550 auth_param->auth_off >>= 3;
551 auth_param->auth_len >>= 3;
553 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
554 /* (GCM) aad length(240 max) will be at this location after precompute */
555 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
556 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
557 struct icp_qat_hw_auth_algo_blk *hash;
559 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER)
560 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd);
562 hash = (struct icp_qat_hw_auth_algo_blk *)((char *)&ctx->cd +
563 sizeof(struct icp_qat_hw_cipher_algo_blk));
565 auth_param->u2.aad_sz = ALIGN_POW2_ROUNDUP(hash->sha.state1[
566 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
567 ICP_QAT_HW_GALOIS_H_SZ + 3], 16);
568 if (op->sym->cipher.iv.length == 12) {
570 * For GCM a 12 bit IV is allowed,
571 * but we need to inform the f/w
573 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
574 qat_req->comn_hdr.serv_specif_flags,
575 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
578 auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
581 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
582 rte_hexdump(stdout, "qat_req:", qat_req,
583 sizeof(struct icp_qat_fw_la_bulk_req));
584 rte_hexdump(stdout, "src_data:",
585 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
586 rte_pktmbuf_data_len(op->sym->m_src));
587 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
588 op->sym->cipher.iv.length);
589 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
590 op->sym->auth.digest.length);
591 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
592 op->sym->auth.aad.length);
597 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
599 uint32_t div = data >> shift;
600 uint32_t mult = div << shift;
605 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *priv_sess)
607 struct qat_session *s = priv_sess;
609 PMD_INIT_FUNC_TRACE();
610 s->cd_paddr = rte_mempool_virt2phy(mp, &s->cd);
613 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
615 PMD_INIT_FUNC_TRACE();
619 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
621 PMD_INIT_FUNC_TRACE();
625 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
627 PMD_INIT_FUNC_TRACE();
630 int qat_dev_close(struct rte_cryptodev *dev)
634 PMD_INIT_FUNC_TRACE();
636 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
637 ret = qat_crypto_sym_qp_release(dev, i);
645 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
646 struct rte_cryptodev_info *info)
648 struct qat_pmd_private *internals = dev->data->dev_private;
650 PMD_INIT_FUNC_TRACE();
652 info->max_nb_queue_pairs =
653 ADF_NUM_SYM_QPS_PER_BUNDLE *
654 ADF_NUM_BUNDLES_PER_DEV;
656 info->sym.max_nb_sessions = internals->max_nb_sessions;
657 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
661 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
662 struct rte_cryptodev_stats *stats)
665 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
667 PMD_INIT_FUNC_TRACE();
669 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
672 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
674 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
678 stats->enqueued_count += qp[i]->stats.enqueued_count;
679 stats->dequeued_count += qp[i]->stats.enqueued_count;
680 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
681 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
685 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
688 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
690 PMD_INIT_FUNC_TRACE();
691 for (i = 0; i < dev->data->nb_queue_pairs; i++)
692 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
693 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");