4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
177 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
179 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
181 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
197 { /* AES GCM (AUTH) */
198 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
200 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
202 .algo = RTE_CRYPTO_AUTH_AES_GCM,
222 { /* SNOW3G (UIA2) */
223 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
225 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
227 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
247 { /* AES GCM (CIPHER) */
248 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
250 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
252 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
268 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
270 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
272 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
287 { /* SNOW3G (UEA2) */
288 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
290 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
292 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
308 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
310 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
312 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
327 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
330 static inline uint32_t
331 adf_modulo(uint32_t data, uint32_t shift);
334 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
336 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
339 struct qat_session *sess = session;
340 phys_addr_t cd_paddr;
342 PMD_INIT_FUNC_TRACE();
344 cd_paddr = sess->cd_paddr;
345 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
346 sess->cd_paddr = cd_paddr;
348 PMD_DRV_LOG(ERR, "NULL session");
352 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
355 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
356 return ICP_QAT_FW_LA_CMD_CIPHER;
358 /* Authentication Only */
359 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
360 return ICP_QAT_FW_LA_CMD_AUTH;
362 if (xform->next == NULL)
365 /* Cipher then Authenticate */
366 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
367 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
368 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
370 /* Authenticate then Cipher */
371 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
372 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
373 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
378 static struct rte_crypto_auth_xform *
379 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
382 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
391 static struct rte_crypto_cipher_xform *
392 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
395 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
396 return &xform->cipher;
404 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
405 struct rte_crypto_sym_xform *xform, void *session_private)
407 struct qat_pmd_private *internals = dev->data->dev_private;
409 struct qat_session *session = session_private;
411 struct rte_crypto_cipher_xform *cipher_xform = NULL;
413 /* Get cipher xform from crypto xform chain */
414 cipher_xform = qat_get_cipher_xform(xform);
416 switch (cipher_xform->algo) {
417 case RTE_CRYPTO_CIPHER_AES_CBC:
418 if (qat_alg_validate_aes_key(cipher_xform->key.length,
419 &session->qat_cipher_alg) != 0) {
420 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
423 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
425 case RTE_CRYPTO_CIPHER_AES_GCM:
426 if (qat_alg_validate_aes_key(cipher_xform->key.length,
427 &session->qat_cipher_alg) != 0) {
428 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
431 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
433 case RTE_CRYPTO_CIPHER_AES_CTR:
434 if (qat_alg_validate_aes_key(cipher_xform->key.length,
435 &session->qat_cipher_alg) != 0) {
436 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
439 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
441 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
442 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
443 &session->qat_cipher_alg) != 0) {
444 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
447 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
449 case RTE_CRYPTO_CIPHER_NULL:
450 case RTE_CRYPTO_CIPHER_3DES_ECB:
451 case RTE_CRYPTO_CIPHER_3DES_CBC:
452 case RTE_CRYPTO_CIPHER_AES_ECB:
453 case RTE_CRYPTO_CIPHER_AES_CCM:
454 case RTE_CRYPTO_CIPHER_KASUMI_F8:
455 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
459 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
464 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
465 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
467 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
469 if (qat_alg_aead_session_create_content_desc_cipher(session,
470 cipher_xform->key.data,
471 cipher_xform->key.length))
477 rte_mempool_put(internals->sess_mp, session);
483 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
484 struct rte_crypto_sym_xform *xform, void *session_private)
486 struct qat_pmd_private *internals = dev->data->dev_private;
488 struct qat_session *session = session_private;
492 PMD_INIT_FUNC_TRACE();
494 /* Get requested QAT command id */
495 qat_cmd_id = qat_get_cmd_id(xform);
496 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
497 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
500 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
501 switch (session->qat_cmd) {
502 case ICP_QAT_FW_LA_CMD_CIPHER:
503 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
505 case ICP_QAT_FW_LA_CMD_AUTH:
506 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
508 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
509 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
510 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
512 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
513 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
514 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
516 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
517 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
518 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
519 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
520 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
521 case ICP_QAT_FW_LA_CMD_MGF1:
522 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
523 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
524 case ICP_QAT_FW_LA_CMD_DELIMITER:
525 PMD_DRV_LOG(ERR, "Unsupported Service %u",
529 PMD_DRV_LOG(ERR, "Unsupported Service %u",
536 rte_mempool_put(internals->sess_mp, session);
541 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
542 struct rte_crypto_sym_xform *xform,
543 struct qat_session *session_private)
546 struct qat_pmd_private *internals = dev->data->dev_private;
547 struct qat_session *session = session_private;
548 struct rte_crypto_auth_xform *auth_xform = NULL;
549 struct rte_crypto_cipher_xform *cipher_xform = NULL;
550 auth_xform = qat_get_auth_xform(xform);
552 switch (auth_xform->algo) {
553 case RTE_CRYPTO_AUTH_SHA1_HMAC:
554 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
556 case RTE_CRYPTO_AUTH_SHA256_HMAC:
557 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
559 case RTE_CRYPTO_AUTH_SHA512_HMAC:
560 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
562 case RTE_CRYPTO_AUTH_SHA224_HMAC:
563 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
565 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
566 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
568 case RTE_CRYPTO_AUTH_AES_GCM:
569 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
571 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
572 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
574 case RTE_CRYPTO_AUTH_MD5_HMAC:
575 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
577 case RTE_CRYPTO_AUTH_NULL:
578 case RTE_CRYPTO_AUTH_SHA1:
579 case RTE_CRYPTO_AUTH_SHA256:
580 case RTE_CRYPTO_AUTH_SHA512:
581 case RTE_CRYPTO_AUTH_SHA224:
582 case RTE_CRYPTO_AUTH_SHA384:
583 case RTE_CRYPTO_AUTH_SHA384_HMAC:
584 case RTE_CRYPTO_AUTH_MD5:
585 case RTE_CRYPTO_AUTH_AES_CCM:
586 case RTE_CRYPTO_AUTH_AES_GMAC:
587 case RTE_CRYPTO_AUTH_KASUMI_F9:
588 case RTE_CRYPTO_AUTH_AES_CMAC:
589 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
590 case RTE_CRYPTO_AUTH_ZUC_EIA3:
591 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
595 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
599 cipher_xform = qat_get_cipher_xform(xform);
601 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
602 (session->qat_hash_alg ==
603 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
604 if (qat_alg_aead_session_create_content_desc_auth(session,
605 cipher_xform->key.data,
606 cipher_xform->key.length,
607 auth_xform->add_auth_data_length,
608 auth_xform->digest_length,
612 if (qat_alg_aead_session_create_content_desc_auth(session,
613 auth_xform->key.data,
614 auth_xform->key.length,
615 auth_xform->add_auth_data_length,
616 auth_xform->digest_length,
623 if (internals->sess_mp != NULL)
624 rte_mempool_put(internals->sess_mp, session);
628 unsigned qat_crypto_sym_get_session_private_size(
629 struct rte_cryptodev *dev __rte_unused)
631 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
636 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
639 register struct qat_queue *queue;
640 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
641 register uint32_t nb_ops_sent = 0;
642 register struct rte_crypto_op **cur_op = ops;
644 uint16_t nb_ops_possible = nb_ops;
645 register uint8_t *base_addr;
646 register uint32_t tail;
649 if (unlikely(nb_ops == 0))
652 /* read params used a lot in main loop into registers */
653 queue = &(tmp_qp->tx_q);
654 base_addr = (uint8_t *)queue->base_addr;
657 /* Find how many can actually fit on the ring */
658 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
659 - queue->max_inflights;
661 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
662 nb_ops_possible = nb_ops - overflow;
663 if (nb_ops_possible == 0)
667 while (nb_ops_sent != nb_ops_possible) {
668 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
670 tmp_qp->stats.enqueue_err_count++;
671 if (nb_ops_sent == 0)
676 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
681 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
682 queue->hw_queue_number, tail);
684 tmp_qp->stats.enqueued_count += nb_ops_sent;
689 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
692 struct qat_queue *queue;
693 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
694 uint32_t msg_counter = 0;
695 struct rte_crypto_op *rx_op;
696 struct icp_qat_fw_comn_resp *resp_msg;
698 queue = &(tmp_qp->rx_q);
699 resp_msg = (struct icp_qat_fw_comn_resp *)
700 ((uint8_t *)queue->base_addr + queue->head);
702 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
703 msg_counter != nb_ops) {
704 rx_op = (struct rte_crypto_op *)(uintptr_t)
705 (resp_msg->opaque_data);
707 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
708 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
709 sizeof(struct icp_qat_fw_comn_resp));
711 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
712 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
713 resp_msg->comn_hdr.comn_status)) {
714 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
716 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
718 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
719 queue->head = adf_modulo(queue->head +
721 ADF_RING_SIZE_MODULO(queue->queue_size));
722 resp_msg = (struct icp_qat_fw_comn_resp *)
723 ((uint8_t *)queue->base_addr +
729 if (msg_counter > 0) {
730 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
731 queue->hw_bundle_number,
732 queue->hw_queue_number, queue->head);
733 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
734 tmp_qp->stats.dequeued_count += msg_counter;
740 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
742 struct qat_session *ctx;
743 struct icp_qat_fw_la_cipher_req_params *cipher_param;
744 struct icp_qat_fw_la_auth_req_params *auth_param;
745 register struct icp_qat_fw_la_bulk_req *qat_req;
747 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
748 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
749 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
750 "operation requests, op (%p) is not a "
751 "symmetric operation.", op);
755 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
756 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
757 " requests, op (%p) is sessionless.", op);
761 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
762 PMD_DRV_LOG(ERR, "Session was not created for this device");
766 ctx = (struct qat_session *)op->sym->session->_private;
767 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
768 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
769 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
771 qat_req->comn_mid.dst_length =
772 qat_req->comn_mid.src_length =
773 rte_pktmbuf_data_len(op->sym->m_src);
775 qat_req->comn_mid.dest_data_addr =
776 qat_req->comn_mid.src_data_addr =
777 rte_pktmbuf_mtophys(op->sym->m_src);
779 if (unlikely(op->sym->m_dst != NULL)) {
780 qat_req->comn_mid.dest_data_addr =
781 rte_pktmbuf_mtophys(op->sym->m_dst);
782 qat_req->comn_mid.dst_length =
783 rte_pktmbuf_data_len(op->sym->m_dst);
786 cipher_param = (void *)&qat_req->serv_specif_rqpars;
787 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
789 cipher_param->cipher_length = op->sym->cipher.data.length;
790 cipher_param->cipher_offset = op->sym->cipher.data.offset;
791 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
792 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
793 (cipher_param->cipher_offset
794 % BYTE_LENGTH != 0))) {
795 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
796 "supports byte aligned values");
797 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
800 cipher_param->cipher_length >>= 3;
801 cipher_param->cipher_offset >>= 3;
804 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
805 sizeof(cipher_param->u.cipher_IV_array))) {
806 rte_memcpy(cipher_param->u.cipher_IV_array,
807 op->sym->cipher.iv.data,
808 op->sym->cipher.iv.length);
810 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
811 qat_req->comn_hdr.serv_specif_flags,
812 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
813 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
815 if (op->sym->auth.digest.phys_addr) {
816 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
817 qat_req->comn_hdr.serv_specif_flags,
818 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
819 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
821 auth_param->auth_off = op->sym->auth.data.offset;
822 auth_param->auth_len = op->sym->auth.data.length;
823 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
824 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
825 (auth_param->auth_len % BYTE_LENGTH != 0))) {
826 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
827 "supports byte aligned values");
828 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
831 auth_param->auth_off >>= 3;
832 auth_param->auth_len >>= 3;
834 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
836 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
837 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
838 if (op->sym->cipher.iv.length == 12) {
840 * For GCM a 12 bit IV is allowed,
841 * but we need to inform the f/w
843 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
844 qat_req->comn_hdr.serv_specif_flags,
845 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
849 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
850 rte_hexdump(stdout, "qat_req:", qat_req,
851 sizeof(struct icp_qat_fw_la_bulk_req));
852 rte_hexdump(stdout, "src_data:",
853 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
854 rte_pktmbuf_data_len(op->sym->m_src));
855 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
856 op->sym->cipher.iv.length);
857 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
858 op->sym->auth.digest.length);
859 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
860 op->sym->auth.aad.length);
865 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
867 uint32_t div = data >> shift;
868 uint32_t mult = div << shift;
873 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
875 struct rte_cryptodev_sym_session *sess = sym_sess;
876 struct qat_session *s = (void *)sess->_private;
878 PMD_INIT_FUNC_TRACE();
879 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
880 offsetof(struct qat_session, cd) +
881 offsetof(struct rte_cryptodev_sym_session, _private);
884 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
886 PMD_INIT_FUNC_TRACE();
890 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
892 PMD_INIT_FUNC_TRACE();
896 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
898 PMD_INIT_FUNC_TRACE();
901 int qat_dev_close(struct rte_cryptodev *dev)
905 PMD_INIT_FUNC_TRACE();
907 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
908 ret = qat_crypto_sym_qp_release(dev, i);
916 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
917 struct rte_cryptodev_info *info)
919 struct qat_pmd_private *internals = dev->data->dev_private;
921 PMD_INIT_FUNC_TRACE();
923 info->max_nb_queue_pairs =
924 ADF_NUM_SYM_QPS_PER_BUNDLE *
925 ADF_NUM_BUNDLES_PER_DEV;
926 info->feature_flags = dev->feature_flags;
927 info->capabilities = qat_pmd_capabilities;
928 info->sym.max_nb_sessions = internals->max_nb_sessions;
929 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
933 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
934 struct rte_cryptodev_stats *stats)
937 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
939 PMD_INIT_FUNC_TRACE();
941 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
944 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
946 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
950 stats->enqueued_count += qp[i]->stats.enqueued_count;
951 stats->dequeued_count += qp[i]->stats.enqueued_count;
952 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
953 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
957 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
960 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
962 PMD_INIT_FUNC_TRACE();
963 for (i = 0; i < dev->data->nb_queue_pairs; i++)
964 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
965 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");