4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
65 #include "qat_crypto.h"
66 #include "adf_transport_access_macros.h"
70 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
72 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
74 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
76 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
93 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
95 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
97 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
114 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
116 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
118 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
135 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
137 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
139 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
156 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
158 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
160 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
177 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
179 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
181 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
198 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
200 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
202 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
218 { /* AES GCM (AUTH) */
219 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
221 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
223 .algo = RTE_CRYPTO_AUTH_AES_GCM,
243 { /* SNOW3G (UIA2) */
244 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
246 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
248 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
268 { /* AES GCM (CIPHER) */
269 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
271 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
273 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
289 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
291 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
293 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
308 { /* SNOW3G (UEA2) */
309 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
311 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
313 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
329 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
331 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
333 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
349 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
351 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
353 .algo = RTE_CRYPTO_AUTH_NULL,
369 { /* NULL (CIPHER) */
370 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
372 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
374 .algo = RTE_CRYPTO_CIPHER_NULL,
390 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
392 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
394 .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
410 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
412 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
414 .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
434 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
437 static inline uint32_t
438 adf_modulo(uint32_t data, uint32_t shift);
441 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg);
443 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
446 struct qat_session *sess = session;
447 phys_addr_t cd_paddr;
449 PMD_INIT_FUNC_TRACE();
451 cd_paddr = sess->cd_paddr;
452 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
453 sess->cd_paddr = cd_paddr;
455 PMD_DRV_LOG(ERR, "NULL session");
459 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
462 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
463 return ICP_QAT_FW_LA_CMD_CIPHER;
465 /* Authentication Only */
466 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
467 return ICP_QAT_FW_LA_CMD_AUTH;
469 if (xform->next == NULL)
472 /* Cipher then Authenticate */
473 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
474 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
475 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
477 /* Authenticate then Cipher */
478 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
479 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
480 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
485 static struct rte_crypto_auth_xform *
486 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
489 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
498 static struct rte_crypto_cipher_xform *
499 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
502 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
503 return &xform->cipher;
511 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
512 struct rte_crypto_sym_xform *xform, void *session_private)
514 struct qat_pmd_private *internals = dev->data->dev_private;
516 struct qat_session *session = session_private;
518 struct rte_crypto_cipher_xform *cipher_xform = NULL;
520 /* Get cipher xform from crypto xform chain */
521 cipher_xform = qat_get_cipher_xform(xform);
523 switch (cipher_xform->algo) {
524 case RTE_CRYPTO_CIPHER_AES_CBC:
525 if (qat_alg_validate_aes_key(cipher_xform->key.length,
526 &session->qat_cipher_alg) != 0) {
527 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
530 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
532 case RTE_CRYPTO_CIPHER_AES_GCM:
533 if (qat_alg_validate_aes_key(cipher_xform->key.length,
534 &session->qat_cipher_alg) != 0) {
535 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
538 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
540 case RTE_CRYPTO_CIPHER_AES_CTR:
541 if (qat_alg_validate_aes_key(cipher_xform->key.length,
542 &session->qat_cipher_alg) != 0) {
543 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
546 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
548 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
549 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
550 &session->qat_cipher_alg) != 0) {
551 PMD_DRV_LOG(ERR, "Invalid SNOW3G cipher key size");
554 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
556 case RTE_CRYPTO_CIPHER_NULL:
557 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
559 case RTE_CRYPTO_CIPHER_KASUMI_F8:
560 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
561 &session->qat_cipher_alg) != 0) {
562 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
565 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
567 case RTE_CRYPTO_CIPHER_3DES_ECB:
568 case RTE_CRYPTO_CIPHER_3DES_CBC:
569 case RTE_CRYPTO_CIPHER_AES_ECB:
570 case RTE_CRYPTO_CIPHER_AES_CCM:
571 PMD_DRV_LOG(ERR, "Crypto: Unsupported Cipher alg %u",
575 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
580 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
581 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
583 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
585 if (qat_alg_aead_session_create_content_desc_cipher(session,
586 cipher_xform->key.data,
587 cipher_xform->key.length))
593 rte_mempool_put(internals->sess_mp, session);
599 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
600 struct rte_crypto_sym_xform *xform, void *session_private)
602 struct qat_pmd_private *internals = dev->data->dev_private;
604 struct qat_session *session = session_private;
608 PMD_INIT_FUNC_TRACE();
610 /* Get requested QAT command id */
611 qat_cmd_id = qat_get_cmd_id(xform);
612 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
613 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
616 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
617 switch (session->qat_cmd) {
618 case ICP_QAT_FW_LA_CMD_CIPHER:
619 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
621 case ICP_QAT_FW_LA_CMD_AUTH:
622 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
624 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
625 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
626 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
628 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
629 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
630 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
632 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
633 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
634 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
635 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
636 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
637 case ICP_QAT_FW_LA_CMD_MGF1:
638 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
639 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
640 case ICP_QAT_FW_LA_CMD_DELIMITER:
641 PMD_DRV_LOG(ERR, "Unsupported Service %u",
645 PMD_DRV_LOG(ERR, "Unsupported Service %u",
652 rte_mempool_put(internals->sess_mp, session);
657 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
658 struct rte_crypto_sym_xform *xform,
659 struct qat_session *session_private)
662 struct qat_pmd_private *internals = dev->data->dev_private;
663 struct qat_session *session = session_private;
664 struct rte_crypto_auth_xform *auth_xform = NULL;
665 struct rte_crypto_cipher_xform *cipher_xform = NULL;
666 auth_xform = qat_get_auth_xform(xform);
668 switch (auth_xform->algo) {
669 case RTE_CRYPTO_AUTH_SHA1_HMAC:
670 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
672 case RTE_CRYPTO_AUTH_SHA224_HMAC:
673 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
675 case RTE_CRYPTO_AUTH_SHA256_HMAC:
676 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
678 case RTE_CRYPTO_AUTH_SHA384_HMAC:
679 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
681 case RTE_CRYPTO_AUTH_SHA512_HMAC:
682 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
684 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
685 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
687 case RTE_CRYPTO_AUTH_AES_GCM:
688 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
690 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
691 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
693 case RTE_CRYPTO_AUTH_MD5_HMAC:
694 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
696 case RTE_CRYPTO_AUTH_NULL:
697 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
699 case RTE_CRYPTO_AUTH_KASUMI_F9:
700 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
702 case RTE_CRYPTO_AUTH_SHA1:
703 case RTE_CRYPTO_AUTH_SHA256:
704 case RTE_CRYPTO_AUTH_SHA512:
705 case RTE_CRYPTO_AUTH_SHA224:
706 case RTE_CRYPTO_AUTH_SHA384:
707 case RTE_CRYPTO_AUTH_MD5:
708 case RTE_CRYPTO_AUTH_AES_CCM:
709 case RTE_CRYPTO_AUTH_AES_GMAC:
710 case RTE_CRYPTO_AUTH_AES_CMAC:
711 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
712 case RTE_CRYPTO_AUTH_ZUC_EIA3:
713 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
717 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
721 cipher_xform = qat_get_cipher_xform(xform);
723 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
724 (session->qat_hash_alg ==
725 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
726 if (qat_alg_aead_session_create_content_desc_auth(session,
727 cipher_xform->key.data,
728 cipher_xform->key.length,
729 auth_xform->add_auth_data_length,
730 auth_xform->digest_length,
734 if (qat_alg_aead_session_create_content_desc_auth(session,
735 auth_xform->key.data,
736 auth_xform->key.length,
737 auth_xform->add_auth_data_length,
738 auth_xform->digest_length,
745 if (internals->sess_mp != NULL)
746 rte_mempool_put(internals->sess_mp, session);
750 unsigned qat_crypto_sym_get_session_private_size(
751 struct rte_cryptodev *dev __rte_unused)
753 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
758 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
761 register struct qat_queue *queue;
762 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
763 register uint32_t nb_ops_sent = 0;
764 register struct rte_crypto_op **cur_op = ops;
766 uint16_t nb_ops_possible = nb_ops;
767 register uint8_t *base_addr;
768 register uint32_t tail;
771 if (unlikely(nb_ops == 0))
774 /* read params used a lot in main loop into registers */
775 queue = &(tmp_qp->tx_q);
776 base_addr = (uint8_t *)queue->base_addr;
779 /* Find how many can actually fit on the ring */
780 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
781 - queue->max_inflights;
783 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
784 nb_ops_possible = nb_ops - overflow;
785 if (nb_ops_possible == 0)
789 while (nb_ops_sent != nb_ops_possible) {
790 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail);
792 tmp_qp->stats.enqueue_err_count++;
793 if (nb_ops_sent == 0)
798 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
803 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
804 queue->hw_queue_number, tail);
806 tmp_qp->stats.enqueued_count += nb_ops_sent;
811 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
814 struct qat_queue *queue;
815 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
816 uint32_t msg_counter = 0;
817 struct rte_crypto_op *rx_op;
818 struct icp_qat_fw_comn_resp *resp_msg;
820 queue = &(tmp_qp->rx_q);
821 resp_msg = (struct icp_qat_fw_comn_resp *)
822 ((uint8_t *)queue->base_addr + queue->head);
824 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
825 msg_counter != nb_ops) {
826 rx_op = (struct rte_crypto_op *)(uintptr_t)
827 (resp_msg->opaque_data);
829 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
830 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
831 sizeof(struct icp_qat_fw_comn_resp));
833 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
834 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
835 resp_msg->comn_hdr.comn_status)) {
836 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
838 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
840 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
841 queue->head = adf_modulo(queue->head +
843 ADF_RING_SIZE_MODULO(queue->queue_size));
844 resp_msg = (struct icp_qat_fw_comn_resp *)
845 ((uint8_t *)queue->base_addr +
851 if (msg_counter > 0) {
852 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
853 queue->hw_bundle_number,
854 queue->hw_queue_number, queue->head);
855 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
856 tmp_qp->stats.dequeued_count += msg_counter;
862 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg)
864 struct qat_session *ctx;
865 struct icp_qat_fw_la_cipher_req_params *cipher_param;
866 struct icp_qat_fw_la_auth_req_params *auth_param;
867 register struct icp_qat_fw_la_bulk_req *qat_req;
869 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
870 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
871 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
872 "operation requests, op (%p) is not a "
873 "symmetric operation.", op);
877 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
878 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
879 " requests, op (%p) is sessionless.", op);
883 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
884 PMD_DRV_LOG(ERR, "Session was not created for this device");
888 ctx = (struct qat_session *)op->sym->session->_private;
889 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
890 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
891 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
893 qat_req->comn_mid.dst_length =
894 qat_req->comn_mid.src_length =
895 rte_pktmbuf_data_len(op->sym->m_src);
897 qat_req->comn_mid.dest_data_addr =
898 qat_req->comn_mid.src_data_addr =
899 rte_pktmbuf_mtophys(op->sym->m_src);
901 if (unlikely(op->sym->m_dst != NULL)) {
902 qat_req->comn_mid.dest_data_addr =
903 rte_pktmbuf_mtophys(op->sym->m_dst);
904 qat_req->comn_mid.dst_length =
905 rte_pktmbuf_data_len(op->sym->m_dst);
908 cipher_param = (void *)&qat_req->serv_specif_rqpars;
909 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
911 cipher_param->cipher_length = op->sym->cipher.data.length;
912 cipher_param->cipher_offset = op->sym->cipher.data.offset;
913 if (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
914 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
915 if (unlikely((cipher_param->cipher_length % BYTE_LENGTH != 0) ||
916 (cipher_param->cipher_offset
917 % BYTE_LENGTH != 0))) {
918 PMD_DRV_LOG(ERR, " For Snow3g/Kasumi, QAT PMD only "
919 "supports byte aligned values");
920 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
923 cipher_param->cipher_length >>= 3;
924 cipher_param->cipher_offset >>= 3;
927 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
928 sizeof(cipher_param->u.cipher_IV_array))) {
929 rte_memcpy(cipher_param->u.cipher_IV_array,
930 op->sym->cipher.iv.data,
931 op->sym->cipher.iv.length);
933 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
934 qat_req->comn_hdr.serv_specif_flags,
935 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
936 cipher_param->u.s.cipher_IV_ptr = op->sym->cipher.iv.phys_addr;
938 if (op->sym->auth.digest.phys_addr) {
939 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
940 qat_req->comn_hdr.serv_specif_flags,
941 ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
942 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
944 auth_param->auth_off = op->sym->auth.data.offset;
945 auth_param->auth_len = op->sym->auth.data.length;
946 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
947 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0) ||
948 (auth_param->auth_len % BYTE_LENGTH != 0))) {
949 PMD_DRV_LOG(ERR, " For Snow3g, QAT PMD only "
950 "supports byte aligned values");
951 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
954 auth_param->auth_off >>= 3;
955 auth_param->auth_len >>= 3;
957 if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
958 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&
959 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
960 auth_param->auth_len = (auth_param->auth_len >> 3)
961 + (auth_param->auth_off >> 3)
964 auth_param->auth_off = 8;
965 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH
966 && ctx->qat_hash_alg ==
967 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
968 auth_param->auth_len = (auth_param->auth_len >> 3)
969 + (auth_param->auth_off >> 3)
970 + (BYTE_LENGTH >> 3);
971 auth_param->auth_off = 0;
973 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
975 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
976 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
977 if (op->sym->cipher.iv.length == 12) {
979 * For GCM a 12 bit IV is allowed,
980 * but we need to inform the f/w
982 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
983 qat_req->comn_hdr.serv_specif_flags,
984 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
988 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
989 rte_hexdump(stdout, "qat_req:", qat_req,
990 sizeof(struct icp_qat_fw_la_bulk_req));
991 rte_hexdump(stdout, "src_data:",
992 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
993 rte_pktmbuf_data_len(op->sym->m_src));
994 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
995 op->sym->cipher.iv.length);
996 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
997 op->sym->auth.digest.length);
998 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
999 op->sym->auth.aad.length);
1004 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1006 uint32_t div = data >> shift;
1007 uint32_t mult = div << shift;
1012 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1014 struct rte_cryptodev_sym_session *sess = sym_sess;
1015 struct qat_session *s = (void *)sess->_private;
1017 PMD_INIT_FUNC_TRACE();
1018 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1019 offsetof(struct qat_session, cd) +
1020 offsetof(struct rte_cryptodev_sym_session, _private);
1023 int qat_dev_config(__rte_unused struct rte_cryptodev *dev)
1025 PMD_INIT_FUNC_TRACE();
1029 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1031 PMD_INIT_FUNC_TRACE();
1035 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1037 PMD_INIT_FUNC_TRACE();
1040 int qat_dev_close(struct rte_cryptodev *dev)
1044 PMD_INIT_FUNC_TRACE();
1046 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1047 ret = qat_crypto_sym_qp_release(dev, i);
1055 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
1056 struct rte_cryptodev_info *info)
1058 struct qat_pmd_private *internals = dev->data->dev_private;
1060 PMD_INIT_FUNC_TRACE();
1062 info->max_nb_queue_pairs =
1063 ADF_NUM_SYM_QPS_PER_BUNDLE *
1064 ADF_NUM_BUNDLES_PER_DEV;
1065 info->feature_flags = dev->feature_flags;
1066 info->capabilities = qat_pmd_capabilities;
1067 info->sym.max_nb_sessions = internals->max_nb_sessions;
1068 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1072 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1073 struct rte_cryptodev_stats *stats)
1076 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1078 PMD_INIT_FUNC_TRACE();
1079 if (stats == NULL) {
1080 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1083 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1084 if (qp[i] == NULL) {
1085 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1089 stats->enqueued_count += qp[i]->stats.enqueued_count;
1090 stats->dequeued_count += qp[i]->stats.enqueued_count;
1091 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1092 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
1096 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1099 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1101 PMD_INIT_FUNC_TRACE();
1102 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1103 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1104 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");