4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _QAT_CRYPTO_H_
35 #define _QAT_CRYPTO_H_
37 #include <rte_cryptodev_pmd.h>
38 #include <rte_memzone.h>
40 #include "qat_crypto_capabilities.h"
42 #define CRYPTODEV_NAME_QAT_SYM_PMD crypto_qat
43 /**< Intel QAT Symmetric Crypto PMD device name */
46 * This macro rounds up a number to a be a multiple of
47 * the alignment when the alignment is a power of 2
49 #define ALIGN_POW2_ROUNDUP(num, align) \
50 (((num) + (align) - 1) & ~((align) - 1))
51 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
53 #define QAT_CSR_HEAD_WRITE_THRESH 32U
54 /* number of requests to accumulate before writing head CSR */
55 #define QAT_CSR_TAIL_WRITE_THRESH 32U
56 /* number of requests to accumulate before writing tail CSR */
57 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
58 /* number of inflights below which no tail write coalescing should occur */
68 * Structure associated with each queue.
71 char memz_name[RTE_MEMZONE_NAMESIZE];
72 void *base_addr; /* Base address */
73 phys_addr_t base_phys_addr; /* Queue physical address */
74 uint32_t head; /* Shadow copy of the head */
75 uint32_t tail; /* Shadow copy of the tail */
78 uint16_t max_inflights;
80 uint8_t hw_bundle_number;
81 uint8_t hw_queue_number;
82 /* HW queue aka ring offset on bundle */
83 uint32_t csr_head; /* last written head value */
84 uint32_t csr_tail; /* last written tail value */
85 uint16_t nb_processed_responses;
86 /* number of responses processed since last CSR head write */
87 uint16_t nb_pending_requests;
88 /* number of requests pending since last CSR tail write */
94 struct qat_queue tx_q;
95 struct qat_queue rx_q;
96 struct rte_cryptodev_stats stats;
97 struct rte_mempool *op_cookie_pool;
99 uint32_t nb_descriptors;
100 enum qat_device_gen qat_dev_gen;
101 } __rte_cache_aligned;
103 /** private data structure for each QAT device */
104 struct qat_pmd_private {
105 unsigned max_nb_queue_pairs;
106 /**< Max number of queue pairs supported by device */
107 unsigned max_nb_sessions;
108 /**< Max number of sessions supported by device */
109 enum qat_device_gen qat_dev_gen;
110 /**< QAT device generation */
111 const struct rte_cryptodev_capabilities *qat_dev_capabilities;
114 extern uint8_t cryptodev_qat_driver_id;
116 int qat_dev_config(struct rte_cryptodev *dev,
117 struct rte_cryptodev_config *config);
118 int qat_dev_start(struct rte_cryptodev *dev);
119 void qat_dev_stop(struct rte_cryptodev *dev);
120 int qat_dev_close(struct rte_cryptodev *dev);
121 void qat_dev_info_get(struct rte_cryptodev *dev,
122 struct rte_cryptodev_info *info);
124 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
125 struct rte_cryptodev_stats *stats);
126 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev);
128 int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
129 const struct rte_cryptodev_qp_conf *rx_conf, int socket_id,
130 struct rte_mempool *session_pool);
131 int qat_crypto_sym_qp_release(struct rte_cryptodev *dev,
132 uint16_t queue_pair_id);
135 qat_pmd_session_mempool_create(struct rte_cryptodev *dev,
136 unsigned nb_objs, unsigned obj_cache_size, int socket_id);
139 qat_crypto_sym_get_session_private_size(struct rte_cryptodev *dev);
142 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
143 struct rte_crypto_sym_xform *xform,
144 struct rte_cryptodev_sym_session *sess,
145 struct rte_mempool *mempool);
149 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
150 struct rte_crypto_sym_xform *xform, void *session_private);
153 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
154 struct qat_session *session);
157 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
158 struct rte_crypto_sym_xform *xform,
159 struct qat_session *session);
162 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
163 struct rte_crypto_sym_xform *xform,
164 struct qat_session *session);
168 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
169 struct rte_cryptodev_sym_session *session);
172 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
176 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
179 #endif /* _QAT_CRYPTO_H_ */