1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
8 #include <rte_cryptodev_pmd.h>
9 #include <rte_memzone.h>
11 #include "qat_common.h"
12 #include "qat_crypto_capabilities.h"
15 * This macro rounds up a number to a be a multiple of
16 * the alignment when the alignment is a power of 2
18 #define ALIGN_POW2_ROUNDUP(num, align) \
19 (((num) + (align) - 1) & ~((align) - 1))
20 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
22 #define QAT_CSR_HEAD_WRITE_THRESH 32U
23 /* number of requests to accumulate before writing head CSR */
24 #define QAT_CSR_TAIL_WRITE_THRESH 32U
25 /* number of requests to accumulate before writing tail CSR */
26 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
27 /* number of inflights below which no tail write coalescing should occur */
32 * Structure associated with each queue.
35 char memz_name[RTE_MEMZONE_NAMESIZE];
36 void *base_addr; /* Base address */
37 rte_iova_t base_phys_addr; /* Queue physical address */
38 uint32_t head; /* Shadow copy of the head */
39 uint32_t tail; /* Shadow copy of the tail */
42 uint16_t max_inflights;
44 uint8_t hw_bundle_number;
45 uint8_t hw_queue_number;
46 /* HW queue aka ring offset on bundle */
47 uint32_t csr_head; /* last written head value */
48 uint32_t csr_tail; /* last written tail value */
49 uint16_t nb_processed_responses;
50 /* number of responses processed since last CSR head write */
51 uint16_t nb_pending_requests;
52 /* number of requests pending since last CSR tail write */
58 struct qat_queue tx_q;
59 struct qat_queue rx_q;
60 struct rte_cryptodev_stats stats;
61 struct rte_mempool *op_cookie_pool;
63 uint32_t nb_descriptors;
64 enum qat_device_gen qat_dev_gen;
65 } __rte_cache_aligned;
67 /** private data structure for each QAT device */
68 struct qat_pmd_private {
69 unsigned max_nb_queue_pairs;
70 /**< Max number of queue pairs supported by device */
71 unsigned max_nb_sessions;
72 /**< Max number of sessions supported by device */
73 enum qat_device_gen qat_dev_gen;
74 /**< QAT device generation */
75 const struct rte_cryptodev_capabilities *qat_dev_capabilities;
78 extern uint8_t cryptodev_qat_driver_id;
80 int qat_dev_config(struct rte_cryptodev *dev,
81 struct rte_cryptodev_config *config);
82 int qat_dev_start(struct rte_cryptodev *dev);
83 void qat_dev_stop(struct rte_cryptodev *dev);
84 int qat_dev_close(struct rte_cryptodev *dev);
85 void qat_dev_info_get(struct rte_cryptodev *dev,
86 struct rte_cryptodev_info *info);
88 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
89 struct rte_cryptodev_stats *stats);
90 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev);
92 int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
93 const struct rte_cryptodev_qp_conf *rx_conf, int socket_id,
94 struct rte_mempool *session_pool);
95 int qat_crypto_sym_qp_release(struct rte_cryptodev *dev,
96 uint16_t queue_pair_id);
99 qat_pmd_session_mempool_create(struct rte_cryptodev *dev,
100 unsigned nb_objs, unsigned obj_cache_size, int socket_id);
103 qat_crypto_sym_get_session_private_size(struct rte_cryptodev *dev);
106 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
107 struct rte_crypto_sym_xform *xform,
108 struct rte_cryptodev_sym_session *sess,
109 struct rte_mempool *mempool);
113 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
114 struct rte_crypto_sym_xform *xform, void *session_private);
117 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
118 struct qat_session *session);
121 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
122 struct rte_crypto_sym_xform *xform,
123 struct qat_session *session);
126 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
127 struct rte_crypto_sym_xform *xform,
128 struct qat_session *session);
132 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
133 struct rte_cryptodev_sym_session *session);
136 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
140 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
143 #endif /* _QAT_CRYPTO_H_ */