drivers/crypto/qat/qat_crypto.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2016 Intel Corporation
   3  */
   4
   5 #ifndef _QAT_CRYPTO_H_
   6 #define _QAT_CRYPTO_H_
   7
   8 #include <rte_cryptodev_pmd.h>
   9 #include <rte_memzone.h>
  10
  11 #include "qat_crypto_capabilities.h"
  12
  13 #define CRYPTODEV_NAME_QAT_SYM_PMD      crypto_qat
  14 /**< Intel QAT Symmetric Crypto PMD device name */
  15
  16 /*
  17  * This macro rounds up a number to a be a multiple of
  18  * the alignment when the alignment is a power of 2
  19  */
  20 #define ALIGN_POW2_ROUNDUP(num, align) \
  21         (((num) + (align) - 1) & ~((align) - 1))
  22 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
  23
  24 #define QAT_CSR_HEAD_WRITE_THRESH 32U
  25 /* number of requests to accumulate before writing head CSR */
  26 #define QAT_CSR_TAIL_WRITE_THRESH 32U
  27 /* number of requests to accumulate before writing tail CSR */
  28 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
  29 /* number of inflights below which no tail write coalescing should occur */
  30
  31 struct qat_session;
  32
  33 enum qat_device_gen {
  34         QAT_GEN1 = 1,
  35         QAT_GEN2,
  36 };
  37
  38 /**
  39  * Structure associated with each queue.
  40  */
  41 struct qat_queue {
  42         char            memz_name[RTE_MEMZONE_NAMESIZE];
  43         void            *base_addr;             /* Base address */
  44         rte_iova_t      base_phys_addr;         /* Queue physical address */
  45         uint32_t        head;                   /* Shadow copy of the head */
  46         uint32_t        tail;                   /* Shadow copy of the tail */
  47         uint32_t        modulo;
  48         uint32_t        msg_size;
  49         uint16_t        max_inflights;
  50         uint32_t        queue_size;
  51         uint8_t         hw_bundle_number;
  52         uint8_t         hw_queue_number;
  53         /* HW queue aka ring offset on bundle */
  54         uint32_t        csr_head;               /* last written head value */
  55         uint32_t        csr_tail;               /* last written tail value */
  56         uint16_t        nb_processed_responses;
  57         /* number of responses processed since last CSR head write */
  58         uint16_t        nb_pending_requests;
  59         /* number of requests pending since last CSR tail write */
  60 };
  61
  62 struct qat_qp {
  63         void                    *mmap_bar_addr;
  64         uint16_t                inflights16;
  65         struct  qat_queue       tx_q;
  66         struct  qat_queue       rx_q;
  67         struct  rte_cryptodev_stats stats;
  68         struct rte_mempool *op_cookie_pool;
  69         void **op_cookies;
  70         uint32_t nb_descriptors;
  71         enum qat_device_gen qat_dev_gen;
  72 } __rte_cache_aligned;
  73
  74 /** private data structure for each QAT device */
  75 struct qat_pmd_private {
  76         unsigned max_nb_queue_pairs;
  77         /**< Max number of queue pairs supported by device */
  78         unsigned max_nb_sessions;
  79         /**< Max number of sessions supported by device */
  80         enum qat_device_gen qat_dev_gen;
  81         /**< QAT device generation */
  82         const struct rte_cryptodev_capabilities *qat_dev_capabilities;
  83 };
  84
  85 extern uint8_t cryptodev_qat_driver_id;
  86
  87 int qat_dev_config(struct rte_cryptodev *dev,
  88                 struct rte_cryptodev_config *config);
  89 int qat_dev_start(struct rte_cryptodev *dev);
  90 void qat_dev_stop(struct rte_cryptodev *dev);
  91 int qat_dev_close(struct rte_cryptodev *dev);
  92 void qat_dev_info_get(struct rte_cryptodev *dev,
  93         struct rte_cryptodev_info *info);
  94
  95 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
  96         struct rte_cryptodev_stats *stats);
  97 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev);
  98
  99 int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
 100         const struct rte_cryptodev_qp_conf *rx_conf, int socket_id,
 101         struct rte_mempool *session_pool);
 102 int qat_crypto_sym_qp_release(struct rte_cryptodev *dev,
 103         uint16_t queue_pair_id);
 104
 105 int
 106 qat_pmd_session_mempool_create(struct rte_cryptodev *dev,
 107         unsigned nb_objs, unsigned obj_cache_size, int socket_id);
 108
 109 extern unsigned
 110 qat_crypto_sym_get_session_private_size(struct rte_cryptodev *dev);
 111
 112 extern int
 113 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
 114                 struct rte_crypto_sym_xform *xform,
 115                 struct rte_cryptodev_sym_session *sess,
 116                 struct rte_mempool *mempool);
 117
 118
 119 int
 120 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
 121                 struct rte_crypto_sym_xform *xform, void *session_private);
 122
 123 int
 124 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
 125                                 struct qat_session *session);
 126
 127 int
 128 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
 129                                 struct rte_crypto_sym_xform *xform,
 130                                 struct qat_session *session);
 131
 132 int
 133 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
 134                 struct rte_crypto_sym_xform *xform,
 135                 struct qat_session *session);
 136
 137
 138 extern void
 139 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
 140                 struct rte_cryptodev_sym_session *session);
 141
 142 extern uint16_t
 143 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 144                 uint16_t nb_ops);
 145
 146 extern uint16_t
 147 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 148                 uint16_t nb_ops);
 149
 150 #endif /* _QAT_CRYPTO_H_ */