drivers/crypto/qat/qat_qp.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_common.h>
   6 #include <rte_dev.h>
   7 #include <rte_malloc.h>
   8 #include <rte_memzone.h>
   9 #include <rte_pci.h>
  10 #include <rte_bus_pci.h>
  11 #include <rte_atomic.h>
  12 #include <rte_prefetch.h>
  13
  14 #include "qat_logs.h"
  15 #include "qat_device.h"
  16 #include "qat_qp.h"
  17 #include "adf_transport_access_macros.h"
  18
  19
  20 #define ADF_MAX_DESC                            4096
  21 #define ADF_MIN_DESC                            128
  22
  23 #define ADF_ARB_REG_SLOT                        0x1000
  24 #define ADF_ARB_RINGSRVARBEN_OFFSET             0x19C
  25
  26 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
  27         ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
  28         (ADF_ARB_REG_SLOT * index), value)
  29
  30 __extension__
  31 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
  32                                          [ADF_MAX_QPS_ON_ANY_SERVICE] = {
  33         /* queue pairs which provide an asymmetric crypto service */
  34         [QAT_SERVICE_ASYMMETRIC] = {
  35                 {
  36                         .service_type = QAT_SERVICE_ASYMMETRIC,
  37                         .hw_bundle_num = 0,
  38                         .tx_ring_num = 0,
  39                         .rx_ring_num = 8,
  40                         .tx_msg_size = 64,
  41                         .rx_msg_size = 32,
  42
  43                 }, {
  44                         .service_type = QAT_SERVICE_ASYMMETRIC,
  45                         .hw_bundle_num = 0,
  46                         .tx_ring_num = 1,
  47                         .rx_ring_num = 9,
  48                         .tx_msg_size = 64,
  49                         .rx_msg_size = 32,
  50                 }
  51         },
  52         /* queue pairs which provide a symmetric crypto service */
  53         [QAT_SERVICE_SYMMETRIC] = {
  54                 {
  55                         .service_type = QAT_SERVICE_SYMMETRIC,
  56                         .hw_bundle_num = 0,
  57                         .tx_ring_num = 2,
  58                         .rx_ring_num = 10,
  59                         .tx_msg_size = 128,
  60                         .rx_msg_size = 32,
  61                 },
  62                 {
  63                         .service_type = QAT_SERVICE_SYMMETRIC,
  64                         .hw_bundle_num = 0,
  65                         .tx_ring_num = 3,
  66                         .rx_ring_num = 11,
  67                         .tx_msg_size = 128,
  68                         .rx_msg_size = 32,
  69                 }
  70         },
  71         /* queue pairs which provide a compression service */
  72         [QAT_SERVICE_COMPRESSION] = {
  73                 {
  74                         .service_type = QAT_SERVICE_COMPRESSION,
  75                         .hw_bundle_num = 0,
  76                         .tx_ring_num = 6,
  77                         .rx_ring_num = 14,
  78                         .tx_msg_size = 128,
  79                         .rx_msg_size = 32,
  80                 }, {
  81                         .service_type = QAT_SERVICE_COMPRESSION,
  82                         .hw_bundle_num = 0,
  83                         .tx_ring_num = 7,
  84                         .rx_ring_num = 15,
  85                         .tx_msg_size = 128,
  86                         .rx_msg_size = 32,
  87                 }
  88         }
  89 };
  90
  91 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
  92         uint32_t queue_size_bytes);
  93 static void qat_queue_delete(struct qat_queue *queue);
  94 static int qat_queue_create(struct qat_pci_device *qat_dev,
  95         struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
  96 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
  97         uint32_t *queue_size_for_csr);
  98 static void adf_configure_queues(struct qat_qp *queue);
  99 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
 100         rte_spinlock_t *lock);
 101 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
 102         rte_spinlock_t *lock);
 103
 104
 105 int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 106                 enum qat_service_type service)
 107 {
 108         int i, count;
 109
 110         for (i = 0, count = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++)
 111                 if (qp_hw_data[i].service_type == service)
 112                         count++;
 113         return count;
 114 }
 115
 116 static const struct rte_memzone *
 117 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
 118                         int socket_id)
 119 {
 120         const struct rte_memzone *mz;
 121
 122         PMD_INIT_FUNC_TRACE();
 123         mz = rte_memzone_lookup(queue_name);
 124         if (mz != 0) {
 125                 if (((size_t)queue_size <= mz->len) &&
 126                                 ((socket_id == SOCKET_ID_ANY) ||
 127                                         (socket_id == mz->socket_id))) {
 128                         PMD_DRV_LOG(DEBUG, "re-use memzone already "
 129                                         "allocated for %s", queue_name);
 130                         return mz;
 131                 }
 132
 133                 PMD_DRV_LOG(ERR, "Incompatible memzone already "
 134                                 "allocated %s, size %u, socket %d. "
 135                                 "Requested size %u, socket %u",
 136                                 queue_name, (uint32_t)mz->len,
 137                                 mz->socket_id, queue_size, socket_id);
 138                 return NULL;
 139         }
 140
 141         PMD_DRV_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
 142                                         queue_name, queue_size, socket_id);
 143         return rte_memzone_reserve_aligned(queue_name, queue_size,
 144                 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
 145 }
 146
 147 int qat_qp_setup(struct qat_pci_device *qat_dev,
 148                 struct qat_qp **qp_addr,
 149                 uint16_t queue_pair_id,
 150                 struct qat_qp_config *qat_qp_conf)
 151
 152 {
 153         struct qat_qp *qp;
 154         struct rte_pci_device *pci_dev = qat_dev->pci_dev;
 155         char op_cookie_pool_name[RTE_RING_NAMESIZE];
 156         uint32_t i;
 157
 158         PMD_DRV_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
 159                 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
 160
 161         if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
 162                 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
 163                 PMD_DRV_LOG(ERR, "Can't create qp for %u descriptors",
 164                                 qat_qp_conf->nb_descriptors);
 165                 return -EINVAL;
 166         }
 167
 168         if (pci_dev->mem_resource[0].addr == NULL) {
 169                 PMD_DRV_LOG(ERR, "Could not find VF config space "
 170                                 "(UIO driver attached?).");
 171                 return -EINVAL;
 172         }
 173
 174         /* Allocate the queue pair data structure. */
 175         qp = rte_zmalloc("qat PMD qp metadata",
 176                         sizeof(*qp), RTE_CACHE_LINE_SIZE);
 177         if (qp == NULL) {
 178                 PMD_DRV_LOG(ERR, "Failed to alloc mem for qp struct");
 179                 return -ENOMEM;
 180         }
 181         qp->nb_descriptors = qat_qp_conf->nb_descriptors;
 182         qp->op_cookies = rte_zmalloc("qat PMD op cookie pointer",
 183                         qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
 184                         RTE_CACHE_LINE_SIZE);
 185         if (qp->op_cookies == NULL) {
 186                 PMD_DRV_LOG(ERR, "Failed to alloc mem for cookie");
 187                 rte_free(qp);
 188                 return -ENOMEM;
 189         }
 190
 191         qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
 192         qp->inflights16 = 0;
 193
 194         if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
 195                                         ADF_RING_DIR_TX) != 0) {
 196                 PMD_INIT_LOG(ERR, "Tx queue create failed "
 197                                 "queue_pair_id=%u", queue_pair_id);
 198                 goto create_err;
 199         }
 200
 201         if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
 202                                         ADF_RING_DIR_RX) != 0) {
 203                 PMD_DRV_LOG(ERR, "Rx queue create failed "
 204                                 "queue_pair_id=%hu", queue_pair_id);
 205                 qat_queue_delete(&(qp->tx_q));
 206                 goto create_err;
 207         }
 208
 209         adf_configure_queues(qp);
 210         adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr,
 211                                         &qat_dev->arb_csr_lock);
 212
 213         snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
 214                                         "%s%d_cookies_%s_qp%hu",
 215                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 216                 qat_qp_conf->service_str, queue_pair_id);
 217
 218         PMD_DRV_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
 219         qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
 220         if (qp->op_cookie_pool == NULL)
 221                 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
 222                                 qp->nb_descriptors,
 223                                 qat_qp_conf->cookie_size, 64, 0,
 224                                 NULL, NULL, NULL, NULL, qat_qp_conf->socket_id,
 225                                 0);
 226         if (!qp->op_cookie_pool) {
 227                 PMD_DRV_LOG(ERR, "QAT PMD Cannot create"
 228                                 " op mempool");
 229                 goto create_err;
 230         }
 231
 232         for (i = 0; i < qp->nb_descriptors; i++) {
 233                 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
 234                         PMD_DRV_LOG(ERR, "QAT PMD Cannot get op_cookie");
 235                         goto create_err;
 236                 }
 237         }
 238
 239         qp->qat_dev_gen = qat_dev->qat_dev_gen;
 240         qp->build_request = qat_qp_conf->build_request;
 241         qp->process_response = qat_qp_conf->process_response;
 242         qp->qat_dev = qat_dev;
 243
 244         PMD_DRV_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
 245                         queue_pair_id, op_cookie_pool_name);
 246
 247         *qp_addr = qp;
 248         return 0;
 249
 250 create_err:
 251         if (qp->op_cookie_pool)
 252                 rte_mempool_free(qp->op_cookie_pool);
 253         rte_free(qp->op_cookies);
 254         rte_free(qp);
 255         return -EFAULT;
 256 }
 257
 258 int qat_qp_release(struct qat_qp **qp_addr)
 259 {
 260         struct qat_qp *qp = *qp_addr;
 261         uint32_t i;
 262
 263         PMD_INIT_FUNC_TRACE();
 264         if (qp == NULL) {
 265                 PMD_DRV_LOG(DEBUG, "qp already freed");
 266                 return 0;
 267         }
 268
 269         PMD_DRV_LOG(DEBUG, "Free qp on qat_pci device %d",
 270                                 qp->qat_dev->qat_dev_id);
 271
 272         /* Don't free memory if there are still responses to be processed */
 273         if (qp->inflights16 == 0) {
 274                 qat_queue_delete(&(qp->tx_q));
 275                 qat_queue_delete(&(qp->rx_q));
 276         } else {
 277                 return -EAGAIN;
 278         }
 279
 280         adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr,
 281                                         &qp->qat_dev->arb_csr_lock);
 282
 283         for (i = 0; i < qp->nb_descriptors; i++)
 284                 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
 285
 286         if (qp->op_cookie_pool)
 287                 rte_mempool_free(qp->op_cookie_pool);
 288
 289         rte_free(qp->op_cookies);
 290         rte_free(qp);
 291         *qp_addr = NULL;
 292         return 0;
 293 }
 294
 295
 296 static void qat_queue_delete(struct qat_queue *queue)
 297 {
 298         const struct rte_memzone *mz;
 299         int status = 0;
 300
 301         if (queue == NULL) {
 302                 PMD_DRV_LOG(DEBUG, "Invalid queue");
 303                 return;
 304         }
 305         PMD_DRV_LOG(DEBUG, "Free ring %d, memzone: %s",
 306                         queue->hw_queue_number, queue->memz_name);
 307
 308         mz = rte_memzone_lookup(queue->memz_name);
 309         if (mz != NULL) {
 310                 /* Write an unused pattern to the queue memory. */
 311                 memset(queue->base_addr, 0x7F, queue->queue_size);
 312                 status = rte_memzone_free(mz);
 313                 if (status != 0)
 314                         PMD_DRV_LOG(ERR, "Error %d on freeing queue %s",
 315                                         status, queue->memz_name);
 316         } else {
 317                 PMD_DRV_LOG(DEBUG, "queue %s doesn't exist",
 318                                 queue->memz_name);
 319         }
 320 }
 321
 322 static int
 323 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
 324                 struct qat_qp_config *qp_conf, uint8_t dir)
 325 {
 326         uint64_t queue_base;
 327         void *io_addr;
 328         const struct rte_memzone *qp_mz;
 329         struct rte_pci_device *pci_dev = qat_dev->pci_dev;
 330         int ret = 0;
 331         uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
 332                         qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
 333         uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
 334
 335         queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
 336         queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
 337                         qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
 338
 339         if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
 340                 PMD_DRV_LOG(ERR, "Invalid descriptor size %d", desc_size);
 341                 return -EINVAL;
 342         }
 343
 344         /*
 345          * Allocate a memzone for the queue - create a unique name.
 346          */
 347         snprintf(queue->memz_name, sizeof(queue->memz_name),
 348                         "%s_%d_%s_%s_%d_%d",
 349                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 350                 qp_conf->service_str, "qp_mem",
 351                 queue->hw_bundle_number, queue->hw_queue_number);
 352         qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
 353                         qp_conf->socket_id);
 354         if (qp_mz == NULL) {
 355                 PMD_DRV_LOG(ERR, "Failed to allocate ring memzone");
 356                 return -ENOMEM;
 357         }
 358
 359         queue->base_addr = (char *)qp_mz->addr;
 360         queue->base_phys_addr = qp_mz->iova;
 361         if (qat_qp_check_queue_alignment(queue->base_phys_addr,
 362                         queue_size_bytes)) {
 363                 PMD_DRV_LOG(ERR, "Invalid alignment on queue create "
 364                                         " 0x%"PRIx64"\n",
 365                                         queue->base_phys_addr);
 366                 ret = -EFAULT;
 367                 goto queue_create_err;
 368         }
 369
 370         if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
 371                         &(queue->queue_size)) != 0) {
 372                 PMD_DRV_LOG(ERR, "Invalid num inflights");
 373                 ret = -EINVAL;
 374                 goto queue_create_err;
 375         }
 376
 377         queue->max_inflights = ADF_MAX_INFLIGHTS(queue->queue_size,
 378                                         ADF_BYTES_TO_MSG_SIZE(desc_size));
 379         queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
 380
 381         if (queue->max_inflights < 2) {
 382                 PMD_DRV_LOG(ERR, "Invalid num inflights");
 383                 ret = -EINVAL;
 384                 goto queue_create_err;
 385         }
 386         queue->head = 0;
 387         queue->tail = 0;
 388         queue->msg_size = desc_size;
 389
 390         /*
 391          * Write an unused pattern to the queue memory.
 392          */
 393         memset(queue->base_addr, 0x7F, queue_size_bytes);
 394
 395         queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
 396                                         queue->queue_size);
 397
 398         io_addr = pci_dev->mem_resource[0].addr;
 399
 400         WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
 401                         queue->hw_queue_number, queue_base);
 402
 403         PMD_DRV_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
 404                 " nb msgs %u, msg_size %u, max_inflights %u modulo mask %u",
 405                         queue->memz_name,
 406                         queue->queue_size, queue_size_bytes,
 407                         qp_conf->nb_descriptors, desc_size,
 408                         queue->max_inflights, queue->modulo_mask);
 409
 410         return 0;
 411
 412 queue_create_err:
 413         rte_memzone_free(qp_mz);
 414         return ret;
 415 }
 416
 417 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
 418                                         uint32_t queue_size_bytes)
 419 {
 420         PMD_INIT_FUNC_TRACE();
 421         if (((queue_size_bytes - 1) & phys_addr) != 0)
 422                 return -EINVAL;
 423         return 0;
 424 }
 425
 426 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
 427         uint32_t *p_queue_size_for_csr)
 428 {
 429         uint8_t i = ADF_MIN_RING_SIZE;
 430
 431         PMD_INIT_FUNC_TRACE();
 432         for (; i <= ADF_MAX_RING_SIZE; i++)
 433                 if ((msg_size * msg_num) ==
 434                                 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
 435                         *p_queue_size_for_csr = i;
 436                         return 0;
 437                 }
 438         PMD_DRV_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
 439         return -EINVAL;
 440 }
 441
 442 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
 443                                         rte_spinlock_t *lock)
 444 {
 445         uint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +
 446                                         (ADF_ARB_REG_SLOT *
 447                                                         txq->hw_bundle_number);
 448         uint32_t value;
 449
 450         PMD_INIT_FUNC_TRACE();
 451
 452         rte_spinlock_lock(lock);
 453         value = ADF_CSR_RD(base_addr, arb_csr_offset);
 454         value |= (0x01 << txq->hw_queue_number);
 455         ADF_CSR_WR(base_addr, arb_csr_offset, value);
 456         rte_spinlock_unlock(lock);
 457 }
 458
 459 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
 460                                         rte_spinlock_t *lock)
 461 {
 462         uint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +
 463                                         (ADF_ARB_REG_SLOT *
 464                                                         txq->hw_bundle_number);
 465         uint32_t value;
 466
 467         PMD_INIT_FUNC_TRACE();
 468
 469         rte_spinlock_lock(lock);
 470         value = ADF_CSR_RD(base_addr, arb_csr_offset);
 471         value &= ~(0x01 << txq->hw_queue_number);
 472         ADF_CSR_WR(base_addr, arb_csr_offset, value);
 473         rte_spinlock_unlock(lock);
 474 }
 475
 476 static void adf_configure_queues(struct qat_qp *qp)
 477 {
 478         uint32_t queue_config;
 479         struct qat_queue *queue = &qp->tx_q;
 480
 481         PMD_INIT_FUNC_TRACE();
 482         queue_config = BUILD_RING_CONFIG(queue->queue_size);
 483
 484         WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
 485                         queue->hw_queue_number, queue_config);
 486
 487         queue = &qp->rx_q;
 488         queue_config =
 489                         BUILD_RESP_RING_CONFIG(queue->queue_size,
 490                                         ADF_RING_NEAR_WATERMARK_512,
 491                                         ADF_RING_NEAR_WATERMARK_0);
 492
 493         WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
 494                         queue->hw_queue_number, queue_config);
 495 }
 496
 497 static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)
 498 {
 499         return data & modulo_mask;
 500 }
 501
 502 static inline void
 503 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
 504         WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
 505                         q->hw_queue_number, q->tail);
 506         q->nb_pending_requests = 0;
 507         q->csr_tail = q->tail;
 508 }
 509
 510 static inline
 511 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
 512 {
 513         uint32_t old_head, new_head;
 514         uint32_t max_head;
 515
 516         old_head = q->csr_head;
 517         new_head = q->head;
 518         max_head = qp->nb_descriptors * q->msg_size;
 519
 520         /* write out free descriptors */
 521         void *cur_desc = (uint8_t *)q->base_addr + old_head;
 522
 523         if (new_head < old_head) {
 524                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
 525                 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
 526         } else {
 527                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
 528         }
 529         q->nb_processed_responses = 0;
 530         q->csr_head = new_head;
 531
 532         /* write current head to CSR */
 533         WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
 534                             q->hw_queue_number, new_head);
 535 }
 536
 537 uint16_t
 538 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 539 {
 540         register struct qat_queue *queue;
 541         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 542         register uint32_t nb_ops_sent = 0;
 543         register int ret;
 544         uint16_t nb_ops_possible = nb_ops;
 545         register uint8_t *base_addr;
 546         register uint32_t tail;
 547         int overflow;
 548
 549         if (unlikely(nb_ops == 0))
 550                 return 0;
 551
 552         /* read params used a lot in main loop into registers */
 553         queue = &(tmp_qp->tx_q);
 554         base_addr = (uint8_t *)queue->base_addr;
 555         tail = queue->tail;
 556
 557         /* Find how many can actually fit on the ring */
 558         tmp_qp->inflights16 += nb_ops;
 559         overflow = tmp_qp->inflights16 - queue->max_inflights;
 560         if (overflow > 0) {
 561                 tmp_qp->inflights16 -= overflow;
 562                 nb_ops_possible = nb_ops - overflow;
 563                 if (nb_ops_possible == 0)
 564                         return 0;
 565         }
 566
 567         while (nb_ops_sent != nb_ops_possible) {
 568                 ret = tmp_qp->build_request(*ops, base_addr + tail,
 569                                 tmp_qp->op_cookies[tail / queue->msg_size],
 570                                 tmp_qp->qat_dev_gen);
 571                 if (ret != 0) {
 572                         tmp_qp->stats.enqueue_err_count++;
 573                         /*
 574                          * This message cannot be enqueued,
 575                          * decrease number of ops that wasn't sent
 576                          */
 577                         tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
 578                         if (nb_ops_sent == 0)
 579                                 return 0;
 580                         goto kick_tail;
 581                 }
 582
 583                 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
 584                 ops++;
 585                 nb_ops_sent++;
 586         }
 587 kick_tail:
 588         queue->tail = tail;
 589         tmp_qp->stats.enqueued_count += nb_ops_sent;
 590         queue->nb_pending_requests += nb_ops_sent;
 591         if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
 592                     queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
 593                 txq_write_tail(tmp_qp, queue);
 594         }
 595         return nb_ops_sent;
 596 }
 597
 598 uint16_t
 599 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 600 {
 601         struct qat_queue *rx_queue, *tx_queue;
 602         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 603         uint32_t head;
 604         uint32_t resp_counter = 0;
 605         uint8_t *resp_msg;
 606
 607         rx_queue = &(tmp_qp->rx_q);
 608         tx_queue = &(tmp_qp->tx_q);
 609         head = rx_queue->head;
 610         resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
 611
 612         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 613                         resp_counter != nb_ops) {
 614
 615                 tmp_qp->process_response(ops, resp_msg);
 616
 617                 head = adf_modulo(head + rx_queue->msg_size,
 618                                   rx_queue->modulo_mask);
 619
 620                 resp_msg = (uint8_t *)rx_queue->base_addr + head;
 621                 ops++;
 622                 resp_counter++;
 623         }
 624         if (resp_counter > 0) {
 625                 rx_queue->head = head;
 626                 tmp_qp->stats.dequeued_count += resp_counter;
 627                 rx_queue->nb_processed_responses += resp_counter;
 628                 tmp_qp->inflights16 -= resp_counter;
 629
 630                 if (rx_queue->nb_processed_responses >
 631                                                 QAT_CSR_HEAD_WRITE_THRESH)
 632                         rxq_free_desc(tmp_qp, rx_queue);
 633         }
 634         /* also check if tail needs to be advanced */
 635         if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
 636                 tx_queue->tail != tx_queue->csr_tail) {
 637                 txq_write_tail(tmp_qp, tx_queue);
 638         }
 639         return resp_counter;
 640 }