drivers/crypto/qat/qat_qp.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_common.h>
   6 #include <rte_dev.h>
   7 #include <rte_malloc.h>
   8 #include <rte_memzone.h>
   9 #include <rte_pci.h>
  10 #include <rte_bus_pci.h>
  11 #include <rte_atomic.h>
  12 #include <rte_prefetch.h>
  13
  14 #include "qat_logs.h"
  15 #include "qat_qp.h"
  16 #include "qat_device.h"
  17 #include "adf_transport_access_macros.h"
  18
  19
  20 #define ADF_MAX_DESC                            4096
  21 #define ADF_MIN_DESC                            128
  22
  23 #define ADF_ARB_REG_SLOT                        0x1000
  24 #define ADF_ARB_RINGSRVARBEN_OFFSET             0x19C
  25
  26 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
  27         ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
  28         (ADF_ARB_REG_SLOT * index), value)
  29
  30 __extension__
  31 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
  32                                          [ADF_MAX_QPS_PER_BUNDLE] = {
  33         /* queue pairs which provide an asymmetric crypto service */
  34         [QAT_SERVICE_ASYMMETRIC] = {
  35                 {
  36                         .service_type = QAT_SERVICE_ASYMMETRIC,
  37                         .hw_bundle_num = 0,
  38                         .tx_ring_num = 0,
  39                         .rx_ring_num = 8,
  40                         .tx_msg_size = 64,
  41                         .rx_msg_size = 32,
  42
  43                 }, {
  44                         .service_type = QAT_SERVICE_ASYMMETRIC,
  45                         .tx_ring_num = 1,
  46                         .rx_ring_num = 9,
  47                         .tx_msg_size = 64,
  48                         .rx_msg_size = 32,
  49                 }, {
  50                         .service_type = QAT_SERVICE_INVALID,
  51                 }, {
  52                         .service_type = QAT_SERVICE_INVALID,
  53                 }
  54         },
  55         /* queue pairs which provide a symmetric crypto service */
  56         [QAT_SERVICE_SYMMETRIC] = {
  57                 {
  58                         .service_type = QAT_SERVICE_SYMMETRIC,
  59                         .hw_bundle_num = 0,
  60                         .tx_ring_num = 2,
  61                         .rx_ring_num = 10,
  62                         .tx_msg_size = 128,
  63                         .rx_msg_size = 32,
  64                 },
  65                 {
  66                         .service_type = QAT_SERVICE_SYMMETRIC,
  67                         .hw_bundle_num = 0,
  68                         .tx_ring_num = 3,
  69                         .rx_ring_num = 11,
  70                         .tx_msg_size = 128,
  71                         .rx_msg_size = 32,
  72                 }, {
  73                         .service_type = QAT_SERVICE_INVALID,
  74                 }, {
  75                         .service_type = QAT_SERVICE_INVALID,
  76                 }
  77         },
  78         /* queue pairs which provide a compression service */
  79         [QAT_SERVICE_COMPRESSION] = {
  80                 {
  81                         .service_type = QAT_SERVICE_COMPRESSION,
  82                         .hw_bundle_num = 0,
  83                         .tx_ring_num = 6,
  84                         .rx_ring_num = 14,
  85                         .tx_msg_size = 128,
  86                         .rx_msg_size = 32,
  87                 }, {
  88                         .service_type = QAT_SERVICE_COMPRESSION,
  89                         .hw_bundle_num = 0,
  90                         .tx_ring_num = 7,
  91                         .rx_ring_num = 15,
  92                         .tx_msg_size = 128,
  93                         .rx_msg_size = 32,
  94                 }, {
  95                         .service_type = QAT_SERVICE_INVALID,
  96                 }, {
  97                         .service_type = QAT_SERVICE_INVALID,
  98                 }
  99         }
 100 };
 101
 102 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
 103         uint32_t queue_size_bytes);
 104 static void qat_queue_delete(struct qat_queue *queue);
 105 static int qat_queue_create(struct qat_pci_device *qat_dev,
 106         struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
 107 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
 108         uint32_t *queue_size_for_csr);
 109 static void adf_configure_queues(struct qat_qp *queue);
 110 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr);
 111 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr);
 112
 113
 114 int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 115                 enum qat_service_type service)
 116 {
 117         int i, count;
 118
 119         for (i = 0, count = 0; i < ADF_MAX_QPS_PER_BUNDLE; i++)
 120                 if (qp_hw_data[i].service_type == service)
 121                         count++;
 122         return count * ADF_NUM_BUNDLES_PER_DEV;
 123 }
 124
 125 static const struct rte_memzone *
 126 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
 127                         int socket_id)
 128 {
 129         const struct rte_memzone *mz;
 130
 131         PMD_INIT_FUNC_TRACE();
 132         mz = rte_memzone_lookup(queue_name);
 133         if (mz != 0) {
 134                 if (((size_t)queue_size <= mz->len) &&
 135                                 ((socket_id == SOCKET_ID_ANY) ||
 136                                         (socket_id == mz->socket_id))) {
 137                         PMD_DRV_LOG(DEBUG, "re-use memzone already "
 138                                         "allocated for %s", queue_name);
 139                         return mz;
 140                 }
 141
 142                 PMD_DRV_LOG(ERR, "Incompatible memzone already "
 143                                 "allocated %s, size %u, socket %d. "
 144                                 "Requested size %u, socket %u",
 145                                 queue_name, (uint32_t)mz->len,
 146                                 mz->socket_id, queue_size, socket_id);
 147                 return NULL;
 148         }
 149
 150         PMD_DRV_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
 151                                         queue_name, queue_size, socket_id);
 152         return rte_memzone_reserve_aligned(queue_name, queue_size,
 153                 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
 154 }
 155
 156 int qat_qp_setup(struct qat_pci_device *qat_dev,
 157                 struct qat_qp **qp_addr,
 158                 uint16_t queue_pair_id,
 159                 struct qat_qp_config *qat_qp_conf)
 160
 161 {
 162         struct qat_qp *qp;
 163         struct rte_pci_device *pci_dev = qat_dev->pci_dev;
 164         char op_cookie_pool_name[RTE_RING_NAMESIZE];
 165         uint32_t i;
 166
 167         PMD_DRV_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
 168                 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
 169
 170         if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
 171                 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
 172                 PMD_DRV_LOG(ERR, "Can't create qp for %u descriptors",
 173                                 qat_qp_conf->nb_descriptors);
 174                 return -EINVAL;
 175         }
 176
 177         if (pci_dev->mem_resource[0].addr == NULL) {
 178                 PMD_DRV_LOG(ERR, "Could not find VF config space "
 179                                 "(UIO driver attached?).");
 180                 return -EINVAL;
 181         }
 182
 183         /* Allocate the queue pair data structure. */
 184         qp = rte_zmalloc("qat PMD qp metadata",
 185                         sizeof(*qp), RTE_CACHE_LINE_SIZE);
 186         if (qp == NULL) {
 187                 PMD_DRV_LOG(ERR, "Failed to alloc mem for qp struct");
 188                 return -ENOMEM;
 189         }
 190         qp->nb_descriptors = qat_qp_conf->nb_descriptors;
 191         qp->op_cookies = rte_zmalloc("qat PMD op cookie pointer",
 192                         qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
 193                         RTE_CACHE_LINE_SIZE);
 194         if (qp->op_cookies == NULL) {
 195                 PMD_DRV_LOG(ERR, "Failed to alloc mem for cookie");
 196                 rte_free(qp);
 197                 return -ENOMEM;
 198         }
 199
 200         qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
 201         qp->inflights16 = 0;
 202
 203         if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
 204                                         ADF_RING_DIR_TX) != 0) {
 205                 PMD_INIT_LOG(ERR, "Tx queue create failed "
 206                                 "queue_pair_id=%u", queue_pair_id);
 207                 goto create_err;
 208         }
 209
 210         if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
 211                                         ADF_RING_DIR_RX) != 0) {
 212                 PMD_DRV_LOG(ERR, "Rx queue create failed "
 213                                 "queue_pair_id=%hu", queue_pair_id);
 214                 qat_queue_delete(&(qp->tx_q));
 215                 goto create_err;
 216         }
 217
 218         adf_configure_queues(qp);
 219         adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr);
 220
 221         snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
 222                                         "%s%d_cookies_%s_qp%hu",
 223                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 224                 qat_qp_conf->service_str, queue_pair_id);
 225
 226         PMD_DRV_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
 227         qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
 228         if (qp->op_cookie_pool == NULL)
 229                 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
 230                                 qp->nb_descriptors,
 231                                 qat_qp_conf->cookie_size, 64, 0,
 232                                 NULL, NULL, NULL, NULL, qat_qp_conf->socket_id,
 233                                 0);
 234         if (!qp->op_cookie_pool) {
 235                 PMD_DRV_LOG(ERR, "QAT PMD Cannot create"
 236                                 " op mempool");
 237                 goto create_err;
 238         }
 239
 240         for (i = 0; i < qp->nb_descriptors; i++) {
 241                 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
 242                         PMD_DRV_LOG(ERR, "QAT PMD Cannot get op_cookie");
 243                         goto create_err;
 244                 }
 245         }
 246
 247         qp->qat_dev_gen = qat_dev->qat_dev_gen;
 248         qp->build_request = qat_qp_conf->build_request;
 249         qp->process_response = qat_qp_conf->process_response;
 250         qp->qat_dev = qat_dev;
 251
 252         PMD_DRV_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
 253                         queue_pair_id, op_cookie_pool_name);
 254
 255         *qp_addr = qp;
 256         return 0;
 257
 258 create_err:
 259         rte_free(qp);
 260         return -EFAULT;
 261 }
 262
 263 int qat_qp_release(struct qat_qp **qp_addr)
 264 {
 265         struct qat_qp *qp = *qp_addr;
 266         uint32_t i;
 267
 268         PMD_INIT_FUNC_TRACE();
 269         if (qp == NULL) {
 270                 PMD_DRV_LOG(DEBUG, "qp already freed");
 271                 return 0;
 272         }
 273
 274         PMD_DRV_LOG(DEBUG, "Free qp on qat_pci device %d",
 275                                 qp->qat_dev->qat_dev_id);
 276
 277         /* Don't free memory if there are still responses to be processed */
 278         if (qp->inflights16 == 0) {
 279                 qat_queue_delete(&(qp->tx_q));
 280                 qat_queue_delete(&(qp->rx_q));
 281         } else {
 282                 return -EAGAIN;
 283         }
 284
 285         adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr);
 286
 287         for (i = 0; i < qp->nb_descriptors; i++)
 288                 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
 289
 290         if (qp->op_cookie_pool)
 291                 rte_mempool_free(qp->op_cookie_pool);
 292
 293         rte_free(qp->op_cookies);
 294         rte_free(qp);
 295         *qp_addr = NULL;
 296         return 0;
 297 }
 298
 299
 300 static void qat_queue_delete(struct qat_queue *queue)
 301 {
 302         const struct rte_memzone *mz;
 303         int status = 0;
 304
 305         if (queue == NULL) {
 306                 PMD_DRV_LOG(DEBUG, "Invalid queue");
 307                 return;
 308         }
 309         PMD_DRV_LOG(DEBUG, "Free ring %d, memzone: %s",
 310                         queue->hw_queue_number, queue->memz_name);
 311
 312         mz = rte_memzone_lookup(queue->memz_name);
 313         if (mz != NULL) {
 314                 /* Write an unused pattern to the queue memory. */
 315                 memset(queue->base_addr, 0x7F, queue->queue_size);
 316                 status = rte_memzone_free(mz);
 317                 if (status != 0)
 318                         PMD_DRV_LOG(ERR, "Error %d on freeing queue %s",
 319                                         status, queue->memz_name);
 320         } else {
 321                 PMD_DRV_LOG(DEBUG, "queue %s doesn't exist",
 322                                 queue->memz_name);
 323         }
 324 }
 325
 326 static int
 327 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
 328                 struct qat_qp_config *qp_conf, uint8_t dir)
 329 {
 330         uint64_t queue_base;
 331         void *io_addr;
 332         const struct rte_memzone *qp_mz;
 333         struct rte_pci_device *pci_dev = qat_dev->pci_dev;
 334         int ret = 0;
 335         uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
 336                         qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
 337         uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
 338
 339         queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
 340         queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
 341                         qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
 342
 343         if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
 344                 PMD_DRV_LOG(ERR, "Invalid descriptor size %d", desc_size);
 345                 return -EINVAL;
 346         }
 347
 348         /*
 349          * Allocate a memzone for the queue - create a unique name.
 350          */
 351         snprintf(queue->memz_name, sizeof(queue->memz_name),
 352                         "%s_%d_%s_%s_%d_%d",
 353                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 354                 qp_conf->service_str, "qp_mem",
 355                 queue->hw_bundle_number, queue->hw_queue_number);
 356         qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
 357                         qp_conf->socket_id);
 358         if (qp_mz == NULL) {
 359                 PMD_DRV_LOG(ERR, "Failed to allocate ring memzone");
 360                 return -ENOMEM;
 361         }
 362
 363         queue->base_addr = (char *)qp_mz->addr;
 364         queue->base_phys_addr = qp_mz->iova;
 365         if (qat_qp_check_queue_alignment(queue->base_phys_addr,
 366                         queue_size_bytes)) {
 367                 PMD_DRV_LOG(ERR, "Invalid alignment on queue create "
 368                                         " 0x%"PRIx64"\n",
 369                                         queue->base_phys_addr);
 370                 ret = -EFAULT;
 371                 goto queue_create_err;
 372         }
 373
 374         if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
 375                         &(queue->queue_size)) != 0) {
 376                 PMD_DRV_LOG(ERR, "Invalid num inflights");
 377                 ret = -EINVAL;
 378                 goto queue_create_err;
 379         }
 380
 381         queue->max_inflights = ADF_MAX_INFLIGHTS(queue->queue_size,
 382                                         ADF_BYTES_TO_MSG_SIZE(desc_size));
 383         queue->modulo = ADF_RING_SIZE_MODULO(queue->queue_size);
 384
 385         if (queue->max_inflights < 2) {
 386                 PMD_DRV_LOG(ERR, "Invalid num inflights");
 387                 ret = -EINVAL;
 388                 goto queue_create_err;
 389         }
 390         queue->head = 0;
 391         queue->tail = 0;
 392         queue->msg_size = desc_size;
 393
 394         /*
 395          * Write an unused pattern to the queue memory.
 396          */
 397         memset(queue->base_addr, 0x7F, queue_size_bytes);
 398
 399         queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
 400                                         queue->queue_size);
 401
 402         io_addr = pci_dev->mem_resource[0].addr;
 403
 404         WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
 405                         queue->hw_queue_number, queue_base);
 406
 407         PMD_DRV_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
 408                         " nb msgs %u, msg_size %u, max_inflights %u modulo %u",
 409                         queue->memz_name,
 410                         queue->queue_size, queue_size_bytes,
 411                         qp_conf->nb_descriptors, desc_size,
 412                         queue->max_inflights, queue->modulo);
 413
 414         return 0;
 415
 416 queue_create_err:
 417         rte_memzone_free(qp_mz);
 418         return ret;
 419 }
 420
 421 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
 422                                         uint32_t queue_size_bytes)
 423 {
 424         PMD_INIT_FUNC_TRACE();
 425         if (((queue_size_bytes - 1) & phys_addr) != 0)
 426                 return -EINVAL;
 427         return 0;
 428 }
 429
 430 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
 431         uint32_t *p_queue_size_for_csr)
 432 {
 433         uint8_t i = ADF_MIN_RING_SIZE;
 434
 435         PMD_INIT_FUNC_TRACE();
 436         for (; i <= ADF_MAX_RING_SIZE; i++)
 437                 if ((msg_size * msg_num) ==
 438                                 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
 439                         *p_queue_size_for_csr = i;
 440                         return 0;
 441                 }
 442         PMD_DRV_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
 443         return -EINVAL;
 444 }
 445
 446 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr)
 447 {
 448         uint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +
 449                                         (ADF_ARB_REG_SLOT *
 450                                                         txq->hw_bundle_number);
 451         uint32_t value;
 452
 453         PMD_INIT_FUNC_TRACE();
 454         value = ADF_CSR_RD(base_addr, arb_csr_offset);
 455         value |= (0x01 << txq->hw_queue_number);
 456         ADF_CSR_WR(base_addr, arb_csr_offset, value);
 457 }
 458
 459 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr)
 460 {
 461         uint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +
 462                                         (ADF_ARB_REG_SLOT *
 463                                                         txq->hw_bundle_number);
 464         uint32_t value;
 465
 466         PMD_INIT_FUNC_TRACE();
 467         value = ADF_CSR_RD(base_addr, arb_csr_offset);
 468         value ^= (0x01 << txq->hw_queue_number);
 469         ADF_CSR_WR(base_addr, arb_csr_offset, value);
 470 }
 471
 472 static void adf_configure_queues(struct qat_qp *qp)
 473 {
 474         uint32_t queue_config;
 475         struct qat_queue *queue = &qp->tx_q;
 476
 477         PMD_INIT_FUNC_TRACE();
 478         queue_config = BUILD_RING_CONFIG(queue->queue_size);
 479
 480         WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
 481                         queue->hw_queue_number, queue_config);
 482
 483         queue = &qp->rx_q;
 484         queue_config =
 485                         BUILD_RESP_RING_CONFIG(queue->queue_size,
 486                                         ADF_RING_NEAR_WATERMARK_512,
 487                                         ADF_RING_NEAR_WATERMARK_0);
 488
 489         WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
 490                         queue->hw_queue_number, queue_config);
 491 }
 492
 493
 494 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
 495 {
 496         uint32_t div = data >> shift;
 497         uint32_t mult = div << shift;
 498
 499         return data - mult;
 500 }
 501
 502 static inline void
 503 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
 504         WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
 505                         q->hw_queue_number, q->tail);
 506         q->nb_pending_requests = 0;
 507         q->csr_tail = q->tail;
 508 }
 509
 510 static inline
 511 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
 512 {
 513         uint32_t old_head, new_head;
 514         uint32_t max_head;
 515
 516         old_head = q->csr_head;
 517         new_head = q->head;
 518         max_head = qp->nb_descriptors * q->msg_size;
 519
 520         /* write out free descriptors */
 521         void *cur_desc = (uint8_t *)q->base_addr + old_head;
 522
 523         if (new_head < old_head) {
 524                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
 525                 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
 526         } else {
 527                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
 528         }
 529         q->nb_processed_responses = 0;
 530         q->csr_head = new_head;
 531
 532         /* write current head to CSR */
 533         WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
 534                             q->hw_queue_number, new_head);
 535 }
 536
 537 uint16_t
 538 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 539 {
 540         register struct qat_queue *queue;
 541         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 542         register uint32_t nb_ops_sent = 0;
 543         register int ret;
 544         uint16_t nb_ops_possible = nb_ops;
 545         register uint8_t *base_addr;
 546         register uint32_t tail;
 547         int overflow;
 548
 549         if (unlikely(nb_ops == 0))
 550                 return 0;
 551
 552         /* read params used a lot in main loop into registers */
 553         queue = &(tmp_qp->tx_q);
 554         base_addr = (uint8_t *)queue->base_addr;
 555         tail = queue->tail;
 556
 557         /* Find how many can actually fit on the ring */
 558         tmp_qp->inflights16 += nb_ops;
 559         overflow = tmp_qp->inflights16 - queue->max_inflights;
 560         if (overflow > 0) {
 561                 tmp_qp->inflights16 -= overflow;
 562                 nb_ops_possible = nb_ops - overflow;
 563                 if (nb_ops_possible == 0)
 564                         return 0;
 565         }
 566
 567         while (nb_ops_sent != nb_ops_possible) {
 568                 ret = tmp_qp->build_request(*ops, base_addr + tail,
 569                                 tmp_qp->op_cookies[tail / queue->msg_size],
 570                                 tmp_qp->qat_dev_gen);
 571                 if (ret != 0) {
 572                         tmp_qp->stats.enqueue_err_count++;
 573                         /*
 574                          * This message cannot be enqueued,
 575                          * decrease number of ops that wasn't sent
 576                          */
 577                         tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
 578                         if (nb_ops_sent == 0)
 579                                 return 0;
 580                         goto kick_tail;
 581                 }
 582
 583                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 584                 ops++;
 585                 nb_ops_sent++;
 586         }
 587 kick_tail:
 588         queue->tail = tail;
 589         tmp_qp->stats.enqueued_count += nb_ops_sent;
 590         queue->nb_pending_requests += nb_ops_sent;
 591         if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
 592                     queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
 593                 txq_write_tail(tmp_qp, queue);
 594         }
 595         return nb_ops_sent;
 596 }
 597
 598 uint16_t
 599 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 600 {
 601         struct qat_queue *rx_queue, *tx_queue;
 602         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 603         uint32_t head;
 604         uint32_t resp_counter = 0;
 605         uint8_t *resp_msg;
 606
 607         rx_queue = &(tmp_qp->rx_q);
 608         tx_queue = &(tmp_qp->tx_q);
 609         head = rx_queue->head;
 610         resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
 611
 612         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 613                         resp_counter != nb_ops) {
 614
 615                 tmp_qp->process_response(ops, resp_msg,
 616                         tmp_qp->op_cookies[head / rx_queue->msg_size],
 617                         tmp_qp->qat_dev_gen);
 618
 619                 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
 620
 621                 resp_msg = (uint8_t *)rx_queue->base_addr + head;
 622                 ops++;
 623                 resp_counter++;
 624         }
 625         if (resp_counter > 0) {
 626                 rx_queue->head = head;
 627                 tmp_qp->stats.dequeued_count += resp_counter;
 628                 rx_queue->nb_processed_responses += resp_counter;
 629                 tmp_qp->inflights16 -= resp_counter;
 630
 631                 if (rx_queue->nb_processed_responses >
 632                                                 QAT_CSR_HEAD_WRITE_THRESH)
 633                         rxq_free_desc(tmp_qp, rx_queue);
 634         }
 635         /* also check if tail needs to be advanced */
 636         if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
 637                 tx_queue->tail != tx_queue->csr_tail) {
 638                 txq_write_tail(tmp_qp, tx_queue);
 639         }
 640         return resp_counter;
 641 }