1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
7 #include "qat_common.h"
8 #include <rte_cryptodev_pmd.h>
9 #include "adf_transport_access_macros.h"
11 #define QAT_CSR_HEAD_WRITE_THRESH 32U
12 /* number of requests to accumulate before writing head CSR */
13 #define QAT_CSR_TAIL_WRITE_THRESH 32U
14 /* number of requests to accumulate before writing tail CSR */
15 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
16 /* number of inflights below which no tail write coalescing should occur */
18 typedef int (*build_request_t)(void *op,
19 uint8_t *req, void *op_cookie,
20 enum qat_device_gen qat_dev_gen);
21 /**< Build a request from an op. */
23 typedef int (*process_response_t)(void **ops,
24 uint8_t *resp, void *op_cookie,
25 enum qat_device_gen qat_dev_gen);
26 /**< Process a response descriptor and return the associated op. */
29 * Structure with data needed for creation of queue pair.
31 struct qat_qp_hw_data {
32 enum qat_service_type service_type;
33 uint8_t hw_bundle_num;
40 * Structure with data needed for creation of queue pair.
42 struct qat_qp_config {
43 const struct qat_qp_hw_data *hw;
44 uint32_t nb_descriptors;
47 build_request_t build_request;
48 process_response_t process_response;
49 const char *service_str;
53 * Structure associated with each queue.
56 char memz_name[RTE_MEMZONE_NAMESIZE];
57 void *base_addr; /* Base address */
58 rte_iova_t base_phys_addr; /* Queue physical address */
59 uint32_t head; /* Shadow copy of the head */
60 uint32_t tail; /* Shadow copy of the tail */
63 uint16_t max_inflights;
65 uint8_t hw_bundle_number;
66 uint8_t hw_queue_number;
67 /* HW queue aka ring offset on bundle */
68 uint32_t csr_head; /* last written head value */
69 uint32_t csr_tail; /* last written tail value */
70 uint16_t nb_processed_responses;
71 /* number of responses processed since last CSR head write */
72 uint16_t nb_pending_requests;
73 /* number of requests pending since last CSR tail write */
79 struct qat_queue tx_q;
80 struct qat_queue rx_q;
81 struct rte_cryptodev_stats stats;
82 struct rte_mempool *op_cookie_pool;
84 uint32_t nb_descriptors;
85 enum qat_device_gen qat_dev_gen;
86 build_request_t build_request;
87 process_response_t process_response;
88 struct qat_pmd_private *qat_dev;
89 /**< qat device this qp is on */
90 } __rte_cache_aligned;
92 extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_PER_BUNDLE];
95 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
98 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
101 qat_qp_release(struct qat_qp **qp_addr);
104 qat_qp_setup(struct qat_pmd_private *qat_dev,
105 struct qat_qp **qp_addr, uint16_t queue_pair_id,
106 struct qat_qp_config *qat_qp_conf);
109 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
110 enum qat_service_type service);
111 #endif /* _QAT_QP_H_ */