1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_mempool.h>
7 #include <rte_hexdump.h>
8 #include <rte_crypto_sym.h>
9 #include <rte_bus_pci.h>
10 #include <rte_byteorder.h>
12 #include <openssl/evp.h>
15 #include "qat_sym_session.h"
17 #include "adf_transport_access_macros.h"
20 /* bpi is only used for partial blocks of DES and AES
21 * so AES block len can be assumed as max len for iv, src and dst
23 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
25 /** Encrypt a single partial block
26 * Depends on openssl libcrypto
27 * Uses ECB+XOR to do CFB encryption, same result, more performant
30 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
31 uint8_t *iv, int ivlen, int srclen,
34 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
36 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
37 uint8_t *encr = encrypted_iv;
39 /* ECB method: encrypt the IV, then XOR this with plaintext */
40 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
42 goto cipher_encrypt_err;
44 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
50 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
54 /** Decrypt a single partial block
55 * Depends on openssl libcrypto
56 * Uses ECB+XOR to do CFB encryption, same result, more performant
59 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
60 uint8_t *iv, int ivlen, int srclen,
63 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
65 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
66 uint8_t *encr = encrypted_iv;
68 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
69 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
71 goto cipher_decrypt_err;
73 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
79 PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
83 /** Creates a context in either AES or DES in ECB mode
84 * Depends on openssl libcrypto
86 static inline uint32_t
87 adf_modulo(uint32_t data, uint32_t shift);
90 qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,
91 struct qat_sym_op_cookie *qat_op_cookie, struct qat_qp *qp);
93 static inline uint32_t
94 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
95 struct rte_crypto_op *op)
97 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
98 struct rte_crypto_sym_op *sym_op = op->sym;
99 uint8_t last_block_len = block_len > 0 ?
100 sym_op->cipher.data.length % block_len : 0;
102 if (last_block_len &&
103 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
105 /* Decrypt last block */
106 uint8_t *last_block, *dst, *iv;
107 uint32_t last_block_offset = sym_op->cipher.data.offset +
108 sym_op->cipher.data.length - last_block_len;
109 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
110 uint8_t *, last_block_offset);
112 if (unlikely(sym_op->m_dst != NULL))
113 /* out-of-place operation (OOP) */
114 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
115 uint8_t *, last_block_offset);
119 if (last_block_len < sym_op->cipher.data.length)
120 /* use previous block ciphertext as IV */
121 iv = last_block - block_len;
123 /* runt block, i.e. less than one full block */
124 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
125 ctx->cipher_iv.offset);
127 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
128 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
130 if (sym_op->m_dst != NULL)
131 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
134 bpi_cipher_decrypt(last_block, dst, iv, block_len,
135 last_block_len, ctx->bpi_ctx);
136 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
137 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
139 if (sym_op->m_dst != NULL)
140 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
145 return sym_op->cipher.data.length - last_block_len;
148 static inline uint32_t
149 qat_bpicipher_postprocess(struct qat_sym_session *ctx,
150 struct rte_crypto_op *op)
152 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
153 struct rte_crypto_sym_op *sym_op = op->sym;
154 uint8_t last_block_len = block_len > 0 ?
155 sym_op->cipher.data.length % block_len : 0;
157 if (last_block_len > 0 &&
158 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
160 /* Encrypt last block */
161 uint8_t *last_block, *dst, *iv;
162 uint32_t last_block_offset;
164 last_block_offset = sym_op->cipher.data.offset +
165 sym_op->cipher.data.length - last_block_len;
166 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
167 uint8_t *, last_block_offset);
169 if (unlikely(sym_op->m_dst != NULL))
170 /* out-of-place operation (OOP) */
171 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
172 uint8_t *, last_block_offset);
176 if (last_block_len < sym_op->cipher.data.length)
177 /* use previous block ciphertext as IV */
178 iv = dst - block_len;
180 /* runt block, i.e. less than one full block */
181 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
182 ctx->cipher_iv.offset);
184 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
185 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
187 if (sym_op->m_dst != NULL)
188 rte_hexdump(stdout, "BPI: dst before post-process:",
189 dst, last_block_len);
191 bpi_cipher_encrypt(last_block, dst, iv, block_len,
192 last_block_len, ctx->bpi_ctx);
193 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
194 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
196 if (sym_op->m_dst != NULL)
197 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
201 return sym_op->cipher.data.length - last_block_len;
205 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
206 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
207 q->hw_queue_number, q->tail);
208 q->nb_pending_requests = 0;
209 q->csr_tail = q->tail;
213 qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
216 register struct qat_queue *queue;
217 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
218 register uint32_t nb_ops_sent = 0;
219 register struct rte_crypto_op **cur_op = ops;
221 uint16_t nb_ops_possible = nb_ops;
222 register uint8_t *base_addr;
223 register uint32_t tail;
226 if (unlikely(nb_ops == 0))
229 /* read params used a lot in main loop into registers */
230 queue = &(tmp_qp->tx_q);
231 base_addr = (uint8_t *)queue->base_addr;
234 /* Find how many can actually fit on the ring */
235 tmp_qp->inflights16 += nb_ops;
236 overflow = tmp_qp->inflights16 - queue->max_inflights;
238 tmp_qp->inflights16 -= overflow;
239 nb_ops_possible = nb_ops - overflow;
240 if (nb_ops_possible == 0)
244 while (nb_ops_sent != nb_ops_possible) {
245 ret = qat_sym_build_request(*cur_op, base_addr + tail,
246 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
248 tmp_qp->stats.enqueue_err_count++;
250 * This message cannot be enqueued,
251 * decrease number of ops that wasn't sent
253 tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
254 if (nb_ops_sent == 0)
259 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
265 tmp_qp->stats.enqueued_count += nb_ops_sent;
266 queue->nb_pending_requests += nb_ops_sent;
267 if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
268 queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
269 txq_write_tail(tmp_qp, queue);
275 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
277 uint32_t old_head, new_head;
280 old_head = q->csr_head;
282 max_head = qp->nb_descriptors * q->msg_size;
284 /* write out free descriptors */
285 void *cur_desc = (uint8_t *)q->base_addr + old_head;
287 if (new_head < old_head) {
288 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
289 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
291 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
293 q->nb_processed_responses = 0;
294 q->csr_head = new_head;
296 /* write current head to CSR */
297 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
298 q->hw_queue_number, new_head);
302 qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
305 struct qat_queue *rx_queue, *tx_queue;
306 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
307 uint32_t msg_counter = 0;
308 struct rte_crypto_op *rx_op;
309 struct icp_qat_fw_comn_resp *resp_msg;
312 rx_queue = &(tmp_qp->rx_q);
313 tx_queue = &(tmp_qp->tx_q);
314 head = rx_queue->head;
315 resp_msg = (struct icp_qat_fw_comn_resp *)
316 ((uint8_t *)rx_queue->base_addr + head);
318 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
319 msg_counter != nb_ops) {
320 rx_op = (struct rte_crypto_op *)(uintptr_t)
321 (resp_msg->opaque_data);
323 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
324 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
325 sizeof(struct icp_qat_fw_comn_resp));
327 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
328 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
329 resp_msg->comn_hdr.comn_status)) {
330 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
332 struct qat_sym_session *sess =
333 (struct qat_sym_session *)
334 get_session_private_data(
336 cryptodev_qat_driver_id);
339 qat_bpicipher_postprocess(sess, rx_op);
340 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
343 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
344 resp_msg = (struct icp_qat_fw_comn_resp *)
345 ((uint8_t *)rx_queue->base_addr + head);
350 if (msg_counter > 0) {
351 rx_queue->head = head;
352 tmp_qp->stats.dequeued_count += msg_counter;
353 rx_queue->nb_processed_responses += msg_counter;
354 tmp_qp->inflights16 -= msg_counter;
356 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
357 rxq_free_desc(tmp_qp, rx_queue);
359 /* also check if tail needs to be advanced */
360 if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
361 tx_queue->tail != tx_queue->csr_tail) {
362 txq_write_tail(tmp_qp, tx_queue);
368 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
369 struct qat_alg_buf_list *list, uint32_t data_len)
373 uint32_t buf_len = rte_pktmbuf_iova(buf) -
374 buff_start + rte_pktmbuf_data_len(buf);
376 list->bufers[0].addr = buff_start;
377 list->bufers[0].resrvd = 0;
378 list->bufers[0].len = buf_len;
380 if (data_len <= buf_len) {
382 list->bufers[0].len = data_len;
388 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
389 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
395 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
396 list->bufers[nr].resrvd = 0;
397 list->bufers[nr].addr = rte_pktmbuf_iova(buf);
399 buf_len += list->bufers[nr].len;
402 if (buf_len > data_len) {
403 list->bufers[nr].len -=
415 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
416 struct icp_qat_fw_la_cipher_req_params *cipher_param,
417 struct rte_crypto_op *op,
418 struct icp_qat_fw_la_bulk_req *qat_req)
420 /* copy IV into request if it fits */
421 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
422 rte_memcpy(cipher_param->u.cipher_IV_array,
423 rte_crypto_op_ctod_offset(op, uint8_t *,
427 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
428 qat_req->comn_hdr.serv_specif_flags,
429 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
430 cipher_param->u.s.cipher_IV_ptr =
431 rte_crypto_op_ctophys_offset(op,
436 /** Set IV for CCM is special case, 0th byte is set to q-1
437 * where q is padding of nonce in 16 byte block
440 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
441 struct icp_qat_fw_la_cipher_req_params *cipher_param,
442 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
444 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
445 ICP_QAT_HW_CCM_NONCE_OFFSET,
446 rte_crypto_op_ctod_offset(op, uint8_t *,
447 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
449 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
450 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
452 if (aad_len_field_sz)
453 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
454 rte_crypto_op_ctod_offset(op, uint8_t *,
455 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
460 qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,
461 struct qat_sym_op_cookie *qat_op_cookie, struct qat_qp *qp)
464 struct qat_sym_session *ctx;
465 struct icp_qat_fw_la_cipher_req_params *cipher_param;
466 struct icp_qat_fw_la_auth_req_params *auth_param;
467 register struct icp_qat_fw_la_bulk_req *qat_req;
468 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
469 uint32_t cipher_len = 0, cipher_ofs = 0;
470 uint32_t auth_len = 0, auth_ofs = 0;
471 uint32_t min_ofs = 0;
472 uint64_t src_buf_start = 0, dst_buf_start = 0;
475 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
476 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
477 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
478 "operation requests, op (%p) is not a "
479 "symmetric operation.", op);
483 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
484 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
485 " requests, op (%p) is sessionless.", op);
489 ctx = (struct qat_sym_session *)get_session_private_data(
490 op->sym->session, cryptodev_qat_driver_id);
492 if (unlikely(ctx == NULL)) {
493 PMD_DRV_LOG(ERR, "Session was not created for this device");
497 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
498 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
499 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
503 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
504 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
505 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
506 cipher_param = (void *)&qat_req->serv_specif_rqpars;
507 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
509 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
510 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
511 /* AES-GCM or AES-CCM */
512 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
513 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
514 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
515 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
516 && ctx->qat_hash_alg ==
517 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
523 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
526 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
533 if (ctx->qat_cipher_alg ==
534 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
535 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
536 ctx->qat_cipher_alg ==
537 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
540 (cipher_param->cipher_length % BYTE_LENGTH != 0)
541 || (cipher_param->cipher_offset
542 % BYTE_LENGTH != 0))) {
544 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
545 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
548 cipher_len = op->sym->cipher.data.length >> 3;
549 cipher_ofs = op->sym->cipher.data.offset >> 3;
551 } else if (ctx->bpi_ctx) {
552 /* DOCSIS - only send complete blocks to device
553 * Process any partial block using CFB mode.
554 * Even if 0 complete blocks, still send this to device
555 * to get into rx queue for post-process and dequeuing
557 cipher_len = qat_bpicipher_preprocess(ctx, op);
558 cipher_ofs = op->sym->cipher.data.offset;
560 cipher_len = op->sym->cipher.data.length;
561 cipher_ofs = op->sym->cipher.data.offset;
564 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
565 cipher_param, op, qat_req);
566 min_ofs = cipher_ofs;
571 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
572 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
574 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
575 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
576 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
578 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
579 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
582 auth_ofs = op->sym->auth.data.offset >> 3;
583 auth_len = op->sym->auth.data.length >> 3;
585 auth_param->u1.aad_adr =
586 rte_crypto_op_ctophys_offset(op,
587 ctx->auth_iv.offset);
589 } else if (ctx->qat_hash_alg ==
590 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
592 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
594 set_cipher_iv(ctx->auth_iv.length,
596 cipher_param, op, qat_req);
597 auth_ofs = op->sym->auth.data.offset;
598 auth_len = op->sym->auth.data.length;
600 auth_param->u1.aad_adr = 0;
601 auth_param->u2.aad_sz = 0;
604 * If len(iv)==12B fw computes J0
606 if (ctx->auth_iv.length == 12) {
607 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
608 qat_req->comn_hdr.serv_specif_flags,
609 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
613 auth_ofs = op->sym->auth.data.offset;
614 auth_len = op->sym->auth.data.length;
619 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
620 auth_param->auth_res_addr =
621 op->sym->auth.digest.phys_addr;
627 * This address may used for setting AAD physical pointer
628 * into IV offset from op
630 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
631 if (ctx->qat_hash_alg ==
632 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
634 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
636 * If len(iv)==12B fw computes J0
638 if (ctx->cipher_iv.length == 12) {
639 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
640 qat_req->comn_hdr.serv_specif_flags,
641 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
643 set_cipher_iv(ctx->cipher_iv.length,
644 ctx->cipher_iv.offset,
645 cipher_param, op, qat_req);
647 } else if (ctx->qat_hash_alg ==
648 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
650 /* In case of AES-CCM this may point to user selected
651 * memory or iv offset in cypto_op
653 uint8_t *aad_data = op->sym->aead.aad.data;
654 /* This is true AAD length, it not includes 18 bytes of
657 uint8_t aad_ccm_real_len = 0;
658 uint8_t aad_len_field_sz = 0;
659 uint32_t msg_len_be =
660 rte_bswap32(op->sym->aead.data.length);
662 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
663 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
664 aad_ccm_real_len = ctx->aad_len -
665 ICP_QAT_HW_CCM_AAD_B0_LEN -
666 ICP_QAT_HW_CCM_AAD_LEN_INFO;
669 * aad_len not greater than 18, so no actual aad
670 * data, then use IV after op for B0 block
672 aad_data = rte_crypto_op_ctod_offset(op,
674 ctx->cipher_iv.offset);
676 rte_crypto_op_ctophys_offset(op,
677 ctx->cipher_iv.offset);
680 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
681 ctx->cipher_iv.length;
683 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
685 ctx->digest_length, q);
687 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
688 memcpy(aad_data + ctx->cipher_iv.length +
689 ICP_QAT_HW_CCM_NONCE_OFFSET +
690 (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
691 (uint8_t *)&msg_len_be,
692 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
694 memcpy(aad_data + ctx->cipher_iv.length +
695 ICP_QAT_HW_CCM_NONCE_OFFSET,
696 (uint8_t *)&msg_len_be
697 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
701 if (aad_len_field_sz > 0) {
702 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
703 = rte_bswap16(aad_ccm_real_len);
705 if ((aad_ccm_real_len + aad_len_field_sz)
706 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
710 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
711 ((aad_ccm_real_len + aad_len_field_sz) %
712 ICP_QAT_HW_CCM_AAD_B0_LEN);
713 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
714 aad_ccm_real_len + aad_len_field_sz;
715 memset(&aad_data[pad_idx],
721 set_cipher_iv_ccm(ctx->cipher_iv.length,
722 ctx->cipher_iv.offset,
728 cipher_len = op->sym->aead.data.length;
729 cipher_ofs = op->sym->aead.data.offset;
730 auth_len = op->sym->aead.data.length;
731 auth_ofs = op->sym->aead.data.offset;
733 auth_param->u1.aad_adr = aad_phys_addr_aead;
734 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
735 min_ofs = op->sym->aead.data.offset;
738 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
741 /* adjust for chain case */
742 if (do_cipher && do_auth)
743 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
745 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
748 if (unlikely(op->sym->m_dst != NULL)) {
749 /* Out-of-place operation (OOP)
750 * Don't align DMA start. DMA the minimum data-set
751 * so as not to overwrite data in dest buffer
754 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
756 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
759 /* In-place operation
760 * Start DMA at nearest aligned address below min_ofs
763 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
764 & QAT_64_BTYE_ALIGN_MASK;
766 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
767 rte_pktmbuf_headroom(op->sym->m_src))
769 /* alignment has pushed addr ahead of start of mbuf
770 * so revert and take the performance hit
773 rte_pktmbuf_iova_offset(op->sym->m_src,
776 dst_buf_start = src_buf_start;
779 if (do_cipher || do_aead) {
780 cipher_param->cipher_offset =
781 (uint32_t)rte_pktmbuf_iova_offset(
782 op->sym->m_src, cipher_ofs) - src_buf_start;
783 cipher_param->cipher_length = cipher_len;
785 cipher_param->cipher_offset = 0;
786 cipher_param->cipher_length = 0;
789 if (do_auth || do_aead) {
790 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
791 op->sym->m_src, auth_ofs) - src_buf_start;
792 auth_param->auth_len = auth_len;
794 auth_param->auth_off = 0;
795 auth_param->auth_len = 0;
798 qat_req->comn_mid.dst_length =
799 qat_req->comn_mid.src_length =
800 (cipher_param->cipher_offset + cipher_param->cipher_length)
801 > (auth_param->auth_off + auth_param->auth_len) ?
802 (cipher_param->cipher_offset + cipher_param->cipher_length)
803 : (auth_param->auth_off + auth_param->auth_len);
807 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
808 QAT_COMN_PTR_TYPE_SGL);
809 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
810 &qat_op_cookie->qat_sgl_list_src,
811 qat_req->comn_mid.src_length);
813 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
817 if (likely(op->sym->m_dst == NULL))
818 qat_req->comn_mid.dest_data_addr =
819 qat_req->comn_mid.src_data_addr =
820 qat_op_cookie->qat_sgl_src_phys_addr;
822 ret = qat_sgl_fill_array(op->sym->m_dst,
824 &qat_op_cookie->qat_sgl_list_dst,
825 qat_req->comn_mid.dst_length);
828 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
833 qat_req->comn_mid.src_data_addr =
834 qat_op_cookie->qat_sgl_src_phys_addr;
835 qat_req->comn_mid.dest_data_addr =
836 qat_op_cookie->qat_sgl_dst_phys_addr;
839 qat_req->comn_mid.src_data_addr = src_buf_start;
840 qat_req->comn_mid.dest_data_addr = dst_buf_start;
843 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
844 rte_hexdump(stdout, "qat_req:", qat_req,
845 sizeof(struct icp_qat_fw_la_bulk_req));
846 rte_hexdump(stdout, "src_data:",
847 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
848 rte_pktmbuf_data_len(op->sym->m_src));
850 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
852 ctx->cipher_iv.offset);
853 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
854 ctx->cipher_iv.length);
858 if (ctx->auth_iv.length) {
859 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
861 ctx->auth_iv.offset);
862 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
863 ctx->auth_iv.length);
865 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
870 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
872 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
879 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
881 uint32_t div = data >> shift;
882 uint32_t mult = div << shift;
887 void qat_sym_stats_get(struct rte_cryptodev *dev,
888 struct rte_cryptodev_stats *stats)
891 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
893 PMD_INIT_FUNC_TRACE();
895 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
898 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
900 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
904 stats->enqueued_count += qp[i]->stats.enqueued_count;
905 stats->dequeued_count += qp[i]->stats.dequeued_count;
906 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
907 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
911 void qat_sym_stats_reset(struct rte_cryptodev *dev)
914 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
916 PMD_INIT_FUNC_TRACE();
917 for (i = 0; i < dev->data->nb_queue_pairs; i++)
918 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
919 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");