1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <openssl/evp.h>
7 #include <rte_mempool.h>
9 #include <rte_hexdump.h>
10 #include <rte_crypto_sym.h>
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
17 /** Decrypt a single partial block
18 * Depends on openssl libcrypto
19 * Uses ECB+XOR to do CFB encryption, same result, more performant
22 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
23 uint8_t *iv, int ivlen, int srclen,
26 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
28 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
29 uint8_t *encr = encrypted_iv;
31 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
32 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
34 goto cipher_decrypt_err;
36 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
42 QAT_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
47 static inline uint32_t
48 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
49 struct rte_crypto_op *op)
51 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
52 struct rte_crypto_sym_op *sym_op = op->sym;
53 uint8_t last_block_len = block_len > 0 ?
54 sym_op->cipher.data.length % block_len : 0;
57 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
59 /* Decrypt last block */
60 uint8_t *last_block, *dst, *iv;
61 uint32_t last_block_offset = sym_op->cipher.data.offset +
62 sym_op->cipher.data.length - last_block_len;
63 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
64 uint8_t *, last_block_offset);
66 if (unlikely(sym_op->m_dst != NULL))
67 /* out-of-place operation (OOP) */
68 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
69 uint8_t *, last_block_offset);
73 if (last_block_len < sym_op->cipher.data.length)
74 /* use previous block ciphertext as IV */
75 iv = last_block - block_len;
77 /* runt block, i.e. less than one full block */
78 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
79 ctx->cipher_iv.offset);
81 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
82 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
84 if (sym_op->m_dst != NULL)
85 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
88 bpi_cipher_decrypt(last_block, dst, iv, block_len,
89 last_block_len, ctx->bpi_ctx);
90 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
91 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
93 if (sym_op->m_dst != NULL)
94 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
99 return sym_op->cipher.data.length - last_block_len;
103 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
104 struct icp_qat_fw_la_cipher_req_params *cipher_param,
105 struct rte_crypto_op *op,
106 struct icp_qat_fw_la_bulk_req *qat_req)
108 /* copy IV into request if it fits */
109 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
110 rte_memcpy(cipher_param->u.cipher_IV_array,
111 rte_crypto_op_ctod_offset(op, uint8_t *,
115 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
116 qat_req->comn_hdr.serv_specif_flags,
117 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
118 cipher_param->u.s.cipher_IV_ptr =
119 rte_crypto_op_ctophys_offset(op,
124 /** Set IV for CCM is special case, 0th byte is set to q-1
125 * where q is padding of nonce in 16 byte block
128 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
129 struct icp_qat_fw_la_cipher_req_params *cipher_param,
130 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
132 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
133 ICP_QAT_HW_CCM_NONCE_OFFSET,
134 rte_crypto_op_ctod_offset(op, uint8_t *,
135 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
137 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
138 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
140 if (aad_len_field_sz)
141 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
142 rte_crypto_op_ctod_offset(op, uint8_t *,
143 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
148 qat_sym_build_request(void *in_op, uint8_t *out_msg,
149 void *op_cookie, enum qat_device_gen qat_dev_gen)
152 struct qat_sym_session *ctx;
153 struct icp_qat_fw_la_cipher_req_params *cipher_param;
154 struct icp_qat_fw_la_auth_req_params *auth_param;
155 register struct icp_qat_fw_la_bulk_req *qat_req;
156 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
157 uint32_t cipher_len = 0, cipher_ofs = 0;
158 uint32_t auth_len = 0, auth_ofs = 0;
159 uint32_t min_ofs = 0;
160 uint64_t src_buf_start = 0, dst_buf_start = 0;
162 struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
163 struct qat_sym_op_cookie *cookie =
164 (struct qat_sym_op_cookie *)op_cookie;
166 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
167 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
168 QAT_LOG(ERR, "QAT PMD only supports symmetric crypto "
169 "operation requests, op (%p) is not a "
170 "symmetric operation.", op);
174 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
175 QAT_LOG(ERR, "QAT PMD only supports session oriented"
176 " requests, op (%p) is sessionless.", op);
180 ctx = (struct qat_sym_session *)get_session_private_data(
181 op->sym->session, cryptodev_qat_driver_id);
183 if (unlikely(ctx == NULL)) {
184 QAT_LOG(ERR, "Session was not created for this device");
188 if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
189 QAT_LOG(ERR, "Session alg not supported on this device gen");
190 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
194 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
195 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
196 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
197 cipher_param = (void *)&qat_req->serv_specif_rqpars;
198 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
200 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
201 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
202 /* AES-GCM or AES-CCM */
203 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
204 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
205 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
206 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
207 && ctx->qat_hash_alg ==
208 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
214 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
217 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
224 if (ctx->qat_cipher_alg ==
225 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
226 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
227 ctx->qat_cipher_alg ==
228 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
231 (cipher_param->cipher_length % BYTE_LENGTH != 0)
232 || (cipher_param->cipher_offset
233 % BYTE_LENGTH != 0))) {
235 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
236 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
239 cipher_len = op->sym->cipher.data.length >> 3;
240 cipher_ofs = op->sym->cipher.data.offset >> 3;
242 } else if (ctx->bpi_ctx) {
243 /* DOCSIS - only send complete blocks to device
244 * Process any partial block using CFB mode.
245 * Even if 0 complete blocks, still send this to device
246 * to get into rx queue for post-process and dequeuing
248 cipher_len = qat_bpicipher_preprocess(ctx, op);
249 cipher_ofs = op->sym->cipher.data.offset;
251 cipher_len = op->sym->cipher.data.length;
252 cipher_ofs = op->sym->cipher.data.offset;
255 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
256 cipher_param, op, qat_req);
257 min_ofs = cipher_ofs;
262 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
263 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
265 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
266 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
267 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
269 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
270 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
273 auth_ofs = op->sym->auth.data.offset >> 3;
274 auth_len = op->sym->auth.data.length >> 3;
276 auth_param->u1.aad_adr =
277 rte_crypto_op_ctophys_offset(op,
278 ctx->auth_iv.offset);
280 } else if (ctx->qat_hash_alg ==
281 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
283 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
285 set_cipher_iv(ctx->auth_iv.length,
287 cipher_param, op, qat_req);
288 auth_ofs = op->sym->auth.data.offset;
289 auth_len = op->sym->auth.data.length;
291 auth_param->u1.aad_adr = 0;
292 auth_param->u2.aad_sz = 0;
295 * If len(iv)==12B fw computes J0
297 if (ctx->auth_iv.length == 12) {
298 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
299 qat_req->comn_hdr.serv_specif_flags,
300 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
304 auth_ofs = op->sym->auth.data.offset;
305 auth_len = op->sym->auth.data.length;
310 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
311 auth_param->auth_res_addr =
312 op->sym->auth.digest.phys_addr;
318 * This address may used for setting AAD physical pointer
319 * into IV offset from op
321 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
322 if (ctx->qat_hash_alg ==
323 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
325 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
327 * If len(iv)==12B fw computes J0
329 if (ctx->cipher_iv.length == 12) {
330 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
331 qat_req->comn_hdr.serv_specif_flags,
332 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
334 set_cipher_iv(ctx->cipher_iv.length,
335 ctx->cipher_iv.offset,
336 cipher_param, op, qat_req);
338 } else if (ctx->qat_hash_alg ==
339 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
341 /* In case of AES-CCM this may point to user selected
342 * memory or iv offset in cypto_op
344 uint8_t *aad_data = op->sym->aead.aad.data;
345 /* This is true AAD length, it not includes 18 bytes of
348 uint8_t aad_ccm_real_len = 0;
349 uint8_t aad_len_field_sz = 0;
350 uint32_t msg_len_be =
351 rte_bswap32(op->sym->aead.data.length);
353 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
354 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
355 aad_ccm_real_len = ctx->aad_len -
356 ICP_QAT_HW_CCM_AAD_B0_LEN -
357 ICP_QAT_HW_CCM_AAD_LEN_INFO;
360 * aad_len not greater than 18, so no actual aad
361 * data, then use IV after op for B0 block
363 aad_data = rte_crypto_op_ctod_offset(op,
365 ctx->cipher_iv.offset);
367 rte_crypto_op_ctophys_offset(op,
368 ctx->cipher_iv.offset);
371 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
372 ctx->cipher_iv.length;
374 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
376 ctx->digest_length, q);
378 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
379 memcpy(aad_data + ctx->cipher_iv.length +
380 ICP_QAT_HW_CCM_NONCE_OFFSET +
381 (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
382 (uint8_t *)&msg_len_be,
383 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
385 memcpy(aad_data + ctx->cipher_iv.length +
386 ICP_QAT_HW_CCM_NONCE_OFFSET,
387 (uint8_t *)&msg_len_be
388 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
392 if (aad_len_field_sz > 0) {
393 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
394 = rte_bswap16(aad_ccm_real_len);
396 if ((aad_ccm_real_len + aad_len_field_sz)
397 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
401 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
402 ((aad_ccm_real_len + aad_len_field_sz) %
403 ICP_QAT_HW_CCM_AAD_B0_LEN);
404 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
405 aad_ccm_real_len + aad_len_field_sz;
406 memset(&aad_data[pad_idx],
412 set_cipher_iv_ccm(ctx->cipher_iv.length,
413 ctx->cipher_iv.offset,
419 cipher_len = op->sym->aead.data.length;
420 cipher_ofs = op->sym->aead.data.offset;
421 auth_len = op->sym->aead.data.length;
422 auth_ofs = op->sym->aead.data.offset;
424 auth_param->u1.aad_adr = aad_phys_addr_aead;
425 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
426 min_ofs = op->sym->aead.data.offset;
429 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
432 /* adjust for chain case */
433 if (do_cipher && do_auth)
434 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
436 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
439 if (unlikely(op->sym->m_dst != NULL)) {
440 /* Out-of-place operation (OOP)
441 * Don't align DMA start. DMA the minimum data-set
442 * so as not to overwrite data in dest buffer
445 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
447 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
450 /* In-place operation
451 * Start DMA at nearest aligned address below min_ofs
454 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
455 & QAT_64_BTYE_ALIGN_MASK;
457 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
458 rte_pktmbuf_headroom(op->sym->m_src))
460 /* alignment has pushed addr ahead of start of mbuf
461 * so revert and take the performance hit
464 rte_pktmbuf_iova_offset(op->sym->m_src,
467 dst_buf_start = src_buf_start;
470 if (do_cipher || do_aead) {
471 cipher_param->cipher_offset =
472 (uint32_t)rte_pktmbuf_iova_offset(
473 op->sym->m_src, cipher_ofs) - src_buf_start;
474 cipher_param->cipher_length = cipher_len;
476 cipher_param->cipher_offset = 0;
477 cipher_param->cipher_length = 0;
480 if (do_auth || do_aead) {
481 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
482 op->sym->m_src, auth_ofs) - src_buf_start;
483 auth_param->auth_len = auth_len;
485 auth_param->auth_off = 0;
486 auth_param->auth_len = 0;
489 qat_req->comn_mid.dst_length =
490 qat_req->comn_mid.src_length =
491 (cipher_param->cipher_offset + cipher_param->cipher_length)
492 > (auth_param->auth_off + auth_param->auth_len) ?
493 (cipher_param->cipher_offset + cipher_param->cipher_length)
494 : (auth_param->auth_off + auth_param->auth_len);
498 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
499 QAT_COMN_PTR_TYPE_SGL);
500 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
501 &cookie->qat_sgl_src,
502 qat_req->comn_mid.src_length);
504 QAT_LOG(ERR, "QAT PMD Cannot fill sgl array");
508 if (likely(op->sym->m_dst == NULL))
509 qat_req->comn_mid.dest_data_addr =
510 qat_req->comn_mid.src_data_addr =
511 cookie->qat_sgl_src_phys_addr;
513 ret = qat_sgl_fill_array(op->sym->m_dst,
515 &cookie->qat_sgl_dst,
516 qat_req->comn_mid.dst_length);
519 QAT_LOG(ERR, "QAT PMD Cannot "
524 qat_req->comn_mid.src_data_addr =
525 cookie->qat_sgl_src_phys_addr;
526 qat_req->comn_mid.dest_data_addr =
527 cookie->qat_sgl_dst_phys_addr;
530 qat_req->comn_mid.src_data_addr = src_buf_start;
531 qat_req->comn_mid.dest_data_addr = dst_buf_start;
534 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
535 rte_hexdump(stdout, "qat_req:", qat_req,
536 sizeof(struct icp_qat_fw_la_bulk_req));
537 rte_hexdump(stdout, "src_data:",
538 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
539 rte_pktmbuf_data_len(op->sym->m_src));
541 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
543 ctx->cipher_iv.offset);
544 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
545 ctx->cipher_iv.length);
549 if (ctx->auth_iv.length) {
550 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
552 ctx->auth_iv.offset);
553 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
554 ctx->auth_iv.length);
556 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
561 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
563 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,