1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_mempool.h>
7 #include <rte_hexdump.h>
8 #include <rte_crypto_sym.h>
9 #include <rte_bus_pci.h>
10 #include <rte_byteorder.h>
12 #include <openssl/evp.h>
15 #include "qat_sym_session.h"
18 #include "adf_transport_access_macros.h"
21 /* bpi is only used for partial blocks of DES and AES
22 * so AES block len can be assumed as max len for iv, src and dst
24 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
26 #define ADF_SYM_TX_RING_DESC_SIZE 128
27 #define ADF_SYM_RX_RING_DESC_SIZE 32
28 #define ADF_SYM_TX_QUEUE_STARTOFF 2
29 /* Offset from bundle start to 1st Sym Tx queue */
30 #define ADF_SYM_RX_QUEUE_STARTOFF 10
32 /** Encrypt a single partial block
33 * Depends on openssl libcrypto
34 * Uses ECB+XOR to do CFB encryption, same result, more performant
37 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
38 uint8_t *iv, int ivlen, int srclen,
41 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
43 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
44 uint8_t *encr = encrypted_iv;
46 /* ECB method: encrypt the IV, then XOR this with plaintext */
47 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
49 goto cipher_encrypt_err;
51 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
57 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
61 /** Decrypt a single partial block
62 * Depends on openssl libcrypto
63 * Uses ECB+XOR to do CFB encryption, same result, more performant
66 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
67 uint8_t *iv, int ivlen, int srclen,
70 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
72 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
73 uint8_t *encr = encrypted_iv;
75 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
76 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
78 goto cipher_decrypt_err;
80 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
86 PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
90 /** Creates a context in either AES or DES in ECB mode
91 * Depends on openssl libcrypto
94 static inline uint32_t
95 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
96 struct rte_crypto_op *op)
98 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
99 struct rte_crypto_sym_op *sym_op = op->sym;
100 uint8_t last_block_len = block_len > 0 ?
101 sym_op->cipher.data.length % block_len : 0;
103 if (last_block_len &&
104 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
106 /* Decrypt last block */
107 uint8_t *last_block, *dst, *iv;
108 uint32_t last_block_offset = sym_op->cipher.data.offset +
109 sym_op->cipher.data.length - last_block_len;
110 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
111 uint8_t *, last_block_offset);
113 if (unlikely(sym_op->m_dst != NULL))
114 /* out-of-place operation (OOP) */
115 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
116 uint8_t *, last_block_offset);
120 if (last_block_len < sym_op->cipher.data.length)
121 /* use previous block ciphertext as IV */
122 iv = last_block - block_len;
124 /* runt block, i.e. less than one full block */
125 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
126 ctx->cipher_iv.offset);
128 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
129 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
131 if (sym_op->m_dst != NULL)
132 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
135 bpi_cipher_decrypt(last_block, dst, iv, block_len,
136 last_block_len, ctx->bpi_ctx);
137 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
138 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
140 if (sym_op->m_dst != NULL)
141 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
146 return sym_op->cipher.data.length - last_block_len;
149 static inline uint32_t
150 qat_bpicipher_postprocess(struct qat_sym_session *ctx,
151 struct rte_crypto_op *op)
153 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
154 struct rte_crypto_sym_op *sym_op = op->sym;
155 uint8_t last_block_len = block_len > 0 ?
156 sym_op->cipher.data.length % block_len : 0;
158 if (last_block_len > 0 &&
159 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
161 /* Encrypt last block */
162 uint8_t *last_block, *dst, *iv;
163 uint32_t last_block_offset;
165 last_block_offset = sym_op->cipher.data.offset +
166 sym_op->cipher.data.length - last_block_len;
167 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
168 uint8_t *, last_block_offset);
170 if (unlikely(sym_op->m_dst != NULL))
171 /* out-of-place operation (OOP) */
172 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
173 uint8_t *, last_block_offset);
177 if (last_block_len < sym_op->cipher.data.length)
178 /* use previous block ciphertext as IV */
179 iv = dst - block_len;
181 /* runt block, i.e. less than one full block */
182 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
183 ctx->cipher_iv.offset);
185 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
186 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
188 if (sym_op->m_dst != NULL)
189 rte_hexdump(stdout, "BPI: dst before post-process:",
190 dst, last_block_len);
192 bpi_cipher_encrypt(last_block, dst, iv, block_len,
193 last_block_len, ctx->bpi_ctx);
194 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
195 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
197 if (sym_op->m_dst != NULL)
198 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
202 return sym_op->cipher.data.length - last_block_len;
206 qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
209 return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
213 qat_sym_process_response(void **op, uint8_t *resp,
214 __rte_unused void *op_cookie,
215 __rte_unused enum qat_device_gen qat_dev_gen)
218 struct icp_qat_fw_comn_resp *resp_msg =
219 (struct icp_qat_fw_comn_resp *)resp;
220 struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
221 (resp_msg->opaque_data);
223 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
224 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
225 sizeof(struct icp_qat_fw_comn_resp));
228 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
229 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
230 resp_msg->comn_hdr.comn_status)) {
232 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
234 struct qat_sym_session *sess = (struct qat_sym_session *)
235 get_session_private_data(
237 cryptodev_qat_driver_id);
240 qat_bpicipher_postprocess(sess, rx_op);
241 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
250 qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
253 return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
257 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
258 struct qat_alg_buf_list *list, uint32_t data_len)
262 uint32_t buf_len = rte_pktmbuf_iova(buf) -
263 buff_start + rte_pktmbuf_data_len(buf);
265 list->bufers[0].addr = buff_start;
266 list->bufers[0].resrvd = 0;
267 list->bufers[0].len = buf_len;
269 if (data_len <= buf_len) {
271 list->bufers[0].len = data_len;
277 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
278 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
284 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
285 list->bufers[nr].resrvd = 0;
286 list->bufers[nr].addr = rte_pktmbuf_iova(buf);
288 buf_len += list->bufers[nr].len;
291 if (buf_len > data_len) {
292 list->bufers[nr].len -=
304 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
305 struct icp_qat_fw_la_cipher_req_params *cipher_param,
306 struct rte_crypto_op *op,
307 struct icp_qat_fw_la_bulk_req *qat_req)
309 /* copy IV into request if it fits */
310 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
311 rte_memcpy(cipher_param->u.cipher_IV_array,
312 rte_crypto_op_ctod_offset(op, uint8_t *,
316 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
317 qat_req->comn_hdr.serv_specif_flags,
318 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
319 cipher_param->u.s.cipher_IV_ptr =
320 rte_crypto_op_ctophys_offset(op,
325 /** Set IV for CCM is special case, 0th byte is set to q-1
326 * where q is padding of nonce in 16 byte block
329 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
330 struct icp_qat_fw_la_cipher_req_params *cipher_param,
331 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
333 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
334 ICP_QAT_HW_CCM_NONCE_OFFSET,
335 rte_crypto_op_ctod_offset(op, uint8_t *,
336 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
338 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
339 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
341 if (aad_len_field_sz)
342 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
343 rte_crypto_op_ctod_offset(op, uint8_t *,
344 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
350 qat_sym_build_request(void *in_op, uint8_t *out_msg,
351 void *op_cookie, enum qat_device_gen qat_dev_gen)
354 struct qat_sym_session *ctx;
355 struct icp_qat_fw_la_cipher_req_params *cipher_param;
356 struct icp_qat_fw_la_auth_req_params *auth_param;
357 register struct icp_qat_fw_la_bulk_req *qat_req;
358 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
359 uint32_t cipher_len = 0, cipher_ofs = 0;
360 uint32_t auth_len = 0, auth_ofs = 0;
361 uint32_t min_ofs = 0;
362 uint64_t src_buf_start = 0, dst_buf_start = 0;
364 struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
365 struct qat_sym_op_cookie *cookie =
366 (struct qat_sym_op_cookie *)op_cookie;
368 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
369 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
370 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
371 "operation requests, op (%p) is not a "
372 "symmetric operation.", op);
376 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
377 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
378 " requests, op (%p) is sessionless.", op);
382 ctx = (struct qat_sym_session *)get_session_private_data(
383 op->sym->session, cryptodev_qat_driver_id);
385 if (unlikely(ctx == NULL)) {
386 PMD_DRV_LOG(ERR, "Session was not created for this device");
390 if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
391 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
392 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
396 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
397 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
398 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
399 cipher_param = (void *)&qat_req->serv_specif_rqpars;
400 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
402 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
403 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
404 /* AES-GCM or AES-CCM */
405 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
406 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
407 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
408 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
409 && ctx->qat_hash_alg ==
410 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
416 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
419 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
426 if (ctx->qat_cipher_alg ==
427 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
428 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
429 ctx->qat_cipher_alg ==
430 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
433 (cipher_param->cipher_length % BYTE_LENGTH != 0)
434 || (cipher_param->cipher_offset
435 % BYTE_LENGTH != 0))) {
437 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
438 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
441 cipher_len = op->sym->cipher.data.length >> 3;
442 cipher_ofs = op->sym->cipher.data.offset >> 3;
444 } else if (ctx->bpi_ctx) {
445 /* DOCSIS - only send complete blocks to device
446 * Process any partial block using CFB mode.
447 * Even if 0 complete blocks, still send this to device
448 * to get into rx queue for post-process and dequeuing
450 cipher_len = qat_bpicipher_preprocess(ctx, op);
451 cipher_ofs = op->sym->cipher.data.offset;
453 cipher_len = op->sym->cipher.data.length;
454 cipher_ofs = op->sym->cipher.data.offset;
457 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
458 cipher_param, op, qat_req);
459 min_ofs = cipher_ofs;
464 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
465 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
467 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
468 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
469 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
471 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
472 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
475 auth_ofs = op->sym->auth.data.offset >> 3;
476 auth_len = op->sym->auth.data.length >> 3;
478 auth_param->u1.aad_adr =
479 rte_crypto_op_ctophys_offset(op,
480 ctx->auth_iv.offset);
482 } else if (ctx->qat_hash_alg ==
483 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
485 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
487 set_cipher_iv(ctx->auth_iv.length,
489 cipher_param, op, qat_req);
490 auth_ofs = op->sym->auth.data.offset;
491 auth_len = op->sym->auth.data.length;
493 auth_param->u1.aad_adr = 0;
494 auth_param->u2.aad_sz = 0;
497 * If len(iv)==12B fw computes J0
499 if (ctx->auth_iv.length == 12) {
500 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
501 qat_req->comn_hdr.serv_specif_flags,
502 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
506 auth_ofs = op->sym->auth.data.offset;
507 auth_len = op->sym->auth.data.length;
512 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
513 auth_param->auth_res_addr =
514 op->sym->auth.digest.phys_addr;
520 * This address may used for setting AAD physical pointer
521 * into IV offset from op
523 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
524 if (ctx->qat_hash_alg ==
525 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
527 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
529 * If len(iv)==12B fw computes J0
531 if (ctx->cipher_iv.length == 12) {
532 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
533 qat_req->comn_hdr.serv_specif_flags,
534 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
536 set_cipher_iv(ctx->cipher_iv.length,
537 ctx->cipher_iv.offset,
538 cipher_param, op, qat_req);
540 } else if (ctx->qat_hash_alg ==
541 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
543 /* In case of AES-CCM this may point to user selected
544 * memory or iv offset in cypto_op
546 uint8_t *aad_data = op->sym->aead.aad.data;
547 /* This is true AAD length, it not includes 18 bytes of
550 uint8_t aad_ccm_real_len = 0;
551 uint8_t aad_len_field_sz = 0;
552 uint32_t msg_len_be =
553 rte_bswap32(op->sym->aead.data.length);
555 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
556 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
557 aad_ccm_real_len = ctx->aad_len -
558 ICP_QAT_HW_CCM_AAD_B0_LEN -
559 ICP_QAT_HW_CCM_AAD_LEN_INFO;
562 * aad_len not greater than 18, so no actual aad
563 * data, then use IV after op for B0 block
565 aad_data = rte_crypto_op_ctod_offset(op,
567 ctx->cipher_iv.offset);
569 rte_crypto_op_ctophys_offset(op,
570 ctx->cipher_iv.offset);
573 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
574 ctx->cipher_iv.length;
576 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
578 ctx->digest_length, q);
580 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
581 memcpy(aad_data + ctx->cipher_iv.length +
582 ICP_QAT_HW_CCM_NONCE_OFFSET +
583 (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
584 (uint8_t *)&msg_len_be,
585 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
587 memcpy(aad_data + ctx->cipher_iv.length +
588 ICP_QAT_HW_CCM_NONCE_OFFSET,
589 (uint8_t *)&msg_len_be
590 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
594 if (aad_len_field_sz > 0) {
595 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
596 = rte_bswap16(aad_ccm_real_len);
598 if ((aad_ccm_real_len + aad_len_field_sz)
599 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
603 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
604 ((aad_ccm_real_len + aad_len_field_sz) %
605 ICP_QAT_HW_CCM_AAD_B0_LEN);
606 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
607 aad_ccm_real_len + aad_len_field_sz;
608 memset(&aad_data[pad_idx],
614 set_cipher_iv_ccm(ctx->cipher_iv.length,
615 ctx->cipher_iv.offset,
621 cipher_len = op->sym->aead.data.length;
622 cipher_ofs = op->sym->aead.data.offset;
623 auth_len = op->sym->aead.data.length;
624 auth_ofs = op->sym->aead.data.offset;
626 auth_param->u1.aad_adr = aad_phys_addr_aead;
627 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
628 min_ofs = op->sym->aead.data.offset;
631 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
634 /* adjust for chain case */
635 if (do_cipher && do_auth)
636 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
638 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
641 if (unlikely(op->sym->m_dst != NULL)) {
642 /* Out-of-place operation (OOP)
643 * Don't align DMA start. DMA the minimum data-set
644 * so as not to overwrite data in dest buffer
647 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
649 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
652 /* In-place operation
653 * Start DMA at nearest aligned address below min_ofs
656 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
657 & QAT_64_BTYE_ALIGN_MASK;
659 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
660 rte_pktmbuf_headroom(op->sym->m_src))
662 /* alignment has pushed addr ahead of start of mbuf
663 * so revert and take the performance hit
666 rte_pktmbuf_iova_offset(op->sym->m_src,
669 dst_buf_start = src_buf_start;
672 if (do_cipher || do_aead) {
673 cipher_param->cipher_offset =
674 (uint32_t)rte_pktmbuf_iova_offset(
675 op->sym->m_src, cipher_ofs) - src_buf_start;
676 cipher_param->cipher_length = cipher_len;
678 cipher_param->cipher_offset = 0;
679 cipher_param->cipher_length = 0;
682 if (do_auth || do_aead) {
683 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
684 op->sym->m_src, auth_ofs) - src_buf_start;
685 auth_param->auth_len = auth_len;
687 auth_param->auth_off = 0;
688 auth_param->auth_len = 0;
691 qat_req->comn_mid.dst_length =
692 qat_req->comn_mid.src_length =
693 (cipher_param->cipher_offset + cipher_param->cipher_length)
694 > (auth_param->auth_off + auth_param->auth_len) ?
695 (cipher_param->cipher_offset + cipher_param->cipher_length)
696 : (auth_param->auth_off + auth_param->auth_len);
700 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
701 QAT_COMN_PTR_TYPE_SGL);
702 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
703 &cookie->qat_sgl_list_src,
704 qat_req->comn_mid.src_length);
706 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
710 if (likely(op->sym->m_dst == NULL))
711 qat_req->comn_mid.dest_data_addr =
712 qat_req->comn_mid.src_data_addr =
713 cookie->qat_sgl_src_phys_addr;
715 ret = qat_sgl_fill_array(op->sym->m_dst,
717 &cookie->qat_sgl_list_dst,
718 qat_req->comn_mid.dst_length);
721 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
726 qat_req->comn_mid.src_data_addr =
727 cookie->qat_sgl_src_phys_addr;
728 qat_req->comn_mid.dest_data_addr =
729 cookie->qat_sgl_dst_phys_addr;
732 qat_req->comn_mid.src_data_addr = src_buf_start;
733 qat_req->comn_mid.dest_data_addr = dst_buf_start;
736 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
737 rte_hexdump(stdout, "qat_req:", qat_req,
738 sizeof(struct icp_qat_fw_la_bulk_req));
739 rte_hexdump(stdout, "src_data:",
740 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
741 rte_pktmbuf_data_len(op->sym->m_src));
743 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
745 ctx->cipher_iv.offset);
746 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
747 ctx->cipher_iv.length);
751 if (ctx->auth_iv.length) {
752 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
754 ctx->auth_iv.offset);
755 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
756 ctx->auth_iv.length);
758 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
763 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
765 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
773 void qat_sym_stats_get(struct rte_cryptodev *dev,
774 struct rte_cryptodev_stats *stats)
777 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
779 PMD_INIT_FUNC_TRACE();
781 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
784 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
786 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
790 stats->enqueued_count += qp[i]->stats.enqueued_count;
791 stats->dequeued_count += qp[i]->stats.dequeued_count;
792 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
793 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
797 void qat_sym_stats_reset(struct rte_cryptodev *dev)
800 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
802 PMD_INIT_FUNC_TRACE();
803 for (i = 0; i < dev->data->nb_queue_pairs; i++)
804 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
805 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
810 int qat_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)
812 PMD_DRV_LOG(DEBUG, "Release sym qp %u on device %d",
813 queue_pair_id, dev->data->dev_id);
814 return qat_qp_release((struct qat_qp **)
815 &(dev->data->queue_pairs[queue_pair_id]));
818 int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
819 const struct rte_cryptodev_qp_conf *qp_conf,
820 int socket_id, struct rte_mempool *session_pool __rte_unused)
825 struct qat_qp_config qat_qp_conf;
826 struct qat_qp **qp_addr =
827 (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
828 struct qat_pmd_private *qat_private = dev->data->dev_private;
830 /* If qp is already in use free ring memory and qp metadata. */
831 if (*qp_addr != NULL) {
832 ret = qat_sym_qp_release(dev, qp_id);
836 if (qp_id >= (ADF_NUM_SYM_QPS_PER_BUNDLE *
837 ADF_NUM_BUNDLES_PER_DEV)) {
838 PMD_DRV_LOG(ERR, "qp_id %u invalid for this device", qp_id);
842 qat_qp_conf.hw_bundle_num = (qp_id/ADF_NUM_SYM_QPS_PER_BUNDLE);
843 qat_qp_conf.tx_ring_num = (qp_id%ADF_NUM_SYM_QPS_PER_BUNDLE) +
844 ADF_SYM_TX_QUEUE_STARTOFF;
845 qat_qp_conf.rx_ring_num = (qp_id%ADF_NUM_SYM_QPS_PER_BUNDLE) +
846 ADF_SYM_RX_QUEUE_STARTOFF;
847 qat_qp_conf.tx_msg_size = ADF_SYM_TX_RING_DESC_SIZE;
848 qat_qp_conf.rx_msg_size = ADF_SYM_RX_RING_DESC_SIZE;
849 qat_qp_conf.build_request = qat_sym_build_request;
850 qat_qp_conf.process_response = qat_sym_process_response;
851 qat_qp_conf.cookie_size = sizeof(struct qat_sym_op_cookie);
852 qat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;
853 qat_qp_conf.socket_id = socket_id;
854 qat_qp_conf.service_str = "sym";
856 ret = qat_qp_setup(qat_private, qp_addr, qp_id, &qat_qp_conf);
860 qp = (struct qat_qp *)*qp_addr;
862 for (i = 0; i < qp->nb_descriptors; i++) {
864 struct qat_sym_op_cookie *sql_cookie =
867 sql_cookie->qat_sgl_src_phys_addr =
868 rte_mempool_virt2iova(sql_cookie) +
869 offsetof(struct qat_sym_op_cookie,
872 sql_cookie->qat_sgl_dst_phys_addr =
873 rte_mempool_virt2iova(sql_cookie) +
874 offsetof(struct qat_sym_op_cookie,