1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2019 Intel Corporation
5 #include <openssl/evp.h>
7 #include <rte_mempool.h>
9 #include <rte_crypto_sym.h>
10 #include <rte_bus_pci.h>
11 #include <rte_byteorder.h>
16 /** Decrypt a single partial block
17 * Depends on openssl libcrypto
18 * Uses ECB+XOR to do CFB encryption, same result, more performant
21 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
22 uint8_t *iv, int ivlen, int srclen,
25 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
27 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
28 uint8_t *encr = encrypted_iv;
30 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
31 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
33 goto cipher_decrypt_err;
35 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
41 QAT_DP_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
46 static inline uint32_t
47 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
48 struct rte_crypto_op *op)
50 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
51 struct rte_crypto_sym_op *sym_op = op->sym;
52 uint8_t last_block_len = block_len > 0 ?
53 sym_op->cipher.data.length % block_len : 0;
56 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
58 /* Decrypt last block */
59 uint8_t *last_block, *dst, *iv;
60 uint32_t last_block_offset = sym_op->cipher.data.offset +
61 sym_op->cipher.data.length - last_block_len;
62 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
63 uint8_t *, last_block_offset);
65 if (unlikely((sym_op->m_dst != NULL)
66 && (sym_op->m_dst != sym_op->m_src)))
67 /* out-of-place operation (OOP) */
68 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
69 uint8_t *, last_block_offset);
73 if (last_block_len < sym_op->cipher.data.length)
74 /* use previous block ciphertext as IV */
75 iv = last_block - block_len;
77 /* runt block, i.e. less than one full block */
78 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
79 ctx->cipher_iv.offset);
81 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
82 QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: src before pre-process:",
83 last_block, last_block_len);
84 if (sym_op->m_dst != NULL)
85 QAT_DP_HEXDUMP_LOG(DEBUG, "BPI:dst before pre-process:",
88 bpi_cipher_decrypt(last_block, dst, iv, block_len,
89 last_block_len, ctx->bpi_ctx);
90 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
91 QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: src after pre-process:",
92 last_block, last_block_len);
93 if (sym_op->m_dst != NULL)
94 QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: dst after pre-process:",
99 return sym_op->cipher.data.length - last_block_len;
103 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
104 struct icp_qat_fw_la_cipher_req_params *cipher_param,
105 struct rte_crypto_op *op,
106 struct icp_qat_fw_la_bulk_req *qat_req)
108 /* copy IV into request if it fits */
109 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
110 rte_memcpy(cipher_param->u.cipher_IV_array,
111 rte_crypto_op_ctod_offset(op, uint8_t *,
115 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
116 qat_req->comn_hdr.serv_specif_flags,
117 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
118 cipher_param->u.s.cipher_IV_ptr =
119 rte_crypto_op_ctophys_offset(op,
124 /** Set IV for CCM is special case, 0th byte is set to q-1
125 * where q is padding of nonce in 16 byte block
128 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
129 struct icp_qat_fw_la_cipher_req_params *cipher_param,
130 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
132 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
133 ICP_QAT_HW_CCM_NONCE_OFFSET,
134 rte_crypto_op_ctod_offset(op, uint8_t *,
135 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
137 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
138 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
140 if (aad_len_field_sz)
141 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
142 rte_crypto_op_ctod_offset(op, uint8_t *,
143 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
147 /** Handle Single-Pass AES-GMAC on QAT GEN3 */
149 handle_spc_gmac(struct qat_sym_session *ctx, struct rte_crypto_op *op,
150 struct qat_sym_op_cookie *cookie,
151 struct icp_qat_fw_la_bulk_req *qat_req)
153 static const uint32_t ver_key_offset =
154 sizeof(struct icp_qat_hw_auth_setup) +
155 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
156 ICP_QAT_HW_GALOIS_H_SZ + ICP_QAT_HW_GALOIS_LEN_A_SZ +
157 ICP_QAT_HW_GALOIS_E_CTR0_SZ +
158 sizeof(struct icp_qat_hw_cipher_config);
159 struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl =
160 (void *) &qat_req->cd_ctrl;
161 struct icp_qat_fw_la_cipher_req_params *cipher_param =
162 (void *) &qat_req->serv_specif_rqpars;
163 uint32_t data_length = op->sym->auth.data.length;
165 /* Fill separate Content Descriptor for this op */
166 rte_memcpy(cookie->opt.spc_gmac.cd_cipher.key,
167 ctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?
169 RTE_PTR_ADD(&ctx->cd, ver_key_offset),
170 ctx->auth_key_length);
171 cookie->opt.spc_gmac.cd_cipher.cipher_config.val =
172 ICP_QAT_HW_CIPHER_CONFIG_BUILD(
173 ICP_QAT_HW_CIPHER_AEAD_MODE,
175 ICP_QAT_HW_CIPHER_NO_CONVERT,
176 (ctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?
177 ICP_QAT_HW_CIPHER_ENCRYPT :
178 ICP_QAT_HW_CIPHER_DECRYPT));
179 QAT_FIELD_SET(cookie->opt.spc_gmac.cd_cipher.cipher_config.val,
181 QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,
182 QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);
183 cookie->opt.spc_gmac.cd_cipher.cipher_config.reserved =
184 ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(data_length);
186 /* Update the request */
187 qat_req->cd_pars.u.s.content_desc_addr =
188 cookie->opt.spc_gmac.cd_phys_addr;
189 qat_req->cd_pars.u.s.content_desc_params_sz = RTE_ALIGN_CEIL(
190 sizeof(struct icp_qat_hw_cipher_config) +
191 ctx->auth_key_length, 8) >> 3;
192 qat_req->comn_mid.src_length = data_length;
193 qat_req->comn_mid.dst_length = 0;
195 cipher_param->spc_aad_addr = 0;
196 cipher_param->spc_auth_res_addr = op->sym->auth.digest.phys_addr;
197 cipher_param->spc_aad_sz = data_length;
198 cipher_param->reserved = 0;
199 cipher_param->spc_auth_res_sz = ctx->digest_length;
201 qat_req->comn_hdr.service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER;
202 cipher_cd_ctrl->cipher_cfg_offset = 0;
203 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);
204 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
205 ICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(
206 qat_req->comn_hdr.serv_specif_flags,
207 ICP_QAT_FW_LA_SINGLE_PASS_PROTO);
208 ICP_QAT_FW_LA_PROTO_SET(
209 qat_req->comn_hdr.serv_specif_flags,
210 ICP_QAT_FW_LA_NO_PROTO);
214 qat_sym_build_request(void *in_op, uint8_t *out_msg,
215 void *op_cookie, enum qat_device_gen qat_dev_gen)
218 struct qat_sym_session *ctx = NULL;
219 struct icp_qat_fw_la_cipher_req_params *cipher_param;
220 struct icp_qat_fw_la_auth_req_params *auth_param;
221 register struct icp_qat_fw_la_bulk_req *qat_req;
222 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
223 uint32_t cipher_len = 0, cipher_ofs = 0;
224 uint32_t auth_len = 0, auth_ofs = 0;
225 uint32_t min_ofs = 0;
226 uint64_t src_buf_start = 0, dst_buf_start = 0;
227 uint64_t auth_data_end = 0;
229 uint8_t in_place = 1;
230 int alignment_adjustment = 0;
232 struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
233 struct qat_sym_op_cookie *cookie =
234 (struct qat_sym_op_cookie *)op_cookie;
236 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
237 QAT_DP_LOG(ERR, "QAT PMD only supports symmetric crypto "
238 "operation requests, op (%p) is not a "
239 "symmetric operation.", op);
243 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
244 QAT_DP_LOG(ERR, "QAT PMD only supports session oriented"
245 " requests, op (%p) is sessionless.", op);
247 } else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
248 ctx = (struct qat_sym_session *)get_sym_session_private_data(
249 op->sym->session, qat_sym_driver_id);
250 #ifdef RTE_LIB_SECURITY
252 ctx = (struct qat_sym_session *)get_sec_session_private_data(
253 op->sym->sec_session);
255 if (unlikely(ctx->bpi_ctx == NULL)) {
256 QAT_DP_LOG(ERR, "QAT PMD only supports security"
257 " operation requests for"
258 " DOCSIS, op (%p) is not for"
261 } else if (unlikely(((op->sym->m_dst != NULL) &&
262 (op->sym->m_dst != op->sym->m_src)) ||
263 op->sym->m_src->nb_segs > 1)) {
264 QAT_DP_LOG(ERR, "OOP and/or multi-segment"
265 " buffers not supported for"
266 " DOCSIS security.");
267 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
274 if (unlikely(ctx == NULL)) {
275 QAT_DP_LOG(ERR, "Session was not created for this device");
279 if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
280 QAT_DP_LOG(ERR, "Session alg not supported on this device gen");
281 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
285 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
286 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
287 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
288 cipher_param = (void *)&qat_req->serv_specif_rqpars;
289 auth_param = (void *)((uint8_t *)cipher_param +
290 ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
292 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
293 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
294 /* AES-GCM or AES-CCM */
295 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
296 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
297 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
298 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
299 && ctx->qat_hash_alg ==
300 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
306 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
309 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
316 if (ctx->qat_cipher_alg ==
317 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
318 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
319 ctx->qat_cipher_alg ==
320 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
323 (op->sym->cipher.data.length % BYTE_LENGTH != 0) ||
324 (op->sym->cipher.data.offset % BYTE_LENGTH != 0))) {
326 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
327 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
330 cipher_len = op->sym->cipher.data.length >> 3;
331 cipher_ofs = op->sym->cipher.data.offset >> 3;
333 } else if (ctx->bpi_ctx) {
334 /* DOCSIS - only send complete blocks to device.
335 * Process any partial block using CFB mode.
336 * Even if 0 complete blocks, still send this to device
337 * to get into rx queue for post-process and dequeuing
339 cipher_len = qat_bpicipher_preprocess(ctx, op);
340 cipher_ofs = op->sym->cipher.data.offset;
342 cipher_len = op->sym->cipher.data.length;
343 cipher_ofs = op->sym->cipher.data.offset;
346 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
347 cipher_param, op, qat_req);
348 min_ofs = cipher_ofs;
353 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
354 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
356 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
358 (op->sym->auth.data.offset % BYTE_LENGTH != 0) ||
359 (op->sym->auth.data.length % BYTE_LENGTH != 0))) {
361 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
362 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
365 auth_ofs = op->sym->auth.data.offset >> 3;
366 auth_len = op->sym->auth.data.length >> 3;
368 auth_param->u1.aad_adr =
369 rte_crypto_op_ctophys_offset(op,
370 ctx->auth_iv.offset);
372 } else if (ctx->qat_hash_alg ==
373 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
375 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
377 set_cipher_iv(ctx->auth_iv.length,
379 cipher_param, op, qat_req);
380 auth_ofs = op->sym->auth.data.offset;
381 auth_len = op->sym->auth.data.length;
383 auth_param->u1.aad_adr = 0;
384 auth_param->u2.aad_sz = 0;
387 * If len(iv)==12B fw computes J0
389 if (ctx->auth_iv.length == 12) {
390 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
391 qat_req->comn_hdr.serv_specif_flags,
392 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
396 auth_ofs = op->sym->auth.data.offset;
397 auth_len = op->sym->auth.data.length;
402 auth_param->auth_res_addr =
403 op->sym->auth.digest.phys_addr;
409 * This address may used for setting AAD physical pointer
410 * into IV offset from op
412 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
413 if (ctx->qat_hash_alg ==
414 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
416 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
418 * If len(iv)==12B fw computes J0
420 if (ctx->cipher_iv.length == 12) {
421 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
422 qat_req->comn_hdr.serv_specif_flags,
423 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
425 set_cipher_iv(ctx->cipher_iv.length,
426 ctx->cipher_iv.offset,
427 cipher_param, op, qat_req);
429 } else if (ctx->qat_hash_alg ==
430 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
432 /* In case of AES-CCM this may point to user selected
433 * memory or iv offset in cypto_op
435 uint8_t *aad_data = op->sym->aead.aad.data;
436 /* This is true AAD length, it not includes 18 bytes of
439 uint8_t aad_ccm_real_len = 0;
440 uint8_t aad_len_field_sz = 0;
441 uint32_t msg_len_be =
442 rte_bswap32(op->sym->aead.data.length);
444 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
445 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
446 aad_ccm_real_len = ctx->aad_len -
447 ICP_QAT_HW_CCM_AAD_B0_LEN -
448 ICP_QAT_HW_CCM_AAD_LEN_INFO;
451 * aad_len not greater than 18, so no actual aad
452 * data, then use IV after op for B0 block
454 aad_data = rte_crypto_op_ctod_offset(op,
456 ctx->cipher_iv.offset);
458 rte_crypto_op_ctophys_offset(op,
459 ctx->cipher_iv.offset);
462 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
463 ctx->cipher_iv.length;
465 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
467 ctx->digest_length, q);
469 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
470 memcpy(aad_data + ctx->cipher_iv.length +
471 ICP_QAT_HW_CCM_NONCE_OFFSET +
472 (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
473 (uint8_t *)&msg_len_be,
474 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
476 memcpy(aad_data + ctx->cipher_iv.length +
477 ICP_QAT_HW_CCM_NONCE_OFFSET,
478 (uint8_t *)&msg_len_be
479 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
483 if (aad_len_field_sz > 0) {
484 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
485 = rte_bswap16(aad_ccm_real_len);
487 if ((aad_ccm_real_len + aad_len_field_sz)
488 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
492 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
493 ((aad_ccm_real_len + aad_len_field_sz) %
494 ICP_QAT_HW_CCM_AAD_B0_LEN);
495 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
496 aad_ccm_real_len + aad_len_field_sz;
497 memset(&aad_data[pad_idx],
503 set_cipher_iv_ccm(ctx->cipher_iv.length,
504 ctx->cipher_iv.offset,
510 cipher_len = op->sym->aead.data.length;
511 cipher_ofs = op->sym->aead.data.offset;
512 auth_len = op->sym->aead.data.length;
513 auth_ofs = op->sym->aead.data.offset;
515 auth_param->u1.aad_adr = aad_phys_addr_aead;
516 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
517 min_ofs = op->sym->aead.data.offset;
520 if (op->sym->m_src->nb_segs > 1 ||
521 (op->sym->m_dst && op->sym->m_dst->nb_segs > 1))
524 /* adjust for chain case */
525 if (do_cipher && do_auth)
526 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
528 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
531 if (unlikely((op->sym->m_dst != NULL) &&
532 (op->sym->m_dst != op->sym->m_src))) {
533 /* Out-of-place operation (OOP)
534 * Don't align DMA start. DMA the minimum data-set
535 * so as not to overwrite data in dest buffer
539 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
541 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
545 /* In-place operation
546 * Start DMA at nearest aligned address below min_ofs
549 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
550 & QAT_64_BTYE_ALIGN_MASK;
552 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
553 rte_pktmbuf_headroom(op->sym->m_src))
555 /* alignment has pushed addr ahead of start of mbuf
556 * so revert and take the performance hit
559 rte_pktmbuf_iova_offset(op->sym->m_src,
562 dst_buf_start = src_buf_start;
564 /* remember any adjustment for later, note, can be +/- */
565 alignment_adjustment = src_buf_start -
566 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
569 if (do_cipher || do_aead) {
570 cipher_param->cipher_offset =
571 (uint32_t)rte_pktmbuf_iova_offset(
572 op->sym->m_src, cipher_ofs) - src_buf_start;
573 cipher_param->cipher_length = cipher_len;
575 cipher_param->cipher_offset = 0;
576 cipher_param->cipher_length = 0;
579 if (do_auth || do_aead) {
580 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
581 op->sym->m_src, auth_ofs) - src_buf_start;
582 auth_param->auth_len = auth_len;
584 auth_param->auth_off = 0;
585 auth_param->auth_len = 0;
588 qat_req->comn_mid.dst_length =
589 qat_req->comn_mid.src_length =
590 (cipher_param->cipher_offset + cipher_param->cipher_length)
591 > (auth_param->auth_off + auth_param->auth_len) ?
592 (cipher_param->cipher_offset + cipher_param->cipher_length)
593 : (auth_param->auth_off + auth_param->auth_len);
595 if (do_auth && do_cipher) {
596 /* Handle digest-encrypted cases, i.e.
597 * auth-gen-then-cipher-encrypt and
598 * cipher-decrypt-then-auth-verify
600 /* First find the end of the data */
602 uint32_t remaining_off = auth_param->auth_off +
603 auth_param->auth_len + alignment_adjustment + oop_shift;
604 struct rte_mbuf *sgl_buf =
606 op->sym->m_src : op->sym->m_dst);
608 while (remaining_off >= rte_pktmbuf_data_len(sgl_buf)
609 && sgl_buf->next != NULL) {
610 remaining_off -= rte_pktmbuf_data_len(sgl_buf);
611 sgl_buf = sgl_buf->next;
614 auth_data_end = (uint64_t)rte_pktmbuf_iova_offset(
615 sgl_buf, remaining_off);
617 auth_data_end = (in_place ?
618 src_buf_start : dst_buf_start) +
619 auth_param->auth_off + auth_param->auth_len;
621 /* Then check if digest-encrypted conditions are met */
622 if ((auth_param->auth_off + auth_param->auth_len <
623 cipher_param->cipher_offset +
624 cipher_param->cipher_length) &&
625 (op->sym->auth.digest.phys_addr ==
627 /* Handle partial digest encryption */
628 if (cipher_param->cipher_offset +
629 cipher_param->cipher_length <
630 auth_param->auth_off +
631 auth_param->auth_len +
633 qat_req->comn_mid.dst_length =
634 qat_req->comn_mid.src_length =
635 auth_param->auth_off +
636 auth_param->auth_len +
638 struct icp_qat_fw_comn_req_hdr *header =
640 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
641 header->serv_specif_flags,
642 ICP_QAT_FW_LA_DIGEST_IN_BUFFER);
648 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
649 QAT_COMN_PTR_TYPE_SGL);
650 ret = qat_sgl_fill_array(op->sym->m_src,
651 (int64_t)(src_buf_start - rte_pktmbuf_iova(op->sym->m_src)),
652 &cookie->qat_sgl_src,
653 qat_req->comn_mid.src_length,
654 QAT_SYM_SGL_MAX_NUMBER);
657 QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array");
662 qat_req->comn_mid.dest_data_addr =
663 qat_req->comn_mid.src_data_addr =
664 cookie->qat_sgl_src_phys_addr;
666 ret = qat_sgl_fill_array(op->sym->m_dst,
667 (int64_t)(dst_buf_start -
668 rte_pktmbuf_iova(op->sym->m_dst)),
669 &cookie->qat_sgl_dst,
670 qat_req->comn_mid.dst_length,
671 QAT_SYM_SGL_MAX_NUMBER);
674 QAT_DP_LOG(ERR, "QAT PMD can't fill sgl array");
678 qat_req->comn_mid.src_data_addr =
679 cookie->qat_sgl_src_phys_addr;
680 qat_req->comn_mid.dest_data_addr =
681 cookie->qat_sgl_dst_phys_addr;
683 qat_req->comn_mid.src_length = 0;
684 qat_req->comn_mid.dst_length = 0;
686 qat_req->comn_mid.src_data_addr = src_buf_start;
687 qat_req->comn_mid.dest_data_addr = dst_buf_start;
690 if (ctx->is_single_pass) {
691 /* Handle Single-Pass GCM */
692 cipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;
693 cipher_param->spc_auth_res_addr =
694 op->sym->aead.digest.phys_addr;
695 } else if (ctx->is_single_pass_gmac &&
696 op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {
697 /* Handle Single-Pass AES-GMAC */
698 handle_spc_gmac(ctx, op, cookie, qat_req);
701 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
702 QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
703 sizeof(struct icp_qat_fw_la_bulk_req));
704 QAT_DP_HEXDUMP_LOG(DEBUG, "src_data:",
705 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
706 rte_pktmbuf_data_len(op->sym->m_src));
708 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
710 ctx->cipher_iv.offset);
711 QAT_DP_HEXDUMP_LOG(DEBUG, "cipher iv:", cipher_iv_ptr,
712 ctx->cipher_iv.length);
716 if (ctx->auth_iv.length) {
717 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
719 ctx->auth_iv.offset);
720 QAT_DP_HEXDUMP_LOG(DEBUG, "auth iv:", auth_iv_ptr,
721 ctx->auth_iv.length);
723 QAT_DP_HEXDUMP_LOG(DEBUG, "digest:", op->sym->auth.digest.data,
728 QAT_DP_HEXDUMP_LOG(DEBUG, "digest:", op->sym->aead.digest.data,
730 QAT_DP_HEXDUMP_LOG(DEBUG, "aad:", op->sym->aead.aad.data,