1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <openssl/evp.h>
7 #include <rte_mempool.h>
9 #include <rte_hexdump.h>
10 #include <rte_crypto_sym.h>
11 #include <rte_bus_pci.h>
12 #include <rte_byteorder.h>
15 #include "qat_sym_session.h"
17 #include "qat_sym_pmd.h"
20 /* bpi is only used for partial blocks of DES and AES
21 * so AES block len can be assumed as max len for iv, src and dst
23 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
25 /** Encrypt a single partial block
26 * Depends on openssl libcrypto
27 * Uses ECB+XOR to do CFB encryption, same result, more performant
30 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
31 uint8_t *iv, int ivlen, int srclen,
34 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
36 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
37 uint8_t *encr = encrypted_iv;
39 /* ECB method: encrypt the IV, then XOR this with plaintext */
40 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
42 goto cipher_encrypt_err;
44 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
50 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
54 /** Decrypt a single partial block
55 * Depends on openssl libcrypto
56 * Uses ECB+XOR to do CFB encryption, same result, more performant
59 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
60 uint8_t *iv, int ivlen, int srclen,
63 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
65 uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
66 uint8_t *encr = encrypted_iv;
68 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
69 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
71 goto cipher_decrypt_err;
73 for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
79 PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
84 static inline uint32_t
85 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
86 struct rte_crypto_op *op)
88 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
89 struct rte_crypto_sym_op *sym_op = op->sym;
90 uint8_t last_block_len = block_len > 0 ?
91 sym_op->cipher.data.length % block_len : 0;
94 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
96 /* Decrypt last block */
97 uint8_t *last_block, *dst, *iv;
98 uint32_t last_block_offset = sym_op->cipher.data.offset +
99 sym_op->cipher.data.length - last_block_len;
100 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
101 uint8_t *, last_block_offset);
103 if (unlikely(sym_op->m_dst != NULL))
104 /* out-of-place operation (OOP) */
105 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
106 uint8_t *, last_block_offset);
110 if (last_block_len < sym_op->cipher.data.length)
111 /* use previous block ciphertext as IV */
112 iv = last_block - block_len;
114 /* runt block, i.e. less than one full block */
115 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
116 ctx->cipher_iv.offset);
118 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
119 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
121 if (sym_op->m_dst != NULL)
122 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
125 bpi_cipher_decrypt(last_block, dst, iv, block_len,
126 last_block_len, ctx->bpi_ctx);
127 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
128 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
130 if (sym_op->m_dst != NULL)
131 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
136 return sym_op->cipher.data.length - last_block_len;
139 static inline uint32_t
140 qat_bpicipher_postprocess(struct qat_sym_session *ctx,
141 struct rte_crypto_op *op)
143 int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
144 struct rte_crypto_sym_op *sym_op = op->sym;
145 uint8_t last_block_len = block_len > 0 ?
146 sym_op->cipher.data.length % block_len : 0;
148 if (last_block_len > 0 &&
149 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
151 /* Encrypt last block */
152 uint8_t *last_block, *dst, *iv;
153 uint32_t last_block_offset;
155 last_block_offset = sym_op->cipher.data.offset +
156 sym_op->cipher.data.length - last_block_len;
157 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
158 uint8_t *, last_block_offset);
160 if (unlikely(sym_op->m_dst != NULL))
161 /* out-of-place operation (OOP) */
162 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
163 uint8_t *, last_block_offset);
167 if (last_block_len < sym_op->cipher.data.length)
168 /* use previous block ciphertext as IV */
169 iv = dst - block_len;
171 /* runt block, i.e. less than one full block */
172 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
173 ctx->cipher_iv.offset);
175 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
176 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
178 if (sym_op->m_dst != NULL)
179 rte_hexdump(stdout, "BPI: dst before post-process:",
180 dst, last_block_len);
182 bpi_cipher_encrypt(last_block, dst, iv, block_len,
183 last_block_len, ctx->bpi_ctx);
184 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
185 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
187 if (sym_op->m_dst != NULL)
188 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
192 return sym_op->cipher.data.length - last_block_len;
196 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
197 struct icp_qat_fw_la_cipher_req_params *cipher_param,
198 struct rte_crypto_op *op,
199 struct icp_qat_fw_la_bulk_req *qat_req)
201 /* copy IV into request if it fits */
202 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
203 rte_memcpy(cipher_param->u.cipher_IV_array,
204 rte_crypto_op_ctod_offset(op, uint8_t *,
208 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
209 qat_req->comn_hdr.serv_specif_flags,
210 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
211 cipher_param->u.s.cipher_IV_ptr =
212 rte_crypto_op_ctophys_offset(op,
217 /** Set IV for CCM is special case, 0th byte is set to q-1
218 * where q is padding of nonce in 16 byte block
221 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
222 struct icp_qat_fw_la_cipher_req_params *cipher_param,
223 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
225 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
226 ICP_QAT_HW_CCM_NONCE_OFFSET,
227 rte_crypto_op_ctod_offset(op, uint8_t *,
228 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
230 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
231 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
233 if (aad_len_field_sz)
234 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
235 rte_crypto_op_ctod_offset(op, uint8_t *,
236 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
241 qat_sym_build_request(void *in_op, uint8_t *out_msg,
242 void *op_cookie, enum qat_device_gen qat_dev_gen)
245 struct qat_sym_session *ctx;
246 struct icp_qat_fw_la_cipher_req_params *cipher_param;
247 struct icp_qat_fw_la_auth_req_params *auth_param;
248 register struct icp_qat_fw_la_bulk_req *qat_req;
249 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
250 uint32_t cipher_len = 0, cipher_ofs = 0;
251 uint32_t auth_len = 0, auth_ofs = 0;
252 uint32_t min_ofs = 0;
253 uint64_t src_buf_start = 0, dst_buf_start = 0;
255 struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
256 struct qat_sym_op_cookie *cookie =
257 (struct qat_sym_op_cookie *)op_cookie;
259 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
260 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
261 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
262 "operation requests, op (%p) is not a "
263 "symmetric operation.", op);
267 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
268 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
269 " requests, op (%p) is sessionless.", op);
273 ctx = (struct qat_sym_session *)get_session_private_data(
274 op->sym->session, cryptodev_qat_driver_id);
276 if (unlikely(ctx == NULL)) {
277 PMD_DRV_LOG(ERR, "Session was not created for this device");
281 if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
282 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
283 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
287 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
288 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
289 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
290 cipher_param = (void *)&qat_req->serv_specif_rqpars;
291 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
293 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
294 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
295 /* AES-GCM or AES-CCM */
296 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
297 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
298 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
299 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
300 && ctx->qat_hash_alg ==
301 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
307 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
310 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
317 if (ctx->qat_cipher_alg ==
318 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
319 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
320 ctx->qat_cipher_alg ==
321 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
324 (cipher_param->cipher_length % BYTE_LENGTH != 0)
325 || (cipher_param->cipher_offset
326 % BYTE_LENGTH != 0))) {
328 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
329 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
332 cipher_len = op->sym->cipher.data.length >> 3;
333 cipher_ofs = op->sym->cipher.data.offset >> 3;
335 } else if (ctx->bpi_ctx) {
336 /* DOCSIS - only send complete blocks to device
337 * Process any partial block using CFB mode.
338 * Even if 0 complete blocks, still send this to device
339 * to get into rx queue for post-process and dequeuing
341 cipher_len = qat_bpicipher_preprocess(ctx, op);
342 cipher_ofs = op->sym->cipher.data.offset;
344 cipher_len = op->sym->cipher.data.length;
345 cipher_ofs = op->sym->cipher.data.offset;
348 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
349 cipher_param, op, qat_req);
350 min_ofs = cipher_ofs;
355 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
356 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
358 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
359 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
360 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
362 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
363 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
366 auth_ofs = op->sym->auth.data.offset >> 3;
367 auth_len = op->sym->auth.data.length >> 3;
369 auth_param->u1.aad_adr =
370 rte_crypto_op_ctophys_offset(op,
371 ctx->auth_iv.offset);
373 } else if (ctx->qat_hash_alg ==
374 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
376 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
378 set_cipher_iv(ctx->auth_iv.length,
380 cipher_param, op, qat_req);
381 auth_ofs = op->sym->auth.data.offset;
382 auth_len = op->sym->auth.data.length;
384 auth_param->u1.aad_adr = 0;
385 auth_param->u2.aad_sz = 0;
388 * If len(iv)==12B fw computes J0
390 if (ctx->auth_iv.length == 12) {
391 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
392 qat_req->comn_hdr.serv_specif_flags,
393 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
397 auth_ofs = op->sym->auth.data.offset;
398 auth_len = op->sym->auth.data.length;
403 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
404 auth_param->auth_res_addr =
405 op->sym->auth.digest.phys_addr;
411 * This address may used for setting AAD physical pointer
412 * into IV offset from op
414 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
415 if (ctx->qat_hash_alg ==
416 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
418 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
420 * If len(iv)==12B fw computes J0
422 if (ctx->cipher_iv.length == 12) {
423 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
424 qat_req->comn_hdr.serv_specif_flags,
425 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
427 set_cipher_iv(ctx->cipher_iv.length,
428 ctx->cipher_iv.offset,
429 cipher_param, op, qat_req);
431 } else if (ctx->qat_hash_alg ==
432 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
434 /* In case of AES-CCM this may point to user selected
435 * memory or iv offset in cypto_op
437 uint8_t *aad_data = op->sym->aead.aad.data;
438 /* This is true AAD length, it not includes 18 bytes of
441 uint8_t aad_ccm_real_len = 0;
442 uint8_t aad_len_field_sz = 0;
443 uint32_t msg_len_be =
444 rte_bswap32(op->sym->aead.data.length);
446 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
447 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
448 aad_ccm_real_len = ctx->aad_len -
449 ICP_QAT_HW_CCM_AAD_B0_LEN -
450 ICP_QAT_HW_CCM_AAD_LEN_INFO;
453 * aad_len not greater than 18, so no actual aad
454 * data, then use IV after op for B0 block
456 aad_data = rte_crypto_op_ctod_offset(op,
458 ctx->cipher_iv.offset);
460 rte_crypto_op_ctophys_offset(op,
461 ctx->cipher_iv.offset);
464 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
465 ctx->cipher_iv.length;
467 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
469 ctx->digest_length, q);
471 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
472 memcpy(aad_data + ctx->cipher_iv.length +
473 ICP_QAT_HW_CCM_NONCE_OFFSET +
474 (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
475 (uint8_t *)&msg_len_be,
476 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
478 memcpy(aad_data + ctx->cipher_iv.length +
479 ICP_QAT_HW_CCM_NONCE_OFFSET,
480 (uint8_t *)&msg_len_be
481 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
485 if (aad_len_field_sz > 0) {
486 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
487 = rte_bswap16(aad_ccm_real_len);
489 if ((aad_ccm_real_len + aad_len_field_sz)
490 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
494 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
495 ((aad_ccm_real_len + aad_len_field_sz) %
496 ICP_QAT_HW_CCM_AAD_B0_LEN);
497 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
498 aad_ccm_real_len + aad_len_field_sz;
499 memset(&aad_data[pad_idx],
505 set_cipher_iv_ccm(ctx->cipher_iv.length,
506 ctx->cipher_iv.offset,
512 cipher_len = op->sym->aead.data.length;
513 cipher_ofs = op->sym->aead.data.offset;
514 auth_len = op->sym->aead.data.length;
515 auth_ofs = op->sym->aead.data.offset;
517 auth_param->u1.aad_adr = aad_phys_addr_aead;
518 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
519 min_ofs = op->sym->aead.data.offset;
522 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
525 /* adjust for chain case */
526 if (do_cipher && do_auth)
527 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
529 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
532 if (unlikely(op->sym->m_dst != NULL)) {
533 /* Out-of-place operation (OOP)
534 * Don't align DMA start. DMA the minimum data-set
535 * so as not to overwrite data in dest buffer
538 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
540 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
543 /* In-place operation
544 * Start DMA at nearest aligned address below min_ofs
547 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
548 & QAT_64_BTYE_ALIGN_MASK;
550 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
551 rte_pktmbuf_headroom(op->sym->m_src))
553 /* alignment has pushed addr ahead of start of mbuf
554 * so revert and take the performance hit
557 rte_pktmbuf_iova_offset(op->sym->m_src,
560 dst_buf_start = src_buf_start;
563 if (do_cipher || do_aead) {
564 cipher_param->cipher_offset =
565 (uint32_t)rte_pktmbuf_iova_offset(
566 op->sym->m_src, cipher_ofs) - src_buf_start;
567 cipher_param->cipher_length = cipher_len;
569 cipher_param->cipher_offset = 0;
570 cipher_param->cipher_length = 0;
573 if (do_auth || do_aead) {
574 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
575 op->sym->m_src, auth_ofs) - src_buf_start;
576 auth_param->auth_len = auth_len;
578 auth_param->auth_off = 0;
579 auth_param->auth_len = 0;
582 qat_req->comn_mid.dst_length =
583 qat_req->comn_mid.src_length =
584 (cipher_param->cipher_offset + cipher_param->cipher_length)
585 > (auth_param->auth_off + auth_param->auth_len) ?
586 (cipher_param->cipher_offset + cipher_param->cipher_length)
587 : (auth_param->auth_off + auth_param->auth_len);
591 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
592 QAT_COMN_PTR_TYPE_SGL);
593 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
594 &cookie->qat_sgl_src,
595 qat_req->comn_mid.src_length);
597 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
601 if (likely(op->sym->m_dst == NULL))
602 qat_req->comn_mid.dest_data_addr =
603 qat_req->comn_mid.src_data_addr =
604 cookie->qat_sgl_src_phys_addr;
606 ret = qat_sgl_fill_array(op->sym->m_dst,
608 &cookie->qat_sgl_dst,
609 qat_req->comn_mid.dst_length);
612 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
617 qat_req->comn_mid.src_data_addr =
618 cookie->qat_sgl_src_phys_addr;
619 qat_req->comn_mid.dest_data_addr =
620 cookie->qat_sgl_dst_phys_addr;
623 qat_req->comn_mid.src_data_addr = src_buf_start;
624 qat_req->comn_mid.dest_data_addr = dst_buf_start;
627 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
628 rte_hexdump(stdout, "qat_req:", qat_req,
629 sizeof(struct icp_qat_fw_la_bulk_req));
630 rte_hexdump(stdout, "src_data:",
631 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
632 rte_pktmbuf_data_len(op->sym->m_src));
634 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
636 ctx->cipher_iv.offset);
637 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
638 ctx->cipher_iv.length);
642 if (ctx->auth_iv.length) {
643 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
645 ctx->auth_iv.offset);
646 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
647 ctx->auth_iv.length);
649 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
654 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
656 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
664 qat_sym_process_response(void **op, uint8_t *resp)
667 struct icp_qat_fw_comn_resp *resp_msg =
668 (struct icp_qat_fw_comn_resp *)resp;
669 struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
670 (resp_msg->opaque_data);
672 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
673 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
674 sizeof(struct icp_qat_fw_comn_resp));
677 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
678 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
679 resp_msg->comn_hdr.comn_status)) {
681 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
683 struct qat_sym_session *sess = (struct qat_sym_session *)
684 get_session_private_data(
686 cryptodev_qat_driver_id);
689 qat_bpicipher_postprocess(sess, rx_op);
690 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;