1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2022 Intel Corporation
5 #include <openssl/evp.h>
7 #include <rte_mempool.h>
9 #include <rte_crypto_sym.h>
10 #include <rte_bus_pci.h>
11 #include <rte_byteorder.h>
14 #include "dev/qat_crypto_pmd_gens.h"
17 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
18 struct icp_qat_fw_la_cipher_req_params *cipher_param,
19 struct rte_crypto_op *op,
20 struct icp_qat_fw_la_bulk_req *qat_req)
22 /* copy IV into request if it fits */
23 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
24 rte_memcpy(cipher_param->u.cipher_IV_array,
25 rte_crypto_op_ctod_offset(op, uint8_t *,
29 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
30 qat_req->comn_hdr.serv_specif_flags,
31 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
32 cipher_param->u.s.cipher_IV_ptr =
33 rte_crypto_op_ctophys_offset(op,
38 /** Set IV for CCM is special case, 0th byte is set to q-1
39 * where q is padding of nonce in 16 byte block
42 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
43 struct icp_qat_fw_la_cipher_req_params *cipher_param,
44 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
46 rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
47 ICP_QAT_HW_CCM_NONCE_OFFSET,
48 rte_crypto_op_ctod_offset(op, uint8_t *,
49 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
51 *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
52 q - ICP_QAT_HW_CCM_NONCE_OFFSET;
55 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
56 rte_crypto_op_ctod_offset(op, uint8_t *,
57 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
61 /** Handle Single-Pass AES-GMAC on QAT GEN3 */
63 handle_spc_gmac(struct qat_sym_session *ctx, struct rte_crypto_op *op,
64 struct qat_sym_op_cookie *cookie,
65 struct icp_qat_fw_la_bulk_req *qat_req)
67 static const uint32_t ver_key_offset =
68 sizeof(struct icp_qat_hw_auth_setup) +
69 ICP_QAT_HW_GALOIS_128_STATE1_SZ +
70 ICP_QAT_HW_GALOIS_H_SZ + ICP_QAT_HW_GALOIS_LEN_A_SZ +
71 ICP_QAT_HW_GALOIS_E_CTR0_SZ +
72 sizeof(struct icp_qat_hw_cipher_config);
73 struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl =
74 (void *) &qat_req->cd_ctrl;
75 struct icp_qat_fw_la_cipher_req_params *cipher_param =
76 (void *) &qat_req->serv_specif_rqpars;
77 uint32_t data_length = op->sym->auth.data.length;
79 /* Fill separate Content Descriptor for this op */
80 rte_memcpy(cookie->opt.spc_gmac.cd_cipher.key,
81 ctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?
83 RTE_PTR_ADD(&ctx->cd, ver_key_offset),
84 ctx->auth_key_length);
85 cookie->opt.spc_gmac.cd_cipher.cipher_config.val =
86 ICP_QAT_HW_CIPHER_CONFIG_BUILD(
87 ICP_QAT_HW_CIPHER_AEAD_MODE,
89 ICP_QAT_HW_CIPHER_NO_CONVERT,
90 (ctx->auth_op == ICP_QAT_HW_AUTH_GENERATE ?
91 ICP_QAT_HW_CIPHER_ENCRYPT :
92 ICP_QAT_HW_CIPHER_DECRYPT));
93 QAT_FIELD_SET(cookie->opt.spc_gmac.cd_cipher.cipher_config.val,
95 QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,
96 QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);
97 cookie->opt.spc_gmac.cd_cipher.cipher_config.reserved =
98 ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(data_length);
100 /* Update the request */
101 qat_req->cd_pars.u.s.content_desc_addr =
102 cookie->opt.spc_gmac.cd_phys_addr;
103 qat_req->cd_pars.u.s.content_desc_params_sz = RTE_ALIGN_CEIL(
104 sizeof(struct icp_qat_hw_cipher_config) +
105 ctx->auth_key_length, 8) >> 3;
106 qat_req->comn_mid.src_length = data_length;
107 qat_req->comn_mid.dst_length = 0;
109 cipher_param->spc_aad_addr = 0;
110 cipher_param->spc_auth_res_addr = op->sym->auth.digest.phys_addr;
111 cipher_param->spc_aad_sz = data_length;
112 cipher_param->reserved = 0;
113 cipher_param->spc_auth_res_sz = ctx->digest_length;
115 qat_req->comn_hdr.service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER;
116 cipher_cd_ctrl->cipher_cfg_offset = 0;
117 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);
118 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
119 ICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(
120 qat_req->comn_hdr.serv_specif_flags,
121 ICP_QAT_FW_LA_SINGLE_PASS_PROTO);
122 ICP_QAT_FW_LA_PROTO_SET(
123 qat_req->comn_hdr.serv_specif_flags,
124 ICP_QAT_FW_LA_NO_PROTO);
128 qat_sym_build_request(void *in_op, uint8_t *out_msg,
129 void *op_cookie, enum qat_device_gen qat_dev_gen)
132 struct qat_sym_session *ctx = NULL;
133 struct icp_qat_fw_la_cipher_req_params *cipher_param;
134 struct icp_qat_fw_la_cipher_20_req_params *cipher_param20;
135 struct icp_qat_fw_la_auth_req_params *auth_param;
136 register struct icp_qat_fw_la_bulk_req *qat_req;
137 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
138 uint32_t cipher_len = 0, cipher_ofs = 0;
139 uint32_t auth_len = 0, auth_ofs = 0;
140 uint32_t min_ofs = 0;
141 uint64_t src_buf_start = 0, dst_buf_start = 0;
142 uint64_t auth_data_end = 0;
144 uint8_t in_place = 1;
145 int alignment_adjustment = 0;
147 struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
148 struct qat_sym_op_cookie *cookie =
149 (struct qat_sym_op_cookie *)op_cookie;
151 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
152 QAT_DP_LOG(ERR, "QAT PMD only supports symmetric crypto "
153 "operation requests, op (%p) is not a "
154 "symmetric operation.", op);
158 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
159 QAT_DP_LOG(ERR, "QAT PMD only supports session oriented"
160 " requests, op (%p) is sessionless.", op);
162 } else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
163 ctx = (struct qat_sym_session *)get_sym_session_private_data(
164 op->sym->session, qat_sym_driver_id);
165 #ifdef RTE_LIB_SECURITY
167 ctx = (struct qat_sym_session *)get_sec_session_private_data(
168 op->sym->sec_session);
170 if (unlikely(ctx->bpi_ctx == NULL)) {
171 QAT_DP_LOG(ERR, "QAT PMD only supports security"
172 " operation requests for"
173 " DOCSIS, op (%p) is not for"
176 } else if (unlikely(((op->sym->m_dst != NULL) &&
177 (op->sym->m_dst != op->sym->m_src)) ||
178 op->sym->m_src->nb_segs > 1)) {
179 QAT_DP_LOG(ERR, "OOP and/or multi-segment"
180 " buffers not supported for"
181 " DOCSIS security.");
182 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
189 if (unlikely(ctx == NULL)) {
190 QAT_DP_LOG(ERR, "Session was not created for this device");
194 if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
195 QAT_DP_LOG(ERR, "Session alg not supported on this device gen");
196 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
200 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
201 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
202 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
203 cipher_param = (void *)&qat_req->serv_specif_rqpars;
204 cipher_param20 = (void *)&qat_req->serv_specif_rqpars;
205 auth_param = (void *)((uint8_t *)cipher_param +
206 ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
208 if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
209 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&
211 /* AES-GCM or AES-CCM */
212 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
213 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
214 (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
215 && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
216 && ctx->qat_hash_alg ==
217 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
223 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH || ctx->is_gmac) {
226 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
233 if (ctx->qat_cipher_alg ==
234 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
235 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
236 ctx->qat_cipher_alg ==
237 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
240 (op->sym->cipher.data.length % BYTE_LENGTH != 0) ||
241 (op->sym->cipher.data.offset % BYTE_LENGTH != 0))) {
243 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
244 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
247 cipher_len = op->sym->cipher.data.length >> 3;
248 cipher_ofs = op->sym->cipher.data.offset >> 3;
250 } else if (ctx->bpi_ctx) {
251 /* DOCSIS - only send complete blocks to device.
252 * Process any partial block using CFB mode.
253 * Even if 0 complete blocks, still send this to device
254 * to get into rx queue for post-process and dequeuing
256 cipher_len = qat_bpicipher_preprocess(ctx, op);
257 cipher_ofs = op->sym->cipher.data.offset;
259 cipher_len = op->sym->cipher.data.length;
260 cipher_ofs = op->sym->cipher.data.offset;
263 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
264 cipher_param, op, qat_req);
265 min_ofs = cipher_ofs;
270 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
271 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
273 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
275 (op->sym->auth.data.offset % BYTE_LENGTH != 0) ||
276 (op->sym->auth.data.length % BYTE_LENGTH != 0))) {
278 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
279 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
282 auth_ofs = op->sym->auth.data.offset >> 3;
283 auth_len = op->sym->auth.data.length >> 3;
285 auth_param->u1.aad_adr =
286 rte_crypto_op_ctophys_offset(op,
287 ctx->auth_iv.offset);
289 } else if (ctx->qat_hash_alg ==
290 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
292 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
294 set_cipher_iv(ctx->auth_iv.length,
296 cipher_param, op, qat_req);
297 auth_ofs = op->sym->auth.data.offset;
298 auth_len = op->sym->auth.data.length;
300 auth_param->u1.aad_adr = 0;
301 auth_param->u2.aad_sz = 0;
304 auth_ofs = op->sym->auth.data.offset;
305 auth_len = op->sym->auth.data.length;
310 if (ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL ||
311 ctx->auth_op == ICP_QAT_HW_AUTH_VERIFY)
312 auth_param->auth_res_addr =
313 op->sym->auth.digest.phys_addr;
319 * This address may used for setting AAD physical pointer
320 * into IV offset from op
322 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
323 if (ctx->qat_hash_alg ==
324 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
326 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
328 set_cipher_iv(ctx->cipher_iv.length,
329 ctx->cipher_iv.offset,
330 cipher_param, op, qat_req);
332 } else if (ctx->qat_hash_alg ==
333 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
335 /* In case of AES-CCM this may point to user selected
336 * memory or iv offset in crypto_op
338 uint8_t *aad_data = op->sym->aead.aad.data;
339 /* This is true AAD length, it not includes 18 bytes of
342 uint8_t aad_ccm_real_len = 0;
343 uint8_t aad_len_field_sz = 0;
344 uint32_t msg_len_be =
345 rte_bswap32(op->sym->aead.data.length);
347 if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
348 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
349 aad_ccm_real_len = ctx->aad_len -
350 ICP_QAT_HW_CCM_AAD_B0_LEN -
351 ICP_QAT_HW_CCM_AAD_LEN_INFO;
354 * aad_len not greater than 18, so no actual aad
355 * data, then use IV after op for B0 block
357 aad_data = rte_crypto_op_ctod_offset(op,
359 ctx->cipher_iv.offset);
361 rte_crypto_op_ctophys_offset(op,
362 ctx->cipher_iv.offset);
365 uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
366 ctx->cipher_iv.length;
368 aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
370 ctx->digest_length, q);
372 if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
373 memcpy(aad_data + ctx->cipher_iv.length +
374 ICP_QAT_HW_CCM_NONCE_OFFSET +
375 (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
376 (uint8_t *)&msg_len_be,
377 ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
379 memcpy(aad_data + ctx->cipher_iv.length +
380 ICP_QAT_HW_CCM_NONCE_OFFSET,
381 (uint8_t *)&msg_len_be
382 + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
386 if (aad_len_field_sz > 0) {
387 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
388 = rte_bswap16(aad_ccm_real_len);
390 if ((aad_ccm_real_len + aad_len_field_sz)
391 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
395 pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
396 ((aad_ccm_real_len + aad_len_field_sz) %
397 ICP_QAT_HW_CCM_AAD_B0_LEN);
398 pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
399 aad_ccm_real_len + aad_len_field_sz;
400 memset(&aad_data[pad_idx],
406 set_cipher_iv_ccm(ctx->cipher_iv.length,
407 ctx->cipher_iv.offset,
413 cipher_len = op->sym->aead.data.length;
414 cipher_ofs = op->sym->aead.data.offset;
415 auth_len = op->sym->aead.data.length;
416 auth_ofs = op->sym->aead.data.offset;
418 auth_param->u1.aad_adr = aad_phys_addr_aead;
419 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
420 min_ofs = op->sym->aead.data.offset;
423 if (op->sym->m_src->nb_segs > 1 ||
424 (op->sym->m_dst && op->sym->m_dst->nb_segs > 1))
427 /* adjust for chain case */
428 if (do_cipher && do_auth)
429 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
431 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
434 if (unlikely((op->sym->m_dst != NULL) &&
435 (op->sym->m_dst != op->sym->m_src))) {
436 /* Out-of-place operation (OOP)
437 * Don't align DMA start. DMA the minimum data-set
438 * so as not to overwrite data in dest buffer
442 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
444 rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
448 /* In-place operation
449 * Start DMA at nearest aligned address below min_ofs
452 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
453 & QAT_64_BTYE_ALIGN_MASK;
455 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
456 rte_pktmbuf_headroom(op->sym->m_src))
458 /* alignment has pushed addr ahead of start of mbuf
459 * so revert and take the performance hit
462 rte_pktmbuf_iova_offset(op->sym->m_src,
465 dst_buf_start = src_buf_start;
467 /* remember any adjustment for later, note, can be +/- */
468 alignment_adjustment = src_buf_start -
469 rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
472 if (do_cipher || do_aead) {
473 cipher_param->cipher_offset =
474 (uint32_t)rte_pktmbuf_iova_offset(
475 op->sym->m_src, cipher_ofs) - src_buf_start;
476 cipher_param->cipher_length = cipher_len;
478 cipher_param->cipher_offset = 0;
479 cipher_param->cipher_length = 0;
482 if (!ctx->is_single_pass) {
483 /* Do not let to overwrite spc_aad len */
484 if (do_auth || do_aead) {
485 auth_param->auth_off =
486 (uint32_t)rte_pktmbuf_iova_offset(
487 op->sym->m_src, auth_ofs) - src_buf_start;
488 auth_param->auth_len = auth_len;
490 auth_param->auth_off = 0;
491 auth_param->auth_len = 0;
495 qat_req->comn_mid.dst_length =
496 qat_req->comn_mid.src_length =
497 (cipher_param->cipher_offset + cipher_param->cipher_length)
498 > (auth_param->auth_off + auth_param->auth_len) ?
499 (cipher_param->cipher_offset + cipher_param->cipher_length)
500 : (auth_param->auth_off + auth_param->auth_len);
502 if (do_auth && do_cipher) {
503 /* Handle digest-encrypted cases, i.e.
504 * auth-gen-then-cipher-encrypt and
505 * cipher-decrypt-then-auth-verify
507 /* First find the end of the data */
509 uint32_t remaining_off = auth_param->auth_off +
510 auth_param->auth_len + alignment_adjustment + oop_shift;
511 struct rte_mbuf *sgl_buf =
513 op->sym->m_src : op->sym->m_dst);
515 while (remaining_off >= rte_pktmbuf_data_len(sgl_buf)
516 && sgl_buf->next != NULL) {
517 remaining_off -= rte_pktmbuf_data_len(sgl_buf);
518 sgl_buf = sgl_buf->next;
521 auth_data_end = (uint64_t)rte_pktmbuf_iova_offset(
522 sgl_buf, remaining_off);
524 auth_data_end = (in_place ?
525 src_buf_start : dst_buf_start) +
526 auth_param->auth_off + auth_param->auth_len;
528 /* Then check if digest-encrypted conditions are met */
529 if ((auth_param->auth_off + auth_param->auth_len <
530 cipher_param->cipher_offset +
531 cipher_param->cipher_length) &&
532 (op->sym->auth.digest.phys_addr ==
534 /* Handle partial digest encryption */
535 if (cipher_param->cipher_offset +
536 cipher_param->cipher_length <
537 auth_param->auth_off +
538 auth_param->auth_len +
540 qat_req->comn_mid.dst_length =
541 qat_req->comn_mid.src_length =
542 auth_param->auth_off +
543 auth_param->auth_len +
545 struct icp_qat_fw_comn_req_hdr *header =
547 ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
548 header->serv_specif_flags,
549 ICP_QAT_FW_LA_DIGEST_IN_BUFFER);
555 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
556 QAT_COMN_PTR_TYPE_SGL);
557 ret = qat_sgl_fill_array(op->sym->m_src,
558 (int64_t)(src_buf_start - rte_pktmbuf_iova(op->sym->m_src)),
559 &cookie->qat_sgl_src,
560 qat_req->comn_mid.src_length,
561 QAT_SYM_SGL_MAX_NUMBER);
564 QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array");
569 qat_req->comn_mid.dest_data_addr =
570 qat_req->comn_mid.src_data_addr =
571 cookie->qat_sgl_src_phys_addr;
573 ret = qat_sgl_fill_array(op->sym->m_dst,
574 (int64_t)(dst_buf_start -
575 rte_pktmbuf_iova(op->sym->m_dst)),
576 &cookie->qat_sgl_dst,
577 qat_req->comn_mid.dst_length,
578 QAT_SYM_SGL_MAX_NUMBER);
581 QAT_DP_LOG(ERR, "QAT PMD can't fill sgl array");
585 qat_req->comn_mid.src_data_addr =
586 cookie->qat_sgl_src_phys_addr;
587 qat_req->comn_mid.dest_data_addr =
588 cookie->qat_sgl_dst_phys_addr;
590 qat_req->comn_mid.src_length = 0;
591 qat_req->comn_mid.dst_length = 0;
593 qat_req->comn_mid.src_data_addr = src_buf_start;
594 qat_req->comn_mid.dest_data_addr = dst_buf_start;
597 if (ctx->is_single_pass) {
600 cipher_param20->spc_aad_addr =
601 op->sym->aead.aad.phys_addr;
602 cipher_param20->spc_auth_res_addr =
603 op->sym->aead.digest.phys_addr;
605 cipher_param->spc_aad_addr =
606 op->sym->aead.aad.phys_addr;
607 cipher_param->spc_auth_res_addr =
608 op->sym->aead.digest.phys_addr;
610 } else if (ctx->is_single_pass_gmac &&
611 op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {
612 /* Handle Single-Pass AES-GMAC */
613 handle_spc_gmac(ctx, op, cookie, qat_req);
616 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
617 QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
618 sizeof(struct icp_qat_fw_la_bulk_req));
619 QAT_DP_HEXDUMP_LOG(DEBUG, "src_data:",
620 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
621 rte_pktmbuf_data_len(op->sym->m_src));
623 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
625 ctx->cipher_iv.offset);
626 QAT_DP_HEXDUMP_LOG(DEBUG, "cipher iv:", cipher_iv_ptr,
627 ctx->cipher_iv.length);
631 if (ctx->auth_iv.length) {
632 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
634 ctx->auth_iv.offset);
635 QAT_DP_HEXDUMP_LOG(DEBUG, "auth iv:", auth_iv_ptr,
636 ctx->auth_iv.length);
638 QAT_DP_HEXDUMP_LOG(DEBUG, "digest:", op->sym->auth.digest.data,
643 QAT_DP_HEXDUMP_LOG(DEBUG, "digest:", op->sym->aead.digest.data,
645 QAT_DP_HEXDUMP_LOG(DEBUG, "aad:", op->sym->aead.aad.data,