1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2021 Marvell International Ltd.
9 #include <rte_bus_pci.h>
10 #include <rte_common.h>
12 #include <rte_lcore.h>
13 #include <rte_mempool.h>
15 #include <rte_dmadev.h>
16 #include <rte_dmadev_pmd.h>
19 #include <cnxk_dmadev.h>
22 cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
23 struct rte_dma_info *dev_info, uint32_t size)
28 dev_info->max_vchans = 1;
29 dev_info->nb_vchans = 1;
30 dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
31 RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
32 RTE_DMA_CAPA_DEV_TO_DEV | RTE_DMA_CAPA_OPS_COPY |
33 RTE_DMA_CAPA_OPS_COPY_SG;
34 dev_info->max_desc = DPI_MAX_DESC;
35 dev_info->min_desc = 1;
36 dev_info->max_sges = DPI_MAX_POINTER;
42 cnxk_dmadev_configure(struct rte_dma_dev *dev,
43 const struct rte_dma_conf *conf, uint32_t conf_sz)
45 struct cnxk_dpi_vf_s *dpivf = NULL;
50 RTE_SET_USED(conf_sz);
51 RTE_SET_USED(conf_sz);
52 dpivf = dev->fp_obj->dev_private;
53 rc = roc_dpi_configure(&dpivf->rdpi);
55 plt_err("DMA configure failed err = %d", rc);
61 cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
62 const struct rte_dma_vchan_conf *conf,
65 struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
66 struct cnxk_dpi_compl_s *comp_data;
67 union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
71 RTE_SET_USED(conf_sz);
73 header->s.pt = DPI_HDR_PT_ZBW_CA;
75 switch (conf->direction) {
76 case RTE_DMA_DIR_DEV_TO_MEM:
77 header->s.xtype = DPI_XTYPE_INBOUND;
78 header->s.lport = conf->src_port.pcie.coreid;
82 case RTE_DMA_DIR_MEM_TO_DEV:
83 header->s.xtype = DPI_XTYPE_OUTBOUND;
85 header->s.fport = conf->dst_port.pcie.coreid;
88 case RTE_DMA_DIR_MEM_TO_MEM:
89 header->s.xtype = DPI_XTYPE_INTERNAL_ONLY;
94 case RTE_DMA_DIR_DEV_TO_DEV:
95 header->s.xtype = DPI_XTYPE_EXTERNAL_ONLY;
96 header->s.lport = conf->src_port.pcie.coreid;
97 header->s.fport = conf->dst_port.pcie.coreid;
100 for (i = 0; i < conf->nb_desc; i++) {
101 comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
102 if (comp_data == NULL) {
103 plt_err("Failed to allocate for comp_data");
106 dpivf->conf.c_desc.compl_ptr[i] = comp_data;
108 dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
109 dpivf->conf.c_desc.head = 0;
110 dpivf->conf.c_desc.tail = 0;
116 cnxk_dmadev_start(struct rte_dma_dev *dev)
118 struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
121 dpivf->num_words = 0;
122 roc_dpi_enable(&dpivf->rdpi);
128 cnxk_dmadev_stop(struct rte_dma_dev *dev)
130 struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
132 roc_dpi_disable(&dpivf->rdpi);
138 cnxk_dmadev_close(struct rte_dma_dev *dev)
140 struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
142 roc_dpi_disable(&dpivf->rdpi);
143 roc_dpi_dev_fini(&dpivf->rdpi);
149 __dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
151 uint64_t *ptr = dpi->chunk_base;
153 if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
158 * Normally there is plenty of room in the current buffer for the
161 if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
162 ptr += dpi->chunk_head;
163 dpi->chunk_head += cmd_count;
168 uint64_t *new_buff = dpi->chunk_next;
171 (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
172 if (!dpi->chunk_next) {
173 plt_err("Failed to alloc next buffer from NPA");
178 * Figure out how many cmd words will fit in this buffer.
179 * One location will be needed for the next buffer pointer.
181 count = dpi->pool_size_m1 - dpi->chunk_head;
182 ptr += dpi->chunk_head;
188 * chunk next ptr is 2 DWORDS
189 * second DWORD is reserved.
191 *ptr++ = (uint64_t)new_buff;
195 * The current buffer is full and has a link to the next
196 * buffers. Time to write the rest of the commands into the new
199 dpi->chunk_base = new_buff;
200 dpi->chunk_head = cmd_count;
205 /* queue index may be greater than pool size */
206 if (dpi->chunk_head >= dpi->pool_size_m1) {
207 new_buff = dpi->chunk_next;
209 (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
211 if (!dpi->chunk_next) {
212 plt_err("Failed to alloc next buffer from NPA");
215 /* Write next buffer address */
216 *ptr = (uint64_t)new_buff;
217 dpi->chunk_base = new_buff;
226 cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
227 rte_iova_t dst, uint32_t length, uint64_t flags)
229 struct cnxk_dpi_vf_s *dpivf = dev_private;
230 union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
231 struct cnxk_dpi_compl_s *comp_ptr;
232 rte_iova_t fptr, lptr;
238 comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
239 comp_ptr->cdata = DPI_REQ_CDATA;
240 header->s.ptr = (uint64_t)comp_ptr;
241 STRM_INC(dpivf->conf.c_desc);
247 * For inbound case, src pointers are last pointers.
248 * For all other cases, src pointers are first pointers.
250 if (header->s.xtype == DPI_XTYPE_INBOUND) {
258 dpivf->cmd[0] = header->u[0];
259 dpivf->cmd[1] = header->u[1];
260 dpivf->cmd[2] = header->u[2];
261 /* word3 is always 0 */
263 dpivf->cmd[num_words++] = length;
264 dpivf->cmd[num_words++] = fptr;
265 dpivf->cmd[num_words++] = length;
266 dpivf->cmd[num_words++] = lptr;
268 rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
270 if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
272 plt_write64(num_words,
273 dpivf->rdpi.rbase + DPI_VDMA_DBELL);
275 dpivf->num_words += num_words;
278 return dpivf->desc_idx++;
282 cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
283 const struct rte_dma_sge *src,
284 const struct rte_dma_sge *dst,
285 uint16_t nb_src, uint16_t nb_dst, uint64_t flags)
287 struct cnxk_dpi_vf_s *dpivf = dev_private;
288 union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
289 const struct rte_dma_sge *fptr, *lptr;
290 struct cnxk_dpi_compl_s *comp_ptr;
296 comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
297 comp_ptr->cdata = DPI_REQ_CDATA;
298 header->s.ptr = (uint64_t)comp_ptr;
299 STRM_INC(dpivf->conf.c_desc);
302 * For inbound case, src pointers are last pointers.
303 * For all other cases, src pointers are first pointers.
305 if (header->s.xtype == DPI_XTYPE_INBOUND) {
306 header->s.nfst = nb_dst & 0xf;
307 header->s.nlst = nb_src & 0xf;
311 header->s.nfst = nb_src & 0xf;
312 header->s.nlst = nb_dst & 0xf;
317 dpivf->cmd[0] = header->u[0];
318 dpivf->cmd[1] = header->u[1];
319 dpivf->cmd[2] = header->u[2];
321 for (i = 0; i < header->s.nfst; i++) {
322 dpivf->cmd[num_words++] = (uint64_t)fptr->length;
323 dpivf->cmd[num_words++] = fptr->addr;
327 for (i = 0; i < header->s.nlst; i++) {
328 dpivf->cmd[num_words++] = (uint64_t)lptr->length;
329 dpivf->cmd[num_words++] = lptr->addr;
333 rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
335 if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
337 plt_write64(num_words,
338 dpivf->rdpi.rbase + DPI_VDMA_DBELL);
340 dpivf->num_words += num_words;
343 return dpivf->desc_idx++;
347 cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
348 uint16_t *last_idx, bool *has_error)
350 struct cnxk_dpi_vf_s *dpivf = dev_private;
354 for (cnt = 0; cnt < nb_cpls; cnt++) {
355 struct cnxk_dpi_compl_s *comp_ptr =
356 dpivf->conf.c_desc.compl_ptr[cnt];
358 if (comp_ptr->cdata) {
365 dpivf->conf.c_desc.tail = cnt;
371 cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
372 const uint16_t nb_cpls, uint16_t *last_idx,
373 enum rte_dma_status_code *status)
375 struct cnxk_dpi_vf_s *dpivf = dev_private;
379 RTE_SET_USED(last_idx);
380 for (cnt = 0; cnt < nb_cpls; cnt++) {
381 struct cnxk_dpi_compl_s *comp_ptr =
382 dpivf->conf.c_desc.compl_ptr[cnt];
383 status[cnt] = comp_ptr->cdata;
387 dpivf->conf.c_desc.tail = 0;
393 cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
395 struct cnxk_dpi_vf_s *dpivf = dev_private;
398 plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
403 static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
404 .dev_close = cnxk_dmadev_close,
405 .dev_configure = cnxk_dmadev_configure,
406 .dev_info_get = cnxk_dmadev_info_get,
407 .dev_start = cnxk_dmadev_start,
408 .dev_stop = cnxk_dmadev_stop,
409 .vchan_setup = cnxk_dmadev_vchan_setup,
413 cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
414 struct rte_pci_device *pci_dev)
416 struct cnxk_dpi_vf_s *dpivf = NULL;
417 char name[RTE_DEV_NAME_MAX_LEN];
418 struct rte_dma_dev *dmadev;
419 struct roc_dpi *rdpi = NULL;
422 if (!pci_dev->mem_resource[0].addr)
427 plt_err("Failed to initialize platform model, rc=%d", rc);
430 memset(name, 0, sizeof(name));
431 rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
433 dmadev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
435 if (dmadev == NULL) {
436 plt_err("dma device allocation failed for %s", name);
440 dpivf = dmadev->data->dev_private;
442 dmadev->device = &pci_dev->device;
443 dmadev->fp_obj->dev_private = dpivf;
444 dmadev->dev_ops = &cnxk_dmadev_ops;
446 dmadev->fp_obj->copy = cnxk_dmadev_copy;
447 dmadev->fp_obj->copy_sg = cnxk_dmadev_copy_sg;
448 dmadev->fp_obj->submit = cnxk_dmadev_submit;
449 dmadev->fp_obj->completed = cnxk_dmadev_completed;
450 dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
454 rdpi->pci_dev = pci_dev;
455 rc = roc_dpi_dev_init(rdpi);
463 rte_dma_pmd_release(name);
469 cnxk_dmadev_remove(struct rte_pci_device *pci_dev)
471 char name[RTE_DEV_NAME_MAX_LEN];
473 memset(name, 0, sizeof(name));
474 rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
476 return rte_dma_pmd_release(name);
479 static const struct rte_pci_id cnxk_dma_pci_map[] = {
481 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
482 PCI_DEVID_CNXK_DPI_VF)
489 static struct rte_pci_driver cnxk_dmadev = {
490 .id_table = cnxk_dma_pci_map,
491 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
492 .probe = cnxk_dmadev_probe,
493 .remove = cnxk_dmadev_remove,
496 RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev);
497 RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map);
498 RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci");