drivers/dma/dpaa/dpaa_qdma.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 NXP
   3  */
   4
   5 #ifndef _DPAA_QDMA_H_
   6 #define _DPAA_QDMA_H_
   7
   8 #include <rte_io.h>
   9
  10 #ifndef BIT
  11 #define BIT(nr)         (1UL << (nr))
  12 #endif
  13
  14 #define CORE_NUMBER 4
  15 #define RETRIES 5
  16
  17 #ifndef GENMASK
  18 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  19 #define GENMASK(h, l) \
  20                 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
  21 #endif
  22
  23 #define FSL_QDMA_DMR                    0x0
  24 #define FSL_QDMA_DSR                    0x4
  25 #define FSL_QDMA_DEDR                   0xe04
  26 #define FSL_QDMA_DECFDW0R               0xe10
  27 #define FSL_QDMA_DECFDW1R               0xe14
  28 #define FSL_QDMA_DECFDW2R               0xe18
  29 #define FSL_QDMA_DECFDW3R               0xe1c
  30 #define FSL_QDMA_DECFQIDR               0xe30
  31 #define FSL_QDMA_DECBR                  0xe34
  32
  33 #define FSL_QDMA_BCQMR(x)               (0xc0 + 0x100 * (x))
  34 #define FSL_QDMA_BCQSR(x)               (0xc4 + 0x100 * (x))
  35 #define FSL_QDMA_BCQEDPA_SADDR(x)       (0xc8 + 0x100 * (x))
  36 #define FSL_QDMA_BCQDPA_SADDR(x)        (0xcc + 0x100 * (x))
  37 #define FSL_QDMA_BCQEEPA_SADDR(x)       (0xd0 + 0x100 * (x))
  38 #define FSL_QDMA_BCQEPA_SADDR(x)        (0xd4 + 0x100 * (x))
  39 #define FSL_QDMA_BCQIER(x)              (0xe0 + 0x100 * (x))
  40 #define FSL_QDMA_BCQIDR(x)              (0xe4 + 0x100 * (x))
  41
  42 #define FSL_QDMA_SQEDPAR                0x808
  43 #define FSL_QDMA_SQDPAR                 0x80c
  44 #define FSL_QDMA_SQEEPAR                0x810
  45 #define FSL_QDMA_SQEPAR                 0x814
  46 #define FSL_QDMA_BSQMR                  0x800
  47 #define FSL_QDMA_BSQSR                  0x804
  48 #define FSL_QDMA_BSQICR                 0x828
  49 #define FSL_QDMA_CQIER                  0xa10
  50 #define FSL_QDMA_SQCCMR                 0xa20
  51
  52 #define FSL_QDMA_SQCCMR_ENTER_WM        0x200000
  53
  54 #define FSL_QDMA_QUEUE_MAX              8
  55
  56 #define FSL_QDMA_BCQMR_EN               0x80000000
  57 #define FSL_QDMA_BCQMR_EI_BE            0x40
  58 #define FSL_QDMA_BCQMR_CD_THLD(x)       ((x) << 20)
  59 #define FSL_QDMA_BCQMR_CQ_SIZE(x)       ((x) << 16)
  60
  61 #define FSL_QDMA_BCQSR_QF_XOFF_BE       0x1000100
  62
  63 #define FSL_QDMA_BSQMR_EN               0x80000000
  64 #define FSL_QDMA_BSQMR_DI_BE            0x40
  65 #define FSL_QDMA_BSQMR_CQ_SIZE(x)       ((x) << 16)
  66
  67 #define FSL_QDMA_BSQSR_QE_BE            0x200
  68
  69 #define FSL_QDMA_DMR_DQD                0x40000000
  70 #define FSL_QDMA_DSR_DB                 0x80000000
  71
  72 #define FSL_QDMA_COMMAND_BUFFER_SIZE    64
  73 #define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
  74 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
  75 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
  76 #define FSL_QDMA_QUEUE_NUM_MAX          8
  77
  78 #define FSL_QDMA_CMD_RWTTYPE            0x4
  79 #define FSL_QDMA_CMD_LWC                0x2
  80
  81 #define FSL_QDMA_CMD_RWTTYPE_OFFSET     28
  82 #define FSL_QDMA_CMD_LWC_OFFSET         16
  83
  84 #define QDMA_CCDF_STATUS                20
  85 #define QDMA_CCDF_OFFSET                20
  86 #define QDMA_CCDF_MASK                  GENMASK(28, 20)
  87 #define QDMA_CCDF_FOTMAT                BIT(29)
  88 #define QDMA_CCDF_SER                   BIT(30)
  89
  90 #define QDMA_SG_FIN                     BIT(30)
  91 #define QDMA_SG_LEN_MASK                GENMASK(29, 0)
  92
  93 #define COMMAND_QUEUE_OVERFLOW          10
  94
  95 /* qdma engine attribute */
  96 #define QDMA_QUEUE_SIZE                 64
  97 #define QDMA_STATUS_SIZE                64
  98 #define QDMA_CCSR_BASE                  0x8380000
  99 #define VIRT_CHANNELS                   32
 100 #define QDMA_BLOCK_OFFSET               0x10000
 101 #define QDMA_BLOCKS                     4
 102 #define QDMA_QUEUES                     8
 103 #define QDMA_DELAY                      1000
 104
 105 #define QDMA_BIG_ENDIAN                 1
 106 #ifdef QDMA_BIG_ENDIAN
 107 #define QDMA_IN(addr)           be32_to_cpu(rte_read32(addr))
 108 #define QDMA_OUT(addr, val)     rte_write32(be32_to_cpu(val), addr)
 109 #define QDMA_IN_BE(addr)        rte_read32(addr)
 110 #define QDMA_OUT_BE(addr, val)  rte_write32(val, addr)
 111 #else
 112 #define QDMA_IN(addr)           rte_read32(addr)
 113 #define QDMA_OUT(addr, val)     rte_write32(val, addr)
 114 #define QDMA_IN_BE(addr)        be32_to_cpu(rte_write32(addr))
 115 #define QDMA_OUT_BE(addr, val)  rte_write32(be32_to_cpu(val), addr)
 116 #endif
 117
 118 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x)                  \
 119         (((fsl_qdma_engine)->block_offset) * (x))
 120
 121 typedef void (*dma_call_back)(void *params);
 122
 123 /* qDMA Command Descriptor Formats */
 124 struct fsl_qdma_format {
 125         __le32 status; /* ser, status */
 126         __le32 cfg;     /* format, offset */
 127         union {
 128                 struct {
 129                         __le32 addr_lo; /* low 32-bits of 40-bit address */
 130                         u8 addr_hi;     /* high 8-bits of 40-bit address */
 131                         u8 __reserved1[2];
 132                         u8 cfg8b_w1; /* dd, queue */
 133                 };
 134                 __le64 data;
 135         };
 136 };
 137
 138 /* qDMA Source Descriptor Format */
 139 struct fsl_qdma_sdf {
 140         __le32 rev3;
 141         __le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */
 142         __le32 rev5;
 143         __le32 cmd;
 144 };
 145
 146 /* qDMA Destination Descriptor Format */
 147 struct fsl_qdma_ddf {
 148         __le32 rev1;
 149         __le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */
 150         __le32 rev3;
 151         __le32 cmd;
 152 };
 153
 154 struct fsl_qdma_chan {
 155         struct fsl_qdma_engine  *qdma;
 156         struct fsl_qdma_queue   *queue;
 157         bool                    free;
 158         struct list_head        list;
 159 };
 160
 161 struct fsl_qdma_queue {
 162         struct fsl_qdma_format  *virt_head;
 163         struct list_head        comp_used;
 164         struct list_head        comp_free;
 165         dma_addr_t              bus_addr;
 166         u32                     n_cq;
 167         u32                     id;
 168         u32                     count;
 169         u32                     pending;
 170         struct fsl_qdma_format  *cq;
 171         void                    *block_base;
 172         struct rte_dma_stats    stats;
 173 };
 174
 175 struct fsl_qdma_comp {
 176         dma_addr_t              bus_addr;
 177         dma_addr_t              desc_bus_addr;
 178         void                    *virt_addr;
 179         int                     index;
 180         void                    *desc_virt_addr;
 181         struct fsl_qdma_chan    *qchan;
 182         dma_call_back           call_back_func;
 183         void                    *params;
 184         struct list_head        list;
 185 };
 186
 187 struct fsl_qdma_engine {
 188         int                     desc_allocated;
 189         void                    *ctrl_base;
 190         void                    *status_base;
 191         void                    *block_base;
 192         u32                     n_chans;
 193         u32                     n_queues;
 194         int                     error_irq;
 195         struct fsl_qdma_queue   *queue;
 196         struct fsl_qdma_queue   **status;
 197         struct fsl_qdma_chan    *chans;
 198         u32                     num_blocks;
 199         u8                      free_block_id;
 200         u32                     vchan_map[4];
 201         int                     block_offset;
 202 };
 203
 204 static rte_atomic32_t wait_task[CORE_NUMBER];
 205
 206 #endif /* _DPAA_QDMA_H_ */