1 /* SPDX-License-Identifier: BSD-3-Clause
11 #define BIT(nr) (1UL << (nr))
18 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
19 #define GENMASK(h, l) \
20 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
23 #define FSL_QDMA_DMR 0x0
24 #define FSL_QDMA_DSR 0x4
25 #define FSL_QDMA_DEDR 0xe04
26 #define FSL_QDMA_DECFDW0R 0xe10
27 #define FSL_QDMA_DECFDW1R 0xe14
28 #define FSL_QDMA_DECFDW2R 0xe18
29 #define FSL_QDMA_DECFDW3R 0xe1c
30 #define FSL_QDMA_DECFQIDR 0xe30
31 #define FSL_QDMA_DECBR 0xe34
33 #define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
34 #define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x))
35 #define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
36 #define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
37 #define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
38 #define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
39 #define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
40 #define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
42 #define FSL_QDMA_SQEDPAR 0x808
43 #define FSL_QDMA_SQDPAR 0x80c
44 #define FSL_QDMA_SQEEPAR 0x810
45 #define FSL_QDMA_SQEPAR 0x814
46 #define FSL_QDMA_BSQMR 0x800
47 #define FSL_QDMA_BSQSR 0x804
48 #define FSL_QDMA_BSQICR 0x828
49 #define FSL_QDMA_CQIER 0xa10
50 #define FSL_QDMA_SQCCMR 0xa20
52 #define FSL_QDMA_SQCCMR_ENTER_WM 0x200000
54 #define FSL_QDMA_QUEUE_MAX 8
56 #define FSL_QDMA_BCQMR_EN 0x80000000
57 #define FSL_QDMA_BCQMR_EI_BE 0x40
58 #define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
59 #define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
61 #define FSL_QDMA_BCQSR_QF_XOFF_BE 0x1000100
63 #define FSL_QDMA_BSQMR_EN 0x80000000
64 #define FSL_QDMA_BSQMR_DI_BE 0x40
65 #define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
67 #define FSL_QDMA_BSQSR_QE_BE 0x200
69 #define FSL_QDMA_DMR_DQD 0x40000000
70 #define FSL_QDMA_DSR_DB 0x80000000
72 #define FSL_QDMA_COMMAND_BUFFER_SIZE 64
73 #define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
74 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
75 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
76 #define FSL_QDMA_QUEUE_NUM_MAX 8
78 #define FSL_QDMA_CMD_RWTTYPE 0x4
79 #define FSL_QDMA_CMD_LWC 0x2
81 #define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
82 #define FSL_QDMA_CMD_LWC_OFFSET 16
84 #define QDMA_CCDF_STATUS 20
85 #define QDMA_CCDF_OFFSET 20
86 #define QDMA_CCDF_MASK GENMASK(28, 20)
87 #define QDMA_CCDF_FOTMAT BIT(29)
88 #define QDMA_CCDF_SER BIT(30)
90 #define QDMA_SG_FIN BIT(30)
91 #define QDMA_SG_LEN_MASK GENMASK(29, 0)
93 #define COMMAND_QUEUE_OVERFLOW 10
95 /* qdma engine attribute */
96 #define QDMA_QUEUE_SIZE 64
97 #define QDMA_STATUS_SIZE 64
98 #define QDMA_CCSR_BASE 0x8380000
99 #define VIRT_CHANNELS 32
100 #define QDMA_BLOCK_OFFSET 0x10000
101 #define QDMA_BLOCKS 4
102 #define QDMA_QUEUES 8
103 #define QDMA_DELAY 1000
105 #define QDMA_BIG_ENDIAN 1
106 #ifdef QDMA_BIG_ENDIAN
107 #define QDMA_IN(addr) be32_to_cpu(rte_read32(addr))
108 #define QDMA_OUT(addr, val) rte_write32(be32_to_cpu(val), addr)
109 #define QDMA_IN_BE(addr) rte_read32(addr)
110 #define QDMA_OUT_BE(addr, val) rte_write32(val, addr)
112 #define QDMA_IN(addr) rte_read32(addr)
113 #define QDMA_OUT(addr, val) rte_write32(val, addr)
114 #define QDMA_IN_BE(addr) be32_to_cpu(rte_write32(addr))
115 #define QDMA_OUT_BE(addr, val) rte_write32(be32_to_cpu(val), addr)
118 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
119 (((fsl_qdma_engine)->block_offset) * (x))
121 typedef void (*dma_call_back)(void *params);
123 /* qDMA Command Descriptor Formats */
124 struct fsl_qdma_format {
125 __le32 status; /* ser, status */
126 __le32 cfg; /* format, offset */
129 __le32 addr_lo; /* low 32-bits of 40-bit address */
130 u8 addr_hi; /* high 8-bits of 40-bit address */
132 u8 cfg8b_w1; /* dd, queue */
138 /* qDMA Source Descriptor Format */
139 struct fsl_qdma_sdf {
141 __le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */
146 /* qDMA Destination Descriptor Format */
147 struct fsl_qdma_ddf {
149 __le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */
154 struct fsl_qdma_chan {
155 struct fsl_qdma_engine *qdma;
156 struct fsl_qdma_queue *queue;
158 struct list_head list;
161 struct fsl_qdma_queue {
162 struct fsl_qdma_format *virt_head;
163 struct list_head comp_used;
164 struct list_head comp_free;
170 struct fsl_qdma_format *cq;
172 struct rte_dma_stats stats;
175 struct fsl_qdma_comp {
177 dma_addr_t desc_bus_addr;
180 void *desc_virt_addr;
181 struct fsl_qdma_chan *qchan;
182 dma_call_back call_back_func;
184 struct list_head list;
187 struct fsl_qdma_engine {
195 struct fsl_qdma_queue *queue;
196 struct fsl_qdma_queue **status;
197 struct fsl_qdma_chan *chans;
204 static rte_atomic32_t wait_task[CORE_NUMBER];
206 #endif /* _DPAA_QDMA_H_ */