1 /* SPDX-License-Identifier: BSD-3-Clause
14 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
15 #define GENMASK(h, l) \
16 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
19 #define FSL_QDMA_DMR 0x0
20 #define FSL_QDMA_DSR 0x4
22 #define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
23 #define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
24 #define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
25 #define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
26 #define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
27 #define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
28 #define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
30 #define FSL_QDMA_SQEDPAR 0x808
31 #define FSL_QDMA_SQDPAR 0x80c
32 #define FSL_QDMA_SQEEPAR 0x810
33 #define FSL_QDMA_SQEPAR 0x814
34 #define FSL_QDMA_BSQMR 0x800
35 #define FSL_QDMA_BSQICR 0x828
36 #define FSL_QDMA_CQIER 0xa10
37 #define FSL_QDMA_SQCCMR 0xa20
39 #define FSL_QDMA_SQCCMR_ENTER_WM 0x200000
41 #define FSL_QDMA_QUEUE_MAX 8
43 #define FSL_QDMA_BCQMR_EN 0x80000000
44 #define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
45 #define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
47 #define FSL_QDMA_BSQMR_EN 0x80000000
48 #define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
50 #define FSL_QDMA_DMR_DQD 0x40000000
51 #define FSL_QDMA_DSR_DB 0x80000000
53 #define FSL_QDMA_COMMAND_BUFFER_SIZE 64
54 #define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
55 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
56 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
57 #define FSL_QDMA_QUEUE_NUM_MAX 8
59 #define FSL_QDMA_CMD_RWTTYPE 0x4
60 #define FSL_QDMA_CMD_LWC 0x2
62 #define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
63 #define FSL_QDMA_CMD_LWC_OFFSET 16
65 #define QDMA_SG_LEN_MASK GENMASK(29, 0)
67 #define COMMAND_QUEUE_OVERFLOW 10
69 /* qdma engine attribute */
70 #define QDMA_QUEUE_SIZE 64
71 #define QDMA_STATUS_SIZE 64
72 #define QDMA_CCSR_BASE 0x8380000
73 #define VIRT_CHANNELS 32
74 #define QDMA_BLOCK_OFFSET 0x10000
77 #define QDMA_DELAY 1000
79 #define QDMA_BIG_ENDIAN 1
80 #ifdef QDMA_BIG_ENDIAN
81 #define QDMA_IN(addr) be32_to_cpu(rte_read32(addr))
82 #define QDMA_OUT(addr, val) rte_write32(be32_to_cpu(val), addr)
84 #define QDMA_IN(addr) rte_read32(addr)
85 #define QDMA_OUT(addr, val) rte_write32(val, addr)
88 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
89 (((fsl_qdma_engine)->block_offset) * (x))
91 typedef void (*dma_call_back)(void *params);
93 /* qDMA Command Descriptor Formats */
94 struct fsl_qdma_format {
95 __le32 status; /* ser, status */
96 __le32 cfg; /* format, offset */
99 __le32 addr_lo; /* low 32-bits of 40-bit address */
100 u8 addr_hi; /* high 8-bits of 40-bit address */
102 u8 cfg8b_w1; /* dd, queue */
108 /* qDMA Source Descriptor Format */
109 struct fsl_qdma_sdf {
111 __le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */
116 /* qDMA Destination Descriptor Format */
117 struct fsl_qdma_ddf {
119 __le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */
124 struct fsl_qdma_chan {
125 struct fsl_qdma_engine *qdma;
126 struct fsl_qdma_queue *queue;
128 struct list_head list;
131 struct fsl_qdma_queue {
132 struct fsl_qdma_format *virt_head;
133 struct list_head comp_used;
134 struct list_head comp_free;
140 struct fsl_qdma_format *cq;
144 struct fsl_qdma_comp {
146 dma_addr_t desc_bus_addr;
149 void *desc_virt_addr;
150 struct fsl_qdma_chan *qchan;
151 dma_call_back call_back_func;
153 struct list_head list;
156 struct fsl_qdma_engine {
164 struct fsl_qdma_queue *queue;
165 struct fsl_qdma_queue **status;
166 struct fsl_qdma_chan *chans;
173 static rte_atomic32_t wait_task[CORE_NUMBER];
175 #endif /* _DPAA_QDMA_H_ */