drivers/dma/dpaa/dpaa_qdma.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 NXP
   3  */
   4
   5 #ifndef _DPAA_QDMA_H_
   6 #define _DPAA_QDMA_H_
   7
   8 #include <rte_io.h>
   9
  10 #define CORE_NUMBER 4
  11 #define RETRIES 5
  12
  13 #ifndef GENMASK
  14 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  15 #define GENMASK(h, l) \
  16                 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
  17 #endif
  18
  19 #define FSL_QDMA_DMR                    0x0
  20 #define FSL_QDMA_DSR                    0x4
  21
  22 #define FSL_QDMA_BCQMR(x)               (0xc0 + 0x100 * (x))
  23 #define FSL_QDMA_BCQEDPA_SADDR(x)       (0xc8 + 0x100 * (x))
  24 #define FSL_QDMA_BCQDPA_SADDR(x)        (0xcc + 0x100 * (x))
  25 #define FSL_QDMA_BCQEEPA_SADDR(x)       (0xd0 + 0x100 * (x))
  26 #define FSL_QDMA_BCQEPA_SADDR(x)        (0xd4 + 0x100 * (x))
  27 #define FSL_QDMA_BCQIER(x)              (0xe0 + 0x100 * (x))
  28 #define FSL_QDMA_BCQIDR(x)              (0xe4 + 0x100 * (x))
  29
  30 #define FSL_QDMA_SQEDPAR                0x808
  31 #define FSL_QDMA_SQDPAR                 0x80c
  32 #define FSL_QDMA_SQEEPAR                0x810
  33 #define FSL_QDMA_SQEPAR                 0x814
  34 #define FSL_QDMA_BSQMR                  0x800
  35 #define FSL_QDMA_BSQICR                 0x828
  36 #define FSL_QDMA_CQIER                  0xa10
  37 #define FSL_QDMA_SQCCMR                 0xa20
  38
  39 #define FSL_QDMA_SQCCMR_ENTER_WM        0x200000
  40
  41 #define FSL_QDMA_QUEUE_MAX              8
  42
  43 #define FSL_QDMA_BCQMR_EN               0x80000000
  44 #define FSL_QDMA_BCQMR_CD_THLD(x)       ((x) << 20)
  45 #define FSL_QDMA_BCQMR_CQ_SIZE(x)       ((x) << 16)
  46
  47 #define FSL_QDMA_BSQMR_EN               0x80000000
  48 #define FSL_QDMA_BSQMR_CQ_SIZE(x)       ((x) << 16)
  49
  50 #define FSL_QDMA_DMR_DQD                0x40000000
  51 #define FSL_QDMA_DSR_DB                 0x80000000
  52
  53 #define FSL_QDMA_COMMAND_BUFFER_SIZE    64
  54 #define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
  55 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
  56 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
  57 #define FSL_QDMA_QUEUE_NUM_MAX          8
  58
  59 #define FSL_QDMA_CMD_RWTTYPE            0x4
  60 #define FSL_QDMA_CMD_LWC                0x2
  61
  62 #define FSL_QDMA_CMD_RWTTYPE_OFFSET     28
  63 #define FSL_QDMA_CMD_LWC_OFFSET         16
  64
  65 #define QDMA_SG_LEN_MASK                GENMASK(29, 0)
  66
  67 #define COMMAND_QUEUE_OVERFLOW          10
  68
  69 /* qdma engine attribute */
  70 #define QDMA_QUEUE_SIZE                 64
  71 #define QDMA_STATUS_SIZE                64
  72 #define QDMA_CCSR_BASE                  0x8380000
  73 #define VIRT_CHANNELS                   32
  74 #define QDMA_BLOCK_OFFSET               0x10000
  75 #define QDMA_BLOCKS                     4
  76 #define QDMA_QUEUES                     8
  77 #define QDMA_DELAY                      1000
  78
  79 #define QDMA_BIG_ENDIAN                 1
  80 #ifdef QDMA_BIG_ENDIAN
  81 #define QDMA_IN(addr)           be32_to_cpu(rte_read32(addr))
  82 #define QDMA_OUT(addr, val)     rte_write32(be32_to_cpu(val), addr)
  83 #else
  84 #define QDMA_IN(addr)           rte_read32(addr)
  85 #define QDMA_OUT(addr, val)     rte_write32(val, addr)
  86 #endif
  87
  88 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x)                  \
  89         (((fsl_qdma_engine)->block_offset) * (x))
  90
  91 typedef void (*dma_call_back)(void *params);
  92
  93 /* qDMA Command Descriptor Formats */
  94 struct fsl_qdma_format {
  95         __le32 status; /* ser, status */
  96         __le32 cfg;     /* format, offset */
  97         union {
  98                 struct {
  99                         __le32 addr_lo; /* low 32-bits of 40-bit address */
 100                         u8 addr_hi;     /* high 8-bits of 40-bit address */
 101                         u8 __reserved1[2];
 102                         u8 cfg8b_w1; /* dd, queue */
 103                 };
 104                 __le64 data;
 105         };
 106 };
 107
 108 /* qDMA Source Descriptor Format */
 109 struct fsl_qdma_sdf {
 110         __le32 rev3;
 111         __le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */
 112         __le32 rev5;
 113         __le32 cmd;
 114 };
 115
 116 /* qDMA Destination Descriptor Format */
 117 struct fsl_qdma_ddf {
 118         __le32 rev1;
 119         __le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */
 120         __le32 rev3;
 121         __le32 cmd;
 122 };
 123
 124 struct fsl_qdma_chan {
 125         struct fsl_qdma_engine  *qdma;
 126         struct fsl_qdma_queue   *queue;
 127         bool                    free;
 128         struct list_head        list;
 129 };
 130
 131 struct fsl_qdma_queue {
 132         struct fsl_qdma_format  *virt_head;
 133         struct list_head        comp_used;
 134         struct list_head        comp_free;
 135         dma_addr_t              bus_addr;
 136         u32                     n_cq;
 137         u32                     id;
 138         u32                     count;
 139         u32                     pending;
 140         struct fsl_qdma_format  *cq;
 141         void                    *block_base;
 142 };
 143
 144 struct fsl_qdma_comp {
 145         dma_addr_t              bus_addr;
 146         dma_addr_t              desc_bus_addr;
 147         void                    *virt_addr;
 148         int                     index;
 149         void                    *desc_virt_addr;
 150         struct fsl_qdma_chan    *qchan;
 151         dma_call_back           call_back_func;
 152         void                    *params;
 153         struct list_head        list;
 154 };
 155
 156 struct fsl_qdma_engine {
 157         int                     desc_allocated;
 158         void                    *ctrl_base;
 159         void                    *status_base;
 160         void                    *block_base;
 161         u32                     n_chans;
 162         u32                     n_queues;
 163         int                     error_irq;
 164         struct fsl_qdma_queue   *queue;
 165         struct fsl_qdma_queue   **status;
 166         struct fsl_qdma_chan    *chans;
 167         u32                     num_blocks;
 168         u8                      free_block_id;
 169         u32                     vchan_map[4];
 170         int                     block_offset;
 171 };
 172
 173 static rte_atomic32_t wait_task[CORE_NUMBER];
 174
 175 #endif /* _DPAA_QDMA_H_ */