drivers/dma/dpaa/dpaa_qdma.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 NXP
   3  */
   4
   5 #ifndef _DPAA_QDMA_H_
   6 #define _DPAA_QDMA_H_
   7
   8 #include <rte_io.h>
   9
  10 #define CORE_NUMBER 4
  11 #define RETRIES 5
  12
  13 #define FSL_QDMA_DMR                    0x0
  14 #define FSL_QDMA_DSR                    0x4
  15
  16 #define FSL_QDMA_BCQMR(x)               (0xc0 + 0x100 * (x))
  17 #define FSL_QDMA_BCQEDPA_SADDR(x)       (0xc8 + 0x100 * (x))
  18 #define FSL_QDMA_BCQDPA_SADDR(x)        (0xcc + 0x100 * (x))
  19 #define FSL_QDMA_BCQEEPA_SADDR(x)       (0xd0 + 0x100 * (x))
  20 #define FSL_QDMA_BCQEPA_SADDR(x)        (0xd4 + 0x100 * (x))
  21 #define FSL_QDMA_BCQIER(x)              (0xe0 + 0x100 * (x))
  22 #define FSL_QDMA_BCQIDR(x)              (0xe4 + 0x100 * (x))
  23
  24 #define FSL_QDMA_SQEDPAR                0x808
  25 #define FSL_QDMA_SQDPAR                 0x80c
  26 #define FSL_QDMA_SQEEPAR                0x810
  27 #define FSL_QDMA_SQEPAR                 0x814
  28 #define FSL_QDMA_BSQMR                  0x800
  29 #define FSL_QDMA_BSQICR                 0x828
  30 #define FSL_QDMA_CQIER                  0xa10
  31 #define FSL_QDMA_SQCCMR                 0xa20
  32
  33 #define FSL_QDMA_SQCCMR_ENTER_WM        0x200000
  34
  35 #define FSL_QDMA_QUEUE_MAX              8
  36
  37 #define FSL_QDMA_BCQMR_EN               0x80000000
  38 #define FSL_QDMA_BCQMR_CD_THLD(x)       ((x) << 20)
  39 #define FSL_QDMA_BCQMR_CQ_SIZE(x)       ((x) << 16)
  40
  41 #define FSL_QDMA_BSQMR_EN               0x80000000
  42 #define FSL_QDMA_BSQMR_CQ_SIZE(x)       ((x) << 16)
  43
  44 #define FSL_QDMA_DMR_DQD                0x40000000
  45 #define FSL_QDMA_DSR_DB                 0x80000000
  46
  47 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
  48 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
  49 #define FSL_QDMA_QUEUE_NUM_MAX          8
  50
  51 /* qdma engine attribute */
  52 #define QDMA_QUEUE_SIZE                 64
  53 #define QDMA_STATUS_SIZE                64
  54 #define QDMA_CCSR_BASE                  0x8380000
  55 #define VIRT_CHANNELS                   32
  56 #define QDMA_BLOCK_OFFSET               0x10000
  57 #define QDMA_BLOCKS                     4
  58 #define QDMA_QUEUES                     8
  59 #define QDMA_DELAY                      1000
  60
  61 #define QDMA_BIG_ENDIAN                 1
  62 #ifdef QDMA_BIG_ENDIAN
  63 #define QDMA_IN(addr)           be32_to_cpu(rte_read32(addr))
  64 #define QDMA_OUT(addr, val)     rte_write32(be32_to_cpu(val), addr)
  65 #else
  66 #define QDMA_IN(addr)           rte_read32(addr)
  67 #define QDMA_OUT(addr, val)     rte_write32(val, addr)
  68 #endif
  69
  70 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x)                  \
  71         (((fsl_qdma_engine)->block_offset) * (x))
  72
  73 typedef void (*dma_call_back)(void *params);
  74
  75 /* qDMA Command Descriptor Formats */
  76 struct fsl_qdma_format {
  77         __le32 status; /* ser, status */
  78         __le32 cfg;     /* format, offset */
  79         union {
  80                 struct {
  81                         __le32 addr_lo; /* low 32-bits of 40-bit address */
  82                         u8 addr_hi;     /* high 8-bits of 40-bit address */
  83                         u8 __reserved1[2];
  84                         u8 cfg8b_w1; /* dd, queue */
  85                 };
  86                 __le64 data;
  87         };
  88 };
  89
  90 struct fsl_qdma_chan {
  91         struct fsl_qdma_engine  *qdma;
  92         struct fsl_qdma_queue   *queue;
  93         bool                    free;
  94         struct list_head        list;
  95 };
  96
  97 struct fsl_qdma_queue {
  98         struct fsl_qdma_format  *virt_head;
  99         struct list_head        comp_used;
 100         struct list_head        comp_free;
 101         dma_addr_t              bus_addr;
 102         u32                     n_cq;
 103         u32                     id;
 104         u32                     count;
 105         u32                     pending;
 106         struct fsl_qdma_format  *cq;
 107         void                    *block_base;
 108 };
 109
 110 struct fsl_qdma_comp {
 111         dma_addr_t              bus_addr;
 112         dma_addr_t              desc_bus_addr;
 113         void                    *virt_addr;
 114         int                     index;
 115         void                    *desc_virt_addr;
 116         struct fsl_qdma_chan    *qchan;
 117         dma_call_back           call_back_func;
 118         void                    *params;
 119         struct list_head        list;
 120 };
 121
 122 struct fsl_qdma_engine {
 123         int                     desc_allocated;
 124         void                    *ctrl_base;
 125         void                    *status_base;
 126         void                    *block_base;
 127         u32                     n_chans;
 128         u32                     n_queues;
 129         int                     error_irq;
 130         struct fsl_qdma_queue   *queue;
 131         struct fsl_qdma_queue   **status;
 132         struct fsl_qdma_chan    *chans;
 133         u32                     num_blocks;
 134         u8                      free_block_id;
 135         u32                     vchan_map[4];
 136         int                     block_offset;
 137 };
 138
 139 static rte_atomic32_t wait_task[CORE_NUMBER];
 140
 141 #endif /* _DPAA_QDMA_H_ */