1 /* SPDX-License-Identifier: BSD-3-Clause
13 #define FSL_QDMA_DMR 0x0
14 #define FSL_QDMA_DSR 0x4
16 #define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
17 #define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
18 #define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
19 #define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
20 #define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
21 #define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
22 #define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
24 #define FSL_QDMA_SQEDPAR 0x808
25 #define FSL_QDMA_SQDPAR 0x80c
26 #define FSL_QDMA_SQEEPAR 0x810
27 #define FSL_QDMA_SQEPAR 0x814
28 #define FSL_QDMA_BSQMR 0x800
29 #define FSL_QDMA_BSQICR 0x828
30 #define FSL_QDMA_CQIER 0xa10
31 #define FSL_QDMA_SQCCMR 0xa20
33 #define FSL_QDMA_SQCCMR_ENTER_WM 0x200000
35 #define FSL_QDMA_QUEUE_MAX 8
37 #define FSL_QDMA_BCQMR_EN 0x80000000
38 #define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
39 #define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
41 #define FSL_QDMA_BSQMR_EN 0x80000000
42 #define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
44 #define FSL_QDMA_DMR_DQD 0x40000000
45 #define FSL_QDMA_DSR_DB 0x80000000
47 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
48 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
49 #define FSL_QDMA_QUEUE_NUM_MAX 8
51 /* qdma engine attribute */
52 #define QDMA_QUEUE_SIZE 64
53 #define QDMA_STATUS_SIZE 64
54 #define QDMA_CCSR_BASE 0x8380000
55 #define VIRT_CHANNELS 32
56 #define QDMA_BLOCK_OFFSET 0x10000
59 #define QDMA_DELAY 1000
61 #define QDMA_BIG_ENDIAN 1
62 #ifdef QDMA_BIG_ENDIAN
63 #define QDMA_IN(addr) be32_to_cpu(rte_read32(addr))
64 #define QDMA_OUT(addr, val) rte_write32(be32_to_cpu(val), addr)
66 #define QDMA_IN(addr) rte_read32(addr)
67 #define QDMA_OUT(addr, val) rte_write32(val, addr)
70 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
71 (((fsl_qdma_engine)->block_offset) * (x))
73 typedef void (*dma_call_back)(void *params);
75 /* qDMA Command Descriptor Formats */
76 struct fsl_qdma_format {
77 __le32 status; /* ser, status */
78 __le32 cfg; /* format, offset */
81 __le32 addr_lo; /* low 32-bits of 40-bit address */
82 u8 addr_hi; /* high 8-bits of 40-bit address */
84 u8 cfg8b_w1; /* dd, queue */
90 struct fsl_qdma_chan {
91 struct fsl_qdma_engine *qdma;
92 struct fsl_qdma_queue *queue;
94 struct list_head list;
97 struct fsl_qdma_queue {
98 struct fsl_qdma_format *virt_head;
99 struct list_head comp_used;
100 struct list_head comp_free;
106 struct fsl_qdma_format *cq;
110 struct fsl_qdma_comp {
112 dma_addr_t desc_bus_addr;
115 void *desc_virt_addr;
116 struct fsl_qdma_chan *qchan;
117 dma_call_back call_back_func;
119 struct list_head list;
122 struct fsl_qdma_engine {
130 struct fsl_qdma_queue *queue;
131 struct fsl_qdma_queue **status;
132 struct fsl_qdma_chan *chans;
139 static rte_atomic32_t wait_task[CORE_NUMBER];
141 #endif /* _DPAA_QDMA_H_ */