drivers/dma/hisilicon/hisi_dmadev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 HiSilicon Limited
   3  */
   4
   5 #include <inttypes.h>
   6 #include <string.h>
   7
   8 #include <rte_bus_pci.h>
   9 #include <rte_cycles.h>
  10 #include <rte_eal.h>
  11 #include <rte_io.h>
  12 #include <rte_log.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memzone.h>
  15 #include <rte_pci.h>
  16 #include <rte_dmadev_pmd.h>
  17
  18 #include "hisi_dmadev.h"
  19
  20 RTE_LOG_REGISTER_DEFAULT(hisi_dma_logtype, INFO);
  21 #define HISI_DMA_LOG(level, fmt, args...) \
  22                 rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
  23                 "%s(): " fmt "\n", __func__, ##args)
  24 #define HISI_DMA_LOG_RAW(hw, level, fmt, args...) \
  25                 rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
  26                 "%s %s(): " fmt "\n", (hw)->data->dev_name, \
  27                 __func__, ##args)
  28 #define HISI_DMA_DEBUG(hw, fmt, args...) \
  29                 HISI_DMA_LOG_RAW(hw, DEBUG, fmt, ## args)
  30 #define HISI_DMA_INFO(hw, fmt, args...) \
  31                 HISI_DMA_LOG_RAW(hw, INFO, fmt, ## args)
  32 #define HISI_DMA_WARN(hw, fmt, args...) \
  33                 HISI_DMA_LOG_RAW(hw, WARNING, fmt, ## args)
  34 #define HISI_DMA_ERR(hw, fmt, args...) \
  35                 HISI_DMA_LOG_RAW(hw, ERR, fmt, ## args)
  36
  37 static uint32_t
  38 hisi_dma_queue_base(struct hisi_dma_dev *hw)
  39 {
  40         if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)
  41                 return HISI_DMA_HIP08_QUEUE_BASE;
  42         else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
  43                 return HISI_DMA_HIP09_QUEUE_BASE;
  44         else
  45                 return 0;
  46 }
  47
  48 static volatile void *
  49 hisi_dma_queue_regaddr(struct hisi_dma_dev *hw, uint32_t qoff)
  50 {
  51         uint32_t off = hisi_dma_queue_base(hw) +
  52                         hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
  53         return (volatile void *)((char *)hw->io_base + off);
  54 }
  55
  56 static void
  57 hisi_dma_write_reg(void *base, uint32_t off, uint32_t val)
  58 {
  59         rte_write32(rte_cpu_to_le_32(val),
  60                     (volatile void *)((char *)base + off));
  61 }
  62
  63 static void
  64 hisi_dma_write_dev(struct hisi_dma_dev *hw, uint32_t off, uint32_t val)
  65 {
  66         hisi_dma_write_reg(hw->io_base, off, val);
  67 }
  68
  69 static void
  70 hisi_dma_write_queue(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t val)
  71 {
  72         uint32_t off = hisi_dma_queue_base(hw) +
  73                         hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
  74         hisi_dma_write_dev(hw, off, val);
  75 }
  76
  77 static uint32_t
  78 hisi_dma_read_reg(void *base, uint32_t off)
  79 {
  80         uint32_t val = rte_read32((volatile void *)((char *)base + off));
  81         return rte_le_to_cpu_32(val);
  82 }
  83
  84 static uint32_t
  85 hisi_dma_read_dev(struct hisi_dma_dev *hw, uint32_t off)
  86 {
  87         return hisi_dma_read_reg(hw->io_base, off);
  88 }
  89
  90 static uint32_t
  91 hisi_dma_read_queue(struct hisi_dma_dev *hw, uint32_t qoff)
  92 {
  93         uint32_t off = hisi_dma_queue_base(hw) +
  94                         hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
  95         return hisi_dma_read_dev(hw, off);
  96 }
  97
  98 static void
  99 hisi_dma_update_bit(struct hisi_dma_dev *hw, uint32_t off, uint32_t pos,
 100                     bool set)
 101 {
 102         uint32_t tmp = hisi_dma_read_dev(hw, off);
 103         uint32_t mask = 1u << pos;
 104         tmp = set ? tmp | mask : tmp & ~mask;
 105         hisi_dma_write_dev(hw, off, tmp);
 106 }
 107
 108 static void
 109 hisi_dma_update_queue_bit(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t pos,
 110                           bool set)
 111 {
 112         uint32_t tmp = hisi_dma_read_queue(hw, qoff);
 113         uint32_t mask = 1u << pos;
 114         tmp = set ? tmp | mask : tmp & ~mask;
 115         hisi_dma_write_queue(hw, qoff, tmp);
 116 }
 117
 118 static void
 119 hisi_dma_update_queue_mbit(struct hisi_dma_dev *hw, uint32_t qoff,
 120                            uint32_t mask, bool set)
 121 {
 122         uint32_t tmp = hisi_dma_read_queue(hw, qoff);
 123         tmp = set ? tmp | mask : tmp & ~mask;
 124         hisi_dma_write_queue(hw, qoff, tmp);
 125 }
 126
 127 #define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) ({ \
 128         uint32_t timeout = 0; \
 129         while (timeout++ <= (timeout_us)) { \
 130                 (val) = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); \
 131                 if (cond) \
 132                         break; \
 133                 rte_delay_us(sleep_us); \
 134         } \
 135         (cond) ? 0 : -ETIME; \
 136 })
 137
 138 static int
 139 hisi_dma_reset_hw(struct hisi_dma_dev *hw)
 140 {
 141 #define POLL_SLEEP_US   100
 142 #define POLL_TIMEOUT_US 10000
 143
 144         uint32_t tmp;
 145         int ret;
 146
 147         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 148                                   HISI_DMA_QUEUE_CTRL0_PAUSE_B, true);
 149         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 150                                   HISI_DMA_QUEUE_CTRL0_EN_B, false);
 151
 152         ret = hisi_dma_poll_hw_state(hw, tmp,
 153                 FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) != HISI_DMA_STATE_RUN,
 154                 POLL_SLEEP_US, POLL_TIMEOUT_US);
 155         if (ret) {
 156                 HISI_DMA_ERR(hw, "disable dma timeout!");
 157                 return ret;
 158         }
 159
 160         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
 161                                   HISI_DMA_QUEUE_CTRL1_RESET_B, true);
 162         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
 163         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
 164         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 165                                   HISI_DMA_QUEUE_CTRL0_PAUSE_B, false);
 166
 167         ret = hisi_dma_poll_hw_state(hw, tmp,
 168                 FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) == HISI_DMA_STATE_IDLE,
 169                 POLL_SLEEP_US, POLL_TIMEOUT_US);
 170         if (ret) {
 171                 HISI_DMA_ERR(hw, "reset dma timeout!");
 172                 return ret;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static void
 179 hisi_dma_init_common(struct hisi_dma_dev *hw)
 180 {
 181         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_L_REG,
 182                              lower_32_bits(hw->sqe_iova));
 183         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_H_REG,
 184                              upper_32_bits(hw->sqe_iova));
 185         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_BASE_L_REG,
 186                              lower_32_bits(hw->cqe_iova));
 187         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_BASE_H_REG,
 188                              upper_32_bits(hw->cqe_iova));
 189         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_DEPTH_REG,
 190                              hw->sq_depth_mask);
 191         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_DEPTH_REG, hw->cq_depth - 1);
 192         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
 193         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
 194         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM0_REG, 0);
 195         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM1_REG, 0);
 196         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM2_REG, 0);
 197 }
 198
 199 static void
 200 hisi_dma_init_hw(struct hisi_dma_dev *hw)
 201 {
 202         hisi_dma_init_common(hw);
 203
 204         if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
 205                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG,
 206                                      0);
 207                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM4_REG,
 208                                      0);
 209                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM5_REG,
 210                                      0);
 211                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM6_REG,
 212                                      0);
 213                 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 214                                 HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B, false);
 215                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
 216                                 HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
 217                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
 218                                 HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
 219         } else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) {
 220                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 221                                 HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false);
 222                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
 223                                 HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
 224                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
 225                                 HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
 226                 hisi_dma_update_queue_mbit(hw,
 227                                 HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG,
 228                                 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
 229                 hisi_dma_update_queue_mbit(hw,
 230                                 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG,
 231                                 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
 232                 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
 233                                 HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true);
 234                 hisi_dma_update_bit(hw,
 235                                 HISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id),
 236                                 HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B,
 237                                 true);
 238         }
 239 }
 240
 241 static void
 242 hisi_dma_init_gbl(void *pci_bar, uint8_t revision)
 243 {
 244         struct hisi_dma_dev hw;
 245
 246         memset(&hw, 0, sizeof(hw));
 247         hw.io_base = pci_bar;
 248
 249         if (revision == HISI_DMA_REVISION_HIP08B)
 250                 hisi_dma_update_bit(&hw, HISI_DMA_HIP08_MODE_REG,
 251                                     HISI_DMA_HIP08_MODE_SEL_B, true);
 252 }
 253
 254 static uint8_t
 255 hisi_dma_reg_layout(uint8_t revision)
 256 {
 257         if (revision == HISI_DMA_REVISION_HIP08B)
 258                 return HISI_DMA_REG_LAYOUT_HIP08;
 259         else if (revision >= HISI_DMA_REVISION_HIP09A)
 260                 return HISI_DMA_REG_LAYOUT_HIP09;
 261         else
 262                 return HISI_DMA_REG_LAYOUT_INVALID;
 263 }
 264
 265 static void
 266 hisi_dma_zero_iomem(struct hisi_dma_dev *hw)
 267 {
 268         memset(hw->iomz->addr, 0, hw->iomz_sz);
 269 }
 270
 271 static int
 272 hisi_dma_alloc_iomem(struct hisi_dma_dev *hw, uint16_t ring_size,
 273                      const char *dev_name)
 274 {
 275         uint32_t sq_size = sizeof(struct hisi_dma_sqe) * ring_size;
 276         uint32_t cq_size = sizeof(struct hisi_dma_cqe) *
 277                            (ring_size + HISI_DMA_CQ_RESERVED);
 278         uint32_t status_size = sizeof(uint16_t) * ring_size;
 279         char mz_name[RTE_MEMZONE_NAMESIZE];
 280         const struct rte_memzone *iomz;
 281         uint32_t total_size;
 282
 283         sq_size = RTE_CACHE_LINE_ROUNDUP(sq_size);
 284         cq_size = RTE_CACHE_LINE_ROUNDUP(cq_size);
 285         status_size = RTE_CACHE_LINE_ROUNDUP(status_size);
 286         total_size = sq_size + cq_size + status_size;
 287
 288         (void)snprintf(mz_name, sizeof(mz_name), "hisi_dma:%s", dev_name);
 289         iomz = rte_memzone_reserve(mz_name, total_size, hw->data->numa_node,
 290                                    RTE_MEMZONE_IOVA_CONTIG);
 291         if (iomz == NULL) {
 292                 HISI_DMA_ERR(hw, "malloc %s iomem fail!", mz_name);
 293                 return -ENOMEM;
 294         }
 295
 296         hw->iomz = iomz;
 297         hw->iomz_sz = total_size;
 298         hw->sqe = iomz->addr;
 299         hw->cqe = (void *)((char *)iomz->addr + sq_size);
 300         hw->status = (void *)((char *)iomz->addr + sq_size + cq_size);
 301         hw->sqe_iova = iomz->iova;
 302         hw->cqe_iova = iomz->iova + sq_size;
 303         hw->sq_depth_mask = ring_size - 1;
 304         hw->cq_depth = ring_size + HISI_DMA_CQ_RESERVED;
 305         hisi_dma_zero_iomem(hw);
 306
 307         return 0;
 308 }
 309
 310 static void
 311 hisi_dma_free_iomem(struct hisi_dma_dev *hw)
 312 {
 313         if (hw->iomz != NULL)
 314                 rte_memzone_free(hw->iomz);
 315
 316         hw->iomz = NULL;
 317         hw->sqe = NULL;
 318         hw->cqe = NULL;
 319         hw->status = NULL;
 320         hw->sqe_iova = 0;
 321         hw->cqe_iova = 0;
 322         hw->sq_depth_mask = 0;
 323         hw->cq_depth = 0;
 324 }
 325
 326 static int
 327 hisi_dma_info_get(const struct rte_dma_dev *dev,
 328                   struct rte_dma_info *dev_info,
 329                   uint32_t info_sz)
 330 {
 331         struct hisi_dma_dev *hw = dev->data->dev_private;
 332         RTE_SET_USED(info_sz);
 333
 334         dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
 335                              RTE_DMA_CAPA_OPS_COPY;
 336         if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
 337                 dev_info->dev_capa |= RTE_DMA_CAPA_HANDLES_ERRORS;
 338
 339         dev_info->max_vchans = 1;
 340         dev_info->max_desc = HISI_DMA_MAX_DESC_NUM;
 341         dev_info->min_desc = HISI_DMA_MIN_DESC_NUM;
 342
 343         return 0;
 344 }
 345
 346 static int
 347 hisi_dma_configure(struct rte_dma_dev *dev,
 348                    const struct rte_dma_conf *conf,
 349                    uint32_t conf_sz)
 350 {
 351         RTE_SET_USED(dev);
 352         RTE_SET_USED(conf);
 353         RTE_SET_USED(conf_sz);
 354         return 0;
 355 }
 356
 357 static int
 358 hisi_dma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
 359                      const struct rte_dma_vchan_conf *conf,
 360                      uint32_t conf_sz)
 361 {
 362         struct hisi_dma_dev *hw = dev->data->dev_private;
 363         int ret;
 364
 365         RTE_SET_USED(vchan);
 366         RTE_SET_USED(conf_sz);
 367
 368         if (!rte_is_power_of_2(conf->nb_desc)) {
 369                 HISI_DMA_ERR(hw, "Number of desc must be power of 2!");
 370                 return -EINVAL;
 371         }
 372
 373         hisi_dma_free_iomem(hw);
 374         ret = hisi_dma_alloc_iomem(hw, conf->nb_desc, dev->data->dev_name);
 375         if (ret)
 376                 return ret;
 377
 378         return 0;
 379 }
 380
 381 static int
 382 hisi_dma_start(struct rte_dma_dev *dev)
 383 {
 384         struct hisi_dma_dev *hw = dev->data->dev_private;
 385
 386         if (hw->iomz == NULL) {
 387                 HISI_DMA_ERR(hw, "Vchan was not setup, start fail!\n");
 388                 return -EINVAL;
 389         }
 390
 391         /* Reset the dmadev to a known state, include:
 392          *   1) zero iomem, also include status fields.
 393          *   2) init hardware register.
 394          *   3) init index values to zero.
 395          *   4) init running statistics.
 396          */
 397         hisi_dma_zero_iomem(hw);
 398         hisi_dma_init_hw(hw);
 399         hw->ridx = 0;
 400         hw->cridx = 0;
 401         hw->sq_head = 0;
 402         hw->sq_tail = 0;
 403         hw->cq_sq_head = 0;
 404         hw->cq_head = 0;
 405         hw->cqs_completed = 0;
 406         hw->cqe_vld = 1;
 407         hw->submitted = 0;
 408         hw->completed = 0;
 409         hw->errors = 0;
 410
 411         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 412                                   HISI_DMA_QUEUE_CTRL0_EN_B, true);
 413
 414         return 0;
 415 }
 416
 417 static int
 418 hisi_dma_stop(struct rte_dma_dev *dev)
 419 {
 420         return hisi_dma_reset_hw(dev->data->dev_private);
 421 }
 422
 423 static int
 424 hisi_dma_close(struct rte_dma_dev *dev)
 425 {
 426         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 427                 /* The dmadev already stopped */
 428                 hisi_dma_free_iomem(dev->data->dev_private);
 429         }
 430         return 0;
 431 }
 432
 433 static int
 434 hisi_dma_stats_get(const struct rte_dma_dev *dev, uint16_t vchan,
 435                    struct rte_dma_stats *stats,
 436                    uint32_t stats_sz)
 437 {
 438         struct hisi_dma_dev *hw = dev->data->dev_private;
 439
 440         RTE_SET_USED(vchan);
 441         RTE_SET_USED(stats_sz);
 442         stats->submitted = hw->submitted;
 443         stats->completed = hw->completed;
 444         stats->errors = hw->errors;
 445
 446         return 0;
 447 }
 448
 449 static int
 450 hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
 451 {
 452         struct hisi_dma_dev *hw = dev->data->dev_private;
 453
 454         RTE_SET_USED(vchan);
 455         hw->submitted = 0;
 456         hw->completed = 0;
 457         hw->errors = 0;
 458
 459         return 0;
 460 }
 461
 462 static void
 463 hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start,
 464                     uint32_t end)
 465 {
 466 #define DUMP_REGNUM_PER_LINE    4
 467
 468         uint32_t cnt, i;
 469
 470         cnt = 0;
 471         for (i = start; i <= end; i += sizeof(uint32_t)) {
 472                 if (cnt % DUMP_REGNUM_PER_LINE == 0)
 473                         (void)fprintf(f, "      [%4x]:", i);
 474                 (void)fprintf(f, " 0x%08x", hisi_dma_read_dev(hw, i));
 475                 cnt++;
 476                 if (cnt % DUMP_REGNUM_PER_LINE == 0)
 477                         (void)fprintf(f, "\n");
 478         }
 479         if (cnt % DUMP_REGNUM_PER_LINE)
 480                 (void)fprintf(f, "\n");
 481 }
 482
 483 static void
 484 hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
 485 {
 486         struct {
 487                 uint8_t reg_layout;
 488                 uint32_t start;
 489                 uint32_t end;
 490         } reg_info[] = {
 491                 { HISI_DMA_REG_LAYOUT_HIP08,
 492                   HISI_DMA_HIP08_DUMP_START_REG,
 493                   HISI_DMA_HIP08_DUMP_END_REG },
 494                 { HISI_DMA_REG_LAYOUT_HIP09,
 495                   HISI_DMA_HIP09_DUMP_REGION_A_START_REG,
 496                   HISI_DMA_HIP09_DUMP_REGION_A_END_REG },
 497                 { HISI_DMA_REG_LAYOUT_HIP09,
 498                   HISI_DMA_HIP09_DUMP_REGION_B_START_REG,
 499                   HISI_DMA_HIP09_DUMP_REGION_B_END_REG },
 500                 { HISI_DMA_REG_LAYOUT_HIP09,
 501                   HISI_DMA_HIP09_DUMP_REGION_C_START_REG,
 502                   HISI_DMA_HIP09_DUMP_REGION_C_END_REG },
 503                 { HISI_DMA_REG_LAYOUT_HIP09,
 504                   HISI_DMA_HIP09_DUMP_REGION_D_START_REG,
 505                   HISI_DMA_HIP09_DUMP_REGION_D_END_REG },
 506         };
 507         uint32_t i;
 508
 509         (void)fprintf(f, "    common-register:\n");
 510         for (i = 0; i < RTE_DIM(reg_info); i++) {
 511                 if (hw->reg_layout != reg_info[i].reg_layout)
 512                         continue;
 513                 hisi_dma_dump_range(hw, f, reg_info[i].start, reg_info[i].end);
 514         }
 515 }
 516
 517 static void
 518 hisi_dma_dump_read_queue(struct hisi_dma_dev *hw, uint32_t qoff,
 519                          char *buffer, int max_sz)
 520 {
 521         memset(buffer, 0, max_sz);
 522
 523         /* Address-related registers are not printed for security reasons. */
 524         if (qoff == HISI_DMA_QUEUE_SQ_BASE_L_REG ||
 525             qoff == HISI_DMA_QUEUE_SQ_BASE_H_REG ||
 526             qoff == HISI_DMA_QUEUE_CQ_BASE_L_REG ||
 527             qoff == HISI_DMA_QUEUE_CQ_BASE_H_REG) {
 528                 (void)snprintf(buffer, max_sz, "**********");
 529                 return;
 530         }
 531
 532         (void)snprintf(buffer, max_sz, "0x%08x", hisi_dma_read_queue(hw, qoff));
 533 }
 534
 535 static void
 536 hisi_dma_dump_queue(struct hisi_dma_dev *hw, FILE *f)
 537 {
 538 #define REG_FMT_LEN     32
 539         char buf[REG_FMT_LEN] = { 0 };
 540         uint32_t i;
 541
 542         (void)fprintf(f, "    queue-register:\n");
 543         for (i = 0; i < HISI_DMA_QUEUE_REGION_SIZE; ) {
 544                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 545                 (void)fprintf(f, "      [%2x]: %s", i, buf);
 546                 i += sizeof(uint32_t);
 547                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 548                 (void)fprintf(f, " %s", buf);
 549                 i += sizeof(uint32_t);
 550                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 551                 (void)fprintf(f, " %s", buf);
 552                 i += sizeof(uint32_t);
 553                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 554                 (void)fprintf(f, " %s\n", buf);
 555                 i += sizeof(uint32_t);
 556         }
 557 }
 558
 559 static int
 560 hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
 561 {
 562         struct hisi_dma_dev *hw = dev->data->dev_private;
 563
 564         (void)fprintf(f,
 565                 "    revision: 0x%x queue_id: %u ring_size: %u\n"
 566                 "    ridx: %u cridx: %u\n"
 567                 "    sq_head: %u sq_tail: %u cq_sq_head: %u\n"
 568                 "    cq_head: %u cqs_completed: %u cqe_vld: %u\n"
 569                 "    submitted: %" PRIu64 " completed: %" PRIu64 " errors %"
 570                 PRIu64"\n",
 571                 hw->revision, hw->queue_id,
 572                 hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0,
 573                 hw->ridx, hw->cridx,
 574                 hw->sq_head, hw->sq_tail, hw->cq_sq_head,
 575                 hw->cq_head, hw->cqs_completed, hw->cqe_vld,
 576                 hw->submitted, hw->completed, hw->errors);
 577         hisi_dma_dump_queue(hw, f);
 578         hisi_dma_dump_common(hw, f);
 579
 580         return 0;
 581 }
 582
 583 static int
 584 hisi_dma_copy(void *dev_private, uint16_t vchan,
 585                  rte_iova_t src, rte_iova_t dst,
 586                  uint32_t length, uint64_t flags)
 587 {
 588         struct hisi_dma_dev *hw = dev_private;
 589         struct hisi_dma_sqe *sqe = &hw->sqe[hw->sq_tail];
 590
 591         RTE_SET_USED(vchan);
 592
 593         if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head)
 594                 return -ENOSPC;
 595
 596         sqe->dw0 = rte_cpu_to_le_32(SQE_OPCODE_M2M);
 597         sqe->dw1 = 0;
 598         sqe->dw2 = 0;
 599         sqe->length = rte_cpu_to_le_32(length);
 600         sqe->src_addr = rte_cpu_to_le_64(src);
 601         sqe->dst_addr = rte_cpu_to_le_64(dst);
 602         hw->sq_tail = (hw->sq_tail + 1) & hw->sq_depth_mask;
 603         hw->submitted++;
 604
 605         if (flags & RTE_DMA_OP_FLAG_FENCE)
 606                 sqe->dw0 |= rte_cpu_to_le_32(SQE_FENCE_FLAG);
 607         if (flags & RTE_DMA_OP_FLAG_SUBMIT)
 608                 rte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);
 609
 610         return hw->ridx++;
 611 }
 612
 613 static int
 614 hisi_dma_submit(void *dev_private, uint16_t vchan)
 615 {
 616         struct hisi_dma_dev *hw = dev_private;
 617
 618         RTE_SET_USED(vchan);
 619         rte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);
 620
 621         return 0;
 622 }
 623
 624 static inline void
 625 hisi_dma_scan_cq(struct hisi_dma_dev *hw)
 626 {
 627         volatile struct hisi_dma_cqe *cqe;
 628         uint16_t csq_head = hw->cq_sq_head;
 629         uint16_t cq_head = hw->cq_head;
 630         uint16_t count = 0;
 631         uint64_t misc;
 632
 633         while (true) {
 634                 cqe = &hw->cqe[cq_head];
 635                 misc = cqe->misc;
 636                 misc = rte_le_to_cpu_64(misc);
 637                 if (FIELD_GET(CQE_VALID_B, misc) != hw->cqe_vld)
 638                         break;
 639
 640                 csq_head = FIELD_GET(CQE_SQ_HEAD_MASK, misc);
 641                 if (unlikely(misc & CQE_STATUS_MASK))
 642                         hw->status[csq_head] = FIELD_GET(CQE_STATUS_MASK,
 643                                                          misc);
 644
 645                 count++;
 646                 cq_head++;
 647                 if (cq_head == hw->cq_depth) {
 648                         hw->cqe_vld = !hw->cqe_vld;
 649                         cq_head = 0;
 650                 }
 651         }
 652
 653         if (count == 0)
 654                 return;
 655
 656         hw->cq_head = cq_head;
 657         hw->cq_sq_head = (csq_head + 1) & hw->sq_depth_mask;
 658         hw->cqs_completed += count;
 659         if (hw->cqs_completed >= HISI_DMA_CQ_RESERVED) {
 660                 rte_write32(rte_cpu_to_le_32(cq_head), hw->cq_head_reg);
 661                 hw->cqs_completed = 0;
 662         }
 663 }
 664
 665 static inline uint16_t
 666 hisi_dma_calc_cpls(struct hisi_dma_dev *hw, const uint16_t nb_cpls)
 667 {
 668         uint16_t cpl_num;
 669
 670         if (hw->cq_sq_head >= hw->sq_head)
 671                 cpl_num = hw->cq_sq_head - hw->sq_head;
 672         else
 673                 cpl_num = hw->sq_depth_mask + 1 - hw->sq_head + hw->cq_sq_head;
 674
 675         if (cpl_num > nb_cpls)
 676                 cpl_num = nb_cpls;
 677
 678         return cpl_num;
 679 }
 680
 681 static uint16_t
 682 hisi_dma_completed(void *dev_private,
 683                    uint16_t vchan, const uint16_t nb_cpls,
 684                    uint16_t *last_idx, bool *has_error)
 685 {
 686         struct hisi_dma_dev *hw = dev_private;
 687         uint16_t sq_head = hw->sq_head;
 688         uint16_t cpl_num, i;
 689
 690         RTE_SET_USED(vchan);
 691         hisi_dma_scan_cq(hw);
 692
 693         cpl_num = hisi_dma_calc_cpls(hw, nb_cpls);
 694         for (i = 0; i < cpl_num; i++) {
 695                 if (hw->status[sq_head]) {
 696                         *has_error = true;
 697                         break;
 698                 }
 699                 sq_head = (sq_head + 1) & hw->sq_depth_mask;
 700         }
 701         if (i > 0) {
 702                 hw->cridx += i;
 703                 *last_idx = hw->cridx - 1;
 704                 hw->sq_head = sq_head;
 705         }
 706         hw->completed += i;
 707
 708         return i;
 709 }
 710
 711 static enum rte_dma_status_code
 712 hisi_dma_convert_status(uint16_t status)
 713 {
 714         switch (status) {
 715         case HISI_DMA_STATUS_SUCCESS:
 716                 return RTE_DMA_STATUS_SUCCESSFUL;
 717         case HISI_DMA_STATUS_INVALID_OPCODE:
 718                 return RTE_DMA_STATUS_INVALID_OPCODE;
 719         case HISI_DMA_STATUS_INVALID_LENGTH:
 720                 return RTE_DMA_STATUS_INVALID_LENGTH;
 721         case HISI_DMA_STATUS_USER_ABORT:
 722                 return RTE_DMA_STATUS_USER_ABORT;
 723         case HISI_DMA_STATUS_REMOTE_READ_ERROR:
 724         case HISI_DMA_STATUS_AXI_READ_ERROR:
 725                 return RTE_DMA_STATUS_BUS_READ_ERROR;
 726         case HISI_DMA_STATUS_AXI_WRITE_ERROR:
 727                 return RTE_DMA_STATUS_BUS_WRITE_ERROR;
 728         case HISI_DMA_STATUS_DATA_POISON:
 729         case HISI_DMA_STATUS_REMOTE_DATA_POISION:
 730                 return RTE_DMA_STATUS_DATA_POISION;
 731         case HISI_DMA_STATUS_SQE_READ_ERROR:
 732         case HISI_DMA_STATUS_SQE_READ_POISION:
 733                 return RTE_DMA_STATUS_DESCRIPTOR_READ_ERROR;
 734         case HISI_DMA_STATUS_LINK_DOWN_ERROR:
 735                 return RTE_DMA_STATUS_DEV_LINK_ERROR;
 736         default:
 737                 return RTE_DMA_STATUS_ERROR_UNKNOWN;
 738         }
 739 }
 740
 741 static uint16_t
 742 hisi_dma_completed_status(void *dev_private,
 743                           uint16_t vchan, const uint16_t nb_cpls,
 744                           uint16_t *last_idx, enum rte_dma_status_code *status)
 745 {
 746         struct hisi_dma_dev *hw = dev_private;
 747         uint16_t sq_head = hw->sq_head;
 748         uint16_t cpl_num, i;
 749
 750         RTE_SET_USED(vchan);
 751         hisi_dma_scan_cq(hw);
 752
 753         cpl_num = hisi_dma_calc_cpls(hw, nb_cpls);
 754         for (i = 0; i < cpl_num; i++) {
 755                 status[i] = hisi_dma_convert_status(hw->status[sq_head]);
 756                 hw->errors += !!status[i];
 757                 hw->status[sq_head] = HISI_DMA_STATUS_SUCCESS;
 758                 sq_head = (sq_head + 1) & hw->sq_depth_mask;
 759         }
 760         if (likely(cpl_num > 0)) {
 761                 hw->cridx += cpl_num;
 762                 *last_idx = hw->cridx - 1;
 763                 hw->sq_head = sq_head;
 764         }
 765         hw->completed += cpl_num;
 766
 767         return cpl_num;
 768 }
 769
 770 static uint16_t
 771 hisi_dma_burst_capacity(const void *dev_private, uint16_t vchan)
 772 {
 773         const struct hisi_dma_dev *hw = dev_private;
 774         uint16_t sq_head = hw->sq_head;
 775         uint16_t sq_tail = hw->sq_tail;
 776
 777         RTE_SET_USED(vchan);
 778
 779         return (sq_tail >= sq_head) ? hw->sq_depth_mask - sq_tail + sq_head :
 780                                       sq_head - 1 - sq_tail;
 781 }
 782
 783 static void
 784 hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,
 785                              char *name, size_t size)
 786 {
 787         memset(name, 0, size);
 788         (void)snprintf(name, size, "%x:%x.%x",
 789                  pci_dev->addr.bus, pci_dev->addr.devid,
 790                  pci_dev->addr.function);
 791 }
 792
 793 static void
 794 hisi_dma_gen_dev_name(const struct rte_pci_device *pci_dev,
 795                       uint8_t queue_id, char *name, size_t size)
 796 {
 797         memset(name, 0, size);
 798         (void)snprintf(name, size, "%x:%x.%x-ch%u",
 799                  pci_dev->addr.bus, pci_dev->addr.devid,
 800                  pci_dev->addr.function, queue_id);
 801 }
 802
 803 /**
 804  * Hardware queue state machine:
 805  *
 806  *   -----------  dmadev_create   ------------------
 807  *   | Unknown | ---------------> |      IDLE      |
 808  *   -----------                  ------------------
 809  *                                   ^          |
 810  *                                   |          |dev_start
 811  *                           dev_stop|          |
 812  *                                   |          v
 813  *                                ------------------
 814  *                                |      RUN       |
 815  *                                ------------------
 816  *
 817  */
 818 static const struct rte_dma_dev_ops hisi_dmadev_ops = {
 819         .dev_info_get     = hisi_dma_info_get,
 820         .dev_configure    = hisi_dma_configure,
 821         .dev_start        = hisi_dma_start,
 822         .dev_stop         = hisi_dma_stop,
 823         .dev_close        = hisi_dma_close,
 824         .vchan_setup      = hisi_dma_vchan_setup,
 825         .stats_get        = hisi_dma_stats_get,
 826         .stats_reset      = hisi_dma_stats_reset,
 827         .dev_dump         = hisi_dma_dump,
 828 };
 829
 830 static int
 831 hisi_dma_create(struct rte_pci_device *pci_dev, uint8_t queue_id,
 832                 uint8_t revision)
 833 {
 834 #define REG_PCI_BAR_INDEX       2
 835
 836         char name[RTE_DEV_NAME_MAX_LEN];
 837         struct rte_dma_dev *dev;
 838         struct hisi_dma_dev *hw;
 839         int ret;
 840
 841         hisi_dma_gen_dev_name(pci_dev, queue_id, name, sizeof(name));
 842         dev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
 843                                    sizeof(*hw));
 844         if (dev == NULL) {
 845                 HISI_DMA_LOG(ERR, "%s allocate dmadev fail!", name);
 846                 return -EINVAL;
 847         }
 848
 849         dev->device = &pci_dev->device;
 850         dev->dev_ops = &hisi_dmadev_ops;
 851         dev->fp_obj->dev_private = dev->data->dev_private;
 852         dev->fp_obj->copy = hisi_dma_copy;
 853         dev->fp_obj->submit = hisi_dma_submit;
 854         dev->fp_obj->completed = hisi_dma_completed;
 855         dev->fp_obj->completed_status = hisi_dma_completed_status;
 856         dev->fp_obj->burst_capacity = hisi_dma_burst_capacity;
 857
 858         hw = dev->data->dev_private;
 859         hw->data = dev->data;
 860         hw->revision = revision;
 861         hw->reg_layout = hisi_dma_reg_layout(revision);
 862         hw->io_base = pci_dev->mem_resource[REG_PCI_BAR_INDEX].addr;
 863         hw->queue_id = queue_id;
 864         hw->sq_tail_reg = hisi_dma_queue_regaddr(hw,
 865                                                  HISI_DMA_QUEUE_SQ_TAIL_REG);
 866         hw->cq_head_reg = hisi_dma_queue_regaddr(hw,
 867                                                  HISI_DMA_QUEUE_CQ_HEAD_REG);
 868
 869         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 870                 ret = hisi_dma_reset_hw(hw);
 871                 if (ret) {
 872                         HISI_DMA_LOG(ERR, "%s init device fail!", name);
 873                         (void)rte_dma_pmd_release(name);
 874                         return -EIO;
 875                 }
 876         }
 877
 878         dev->state = RTE_DMA_DEV_READY;
 879         HISI_DMA_LOG(DEBUG, "%s create dmadev success!", name);
 880
 881         return 0;
 882 }
 883
 884 static int
 885 hisi_dma_check_revision(struct rte_pci_device *pci_dev, const char *name,
 886                         uint8_t *out_revision)
 887 {
 888         uint8_t revision;
 889         int ret;
 890
 891         ret = rte_pci_read_config(pci_dev, &revision, 1,
 892                                   HISI_DMA_PCI_REVISION_ID_REG);
 893         if (ret != 1) {
 894                 HISI_DMA_LOG(ERR, "%s read PCI revision failed!", name);
 895                 return -EINVAL;
 896         }
 897         if (hisi_dma_reg_layout(revision) == HISI_DMA_REG_LAYOUT_INVALID) {
 898                 HISI_DMA_LOG(ERR, "%s revision: 0x%x not supported!",
 899                              name, revision);
 900                 return -EINVAL;
 901         }
 902
 903         *out_revision = revision;
 904         return 0;
 905 }
 906
 907 static int
 908 hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
 909                struct rte_pci_device *pci_dev)
 910 {
 911         char name[RTE_DEV_NAME_MAX_LEN] = { 0 };
 912         uint8_t revision;
 913         uint8_t i;
 914         int ret;
 915
 916         hisi_dma_gen_pci_device_name(pci_dev, name, sizeof(name));
 917
 918         if (pci_dev->mem_resource[2].addr == NULL) {
 919                 HISI_DMA_LOG(ERR, "%s BAR2 is NULL!\n", name);
 920                 return -ENODEV;
 921         }
 922
 923         ret = hisi_dma_check_revision(pci_dev, name, &revision);
 924         if (ret)
 925                 return ret;
 926         HISI_DMA_LOG(DEBUG, "%s read PCI revision: 0x%x", name, revision);
 927
 928         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 929                 hisi_dma_init_gbl(pci_dev->mem_resource[2].addr, revision);
 930
 931         for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
 932                 ret = hisi_dma_create(pci_dev, i, revision);
 933                 if (ret) {
 934                         HISI_DMA_LOG(ERR, "%s create dmadev %u failed!",
 935                                      name, i);
 936                         break;
 937                 }
 938         }
 939
 940         return ret;
 941 }
 942
 943 static int
 944 hisi_dma_remove(struct rte_pci_device *pci_dev)
 945 {
 946         char name[RTE_DEV_NAME_MAX_LEN];
 947         uint8_t i;
 948         int ret;
 949
 950         for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
 951                 hisi_dma_gen_dev_name(pci_dev, i, name, sizeof(name));
 952                 ret = rte_dma_pmd_release(name);
 953                 if (ret)
 954                         return ret;
 955         }
 956
 957         return 0;
 958 }
 959
 960 static const struct rte_pci_id pci_id_hisi_dma_map[] = {
 961         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HISI_DMA_DEVICE_ID) },
 962         { .vendor_id = 0, }, /* sentinel */
 963 };
 964
 965 static struct rte_pci_driver hisi_dma_pmd_drv = {
 966         .id_table  = pci_id_hisi_dma_map,
 967         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 968         .probe     = hisi_dma_probe,
 969         .remove    = hisi_dma_remove,
 970 };
 971
 972 RTE_PMD_REGISTER_PCI(dma_hisilicon, hisi_dma_pmd_drv);
 973 RTE_PMD_REGISTER_PCI_TABLE(dma_hisilicon, pci_id_hisi_dma_map);
 974 RTE_PMD_REGISTER_KMOD_DEP(dma_hisilicon, "vfio-pci");