1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 HiSilicon Limited
8 #include <rte_bus_pci.h>
9 #include <rte_cycles.h>
13 #include <rte_malloc.h>
14 #include <rte_memzone.h>
16 #include <rte_dmadev_pmd.h>
18 #include "hisi_dmadev.h"
20 RTE_LOG_REGISTER_DEFAULT(hisi_dma_logtype, INFO);
21 #define HISI_DMA_LOG(level, fmt, args...) \
22 rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
23 "%s(): " fmt "\n", __func__, ##args)
24 #define HISI_DMA_LOG_RAW(hw, level, fmt, args...) \
25 rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
26 "%s %s(): " fmt "\n", (hw)->data->dev_name, \
28 #define HISI_DMA_DEBUG(hw, fmt, args...) \
29 HISI_DMA_LOG_RAW(hw, DEBUG, fmt, ## args)
30 #define HISI_DMA_INFO(hw, fmt, args...) \
31 HISI_DMA_LOG_RAW(hw, INFO, fmt, ## args)
32 #define HISI_DMA_WARN(hw, fmt, args...) \
33 HISI_DMA_LOG_RAW(hw, WARNING, fmt, ## args)
34 #define HISI_DMA_ERR(hw, fmt, args...) \
35 HISI_DMA_LOG_RAW(hw, ERR, fmt, ## args)
38 hisi_dma_queue_base(struct hisi_dma_dev *hw)
40 if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)
41 return HISI_DMA_HIP08_QUEUE_BASE;
42 else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
43 return HISI_DMA_HIP09_QUEUE_BASE;
48 static volatile void *
49 hisi_dma_queue_regaddr(struct hisi_dma_dev *hw, uint32_t qoff)
51 uint32_t off = hisi_dma_queue_base(hw) +
52 hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
53 return (volatile void *)((char *)hw->io_base + off);
57 hisi_dma_write_reg(void *base, uint32_t off, uint32_t val)
59 rte_write32(rte_cpu_to_le_32(val),
60 (volatile void *)((char *)base + off));
64 hisi_dma_write_dev(struct hisi_dma_dev *hw, uint32_t off, uint32_t val)
66 hisi_dma_write_reg(hw->io_base, off, val);
70 hisi_dma_write_queue(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t val)
72 uint32_t off = hisi_dma_queue_base(hw) +
73 hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
74 hisi_dma_write_dev(hw, off, val);
78 hisi_dma_read_reg(void *base, uint32_t off)
80 uint32_t val = rte_read32((volatile void *)((char *)base + off));
81 return rte_le_to_cpu_32(val);
85 hisi_dma_read_dev(struct hisi_dma_dev *hw, uint32_t off)
87 return hisi_dma_read_reg(hw->io_base, off);
91 hisi_dma_read_queue(struct hisi_dma_dev *hw, uint32_t qoff)
93 uint32_t off = hisi_dma_queue_base(hw) +
94 hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
95 return hisi_dma_read_dev(hw, off);
99 hisi_dma_update_bit(struct hisi_dma_dev *hw, uint32_t off, uint32_t pos,
102 uint32_t tmp = hisi_dma_read_dev(hw, off);
103 uint32_t mask = 1u << pos;
104 tmp = set ? tmp | mask : tmp & ~mask;
105 hisi_dma_write_dev(hw, off, tmp);
109 hisi_dma_update_queue_bit(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t pos,
112 uint32_t tmp = hisi_dma_read_queue(hw, qoff);
113 uint32_t mask = 1u << pos;
114 tmp = set ? tmp | mask : tmp & ~mask;
115 hisi_dma_write_queue(hw, qoff, tmp);
119 hisi_dma_update_queue_mbit(struct hisi_dma_dev *hw, uint32_t qoff,
120 uint32_t mask, bool set)
122 uint32_t tmp = hisi_dma_read_queue(hw, qoff);
123 tmp = set ? tmp | mask : tmp & ~mask;
124 hisi_dma_write_queue(hw, qoff, tmp);
127 #define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) ({ \
128 uint32_t timeout = 0; \
129 while (timeout++ <= (timeout_us)) { \
130 (val) = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); \
133 rte_delay_us(sleep_us); \
135 (cond) ? 0 : -ETIME; \
139 hisi_dma_reset_hw(struct hisi_dma_dev *hw)
141 #define POLL_SLEEP_US 100
142 #define POLL_TIMEOUT_US 10000
147 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
148 HISI_DMA_QUEUE_CTRL0_PAUSE_B, true);
149 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
150 HISI_DMA_QUEUE_CTRL0_EN_B, false);
152 ret = hisi_dma_poll_hw_state(hw, tmp,
153 FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) != HISI_DMA_STATE_RUN,
154 POLL_SLEEP_US, POLL_TIMEOUT_US);
156 HISI_DMA_ERR(hw, "disable dma timeout!");
160 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
161 HISI_DMA_QUEUE_CTRL1_RESET_B, true);
162 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
163 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
164 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
165 HISI_DMA_QUEUE_CTRL0_PAUSE_B, false);
167 ret = hisi_dma_poll_hw_state(hw, tmp,
168 FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) == HISI_DMA_STATE_IDLE,
169 POLL_SLEEP_US, POLL_TIMEOUT_US);
171 HISI_DMA_ERR(hw, "reset dma timeout!");
179 hisi_dma_init_common(struct hisi_dma_dev *hw)
181 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_L_REG,
182 lower_32_bits(hw->sqe_iova));
183 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_H_REG,
184 upper_32_bits(hw->sqe_iova));
185 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_BASE_L_REG,
186 lower_32_bits(hw->cqe_iova));
187 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_BASE_H_REG,
188 upper_32_bits(hw->cqe_iova));
189 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_DEPTH_REG,
191 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_DEPTH_REG, hw->cq_depth - 1);
192 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
193 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
194 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM0_REG, 0);
195 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM1_REG, 0);
196 hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM2_REG, 0);
200 hisi_dma_init_hw(struct hisi_dma_dev *hw)
202 hisi_dma_init_common(hw);
204 if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
205 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG,
207 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM4_REG,
209 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM5_REG,
211 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM6_REG,
213 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
214 HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B, false);
215 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
216 HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
217 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
218 HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
219 } else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) {
220 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG,
221 HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false);
222 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
223 HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
224 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
225 HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
226 hisi_dma_update_queue_mbit(hw,
227 HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG,
228 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
229 hisi_dma_update_queue_mbit(hw,
230 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG,
231 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
232 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
233 HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true);
234 hisi_dma_update_bit(hw,
235 HISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id),
236 HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B,
242 hisi_dma_init_gbl(void *pci_bar, uint8_t revision)
244 struct hisi_dma_dev hw;
246 memset(&hw, 0, sizeof(hw));
247 hw.io_base = pci_bar;
249 if (revision == HISI_DMA_REVISION_HIP08B)
250 hisi_dma_update_bit(&hw, HISI_DMA_HIP08_MODE_REG,
251 HISI_DMA_HIP08_MODE_SEL_B, true);
255 hisi_dma_reg_layout(uint8_t revision)
257 if (revision == HISI_DMA_REVISION_HIP08B)
258 return HISI_DMA_REG_LAYOUT_HIP08;
259 else if (revision >= HISI_DMA_REVISION_HIP09A)
260 return HISI_DMA_REG_LAYOUT_HIP09;
262 return HISI_DMA_REG_LAYOUT_INVALID;
266 hisi_dma_zero_iomem(struct hisi_dma_dev *hw)
268 memset(hw->iomz->addr, 0, hw->iomz_sz);
272 hisi_dma_alloc_iomem(struct hisi_dma_dev *hw, uint16_t ring_size,
273 const char *dev_name)
275 uint32_t sq_size = sizeof(struct hisi_dma_sqe) * ring_size;
276 uint32_t cq_size = sizeof(struct hisi_dma_cqe) *
277 (ring_size + HISI_DMA_CQ_RESERVED);
278 uint32_t status_size = sizeof(uint16_t) * ring_size;
279 char mz_name[RTE_MEMZONE_NAMESIZE];
280 const struct rte_memzone *iomz;
283 sq_size = RTE_CACHE_LINE_ROUNDUP(sq_size);
284 cq_size = RTE_CACHE_LINE_ROUNDUP(cq_size);
285 status_size = RTE_CACHE_LINE_ROUNDUP(status_size);
286 total_size = sq_size + cq_size + status_size;
288 (void)snprintf(mz_name, sizeof(mz_name), "hisi_dma:%s", dev_name);
289 iomz = rte_memzone_reserve(mz_name, total_size, hw->data->numa_node,
290 RTE_MEMZONE_IOVA_CONTIG);
292 HISI_DMA_ERR(hw, "malloc %s iomem fail!", mz_name);
297 hw->iomz_sz = total_size;
298 hw->sqe = iomz->addr;
299 hw->cqe = (void *)((char *)iomz->addr + sq_size);
300 hw->status = (void *)((char *)iomz->addr + sq_size + cq_size);
301 hw->sqe_iova = iomz->iova;
302 hw->cqe_iova = iomz->iova + sq_size;
303 hw->sq_depth_mask = ring_size - 1;
304 hw->cq_depth = ring_size + HISI_DMA_CQ_RESERVED;
305 hisi_dma_zero_iomem(hw);
311 hisi_dma_free_iomem(struct hisi_dma_dev *hw)
313 if (hw->iomz != NULL)
314 rte_memzone_free(hw->iomz);
322 hw->sq_depth_mask = 0;
327 hisi_dma_info_get(const struct rte_dma_dev *dev,
328 struct rte_dma_info *dev_info,
331 struct hisi_dma_dev *hw = dev->data->dev_private;
332 RTE_SET_USED(info_sz);
334 dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
335 RTE_DMA_CAPA_OPS_COPY;
336 if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
337 dev_info->dev_capa |= RTE_DMA_CAPA_HANDLES_ERRORS;
339 dev_info->max_vchans = 1;
340 dev_info->max_desc = HISI_DMA_MAX_DESC_NUM;
341 dev_info->min_desc = HISI_DMA_MIN_DESC_NUM;
347 hisi_dma_configure(struct rte_dma_dev *dev,
348 const struct rte_dma_conf *conf,
353 RTE_SET_USED(conf_sz);
358 hisi_dma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
359 const struct rte_dma_vchan_conf *conf,
362 struct hisi_dma_dev *hw = dev->data->dev_private;
366 RTE_SET_USED(conf_sz);
368 if (!rte_is_power_of_2(conf->nb_desc)) {
369 HISI_DMA_ERR(hw, "Number of desc must be power of 2!");
373 hisi_dma_free_iomem(hw);
374 ret = hisi_dma_alloc_iomem(hw, conf->nb_desc, dev->data->dev_name);
382 hisi_dma_start(struct rte_dma_dev *dev)
384 struct hisi_dma_dev *hw = dev->data->dev_private;
386 if (hw->iomz == NULL) {
387 HISI_DMA_ERR(hw, "Vchan was not setup, start fail!\n");
391 /* Reset the dmadev to a known state, include:
392 * 1) zero iomem, also include status fields.
393 * 2) init hardware register.
394 * 3) init index values to zero.
395 * 4) init running statistics.
397 hisi_dma_zero_iomem(hw);
398 hisi_dma_init_hw(hw);
405 hw->cqs_completed = 0;
412 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
413 HISI_DMA_QUEUE_CTRL0_EN_B, true);
419 hisi_dma_stop(struct rte_dma_dev *dev)
421 return hisi_dma_reset_hw(dev->data->dev_private);
425 hisi_dma_close(struct rte_dma_dev *dev)
427 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
428 /* The dmadev already stopped */
429 hisi_dma_free_iomem(dev->data->dev_private);
435 hisi_dma_stats_get(const struct rte_dma_dev *dev, uint16_t vchan,
436 struct rte_dma_stats *stats,
439 struct hisi_dma_dev *hw = dev->data->dev_private;
442 RTE_SET_USED(stats_sz);
443 stats->submitted = hw->submitted;
444 stats->completed = hw->completed;
445 stats->errors = hw->errors;
451 hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
453 struct hisi_dma_dev *hw = dev->data->dev_private;
465 hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start,
468 #define DUMP_REGNUM_PER_LINE 4
473 for (i = start; i <= end; i += sizeof(uint32_t)) {
474 if (cnt % DUMP_REGNUM_PER_LINE == 0)
475 (void)fprintf(f, " [%4x]:", i);
476 (void)fprintf(f, " 0x%08x", hisi_dma_read_dev(hw, i));
478 if (cnt % DUMP_REGNUM_PER_LINE == 0)
479 (void)fprintf(f, "\n");
481 if (cnt % DUMP_REGNUM_PER_LINE)
482 (void)fprintf(f, "\n");
486 hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
493 { HISI_DMA_REG_LAYOUT_HIP08,
494 HISI_DMA_HIP08_DUMP_START_REG,
495 HISI_DMA_HIP08_DUMP_END_REG },
496 { HISI_DMA_REG_LAYOUT_HIP09,
497 HISI_DMA_HIP09_DUMP_REGION_A_START_REG,
498 HISI_DMA_HIP09_DUMP_REGION_A_END_REG },
499 { HISI_DMA_REG_LAYOUT_HIP09,
500 HISI_DMA_HIP09_DUMP_REGION_B_START_REG,
501 HISI_DMA_HIP09_DUMP_REGION_B_END_REG },
502 { HISI_DMA_REG_LAYOUT_HIP09,
503 HISI_DMA_HIP09_DUMP_REGION_C_START_REG,
504 HISI_DMA_HIP09_DUMP_REGION_C_END_REG },
505 { HISI_DMA_REG_LAYOUT_HIP09,
506 HISI_DMA_HIP09_DUMP_REGION_D_START_REG,
507 HISI_DMA_HIP09_DUMP_REGION_D_END_REG },
511 (void)fprintf(f, " common-register:\n");
512 for (i = 0; i < RTE_DIM(reg_info); i++) {
513 if (hw->reg_layout != reg_info[i].reg_layout)
515 hisi_dma_dump_range(hw, f, reg_info[i].start, reg_info[i].end);
520 hisi_dma_dump_read_queue(struct hisi_dma_dev *hw, uint32_t qoff,
521 char *buffer, int max_sz)
523 memset(buffer, 0, max_sz);
525 /* Address-related registers are not printed for security reasons. */
526 if (qoff == HISI_DMA_QUEUE_SQ_BASE_L_REG ||
527 qoff == HISI_DMA_QUEUE_SQ_BASE_H_REG ||
528 qoff == HISI_DMA_QUEUE_CQ_BASE_L_REG ||
529 qoff == HISI_DMA_QUEUE_CQ_BASE_H_REG) {
530 (void)snprintf(buffer, max_sz, "**********");
534 (void)snprintf(buffer, max_sz, "0x%08x", hisi_dma_read_queue(hw, qoff));
538 hisi_dma_dump_queue(struct hisi_dma_dev *hw, FILE *f)
540 #define REG_FMT_LEN 32
541 char buf[REG_FMT_LEN] = { 0 };
544 (void)fprintf(f, " queue-register:\n");
545 for (i = 0; i < HISI_DMA_QUEUE_REGION_SIZE; ) {
546 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
547 (void)fprintf(f, " [%2x]: %s", i, buf);
548 i += sizeof(uint32_t);
549 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
550 (void)fprintf(f, " %s", buf);
551 i += sizeof(uint32_t);
552 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
553 (void)fprintf(f, " %s", buf);
554 i += sizeof(uint32_t);
555 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
556 (void)fprintf(f, " %s\n", buf);
557 i += sizeof(uint32_t);
562 hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
564 struct hisi_dma_dev *hw = dev->data->dev_private;
567 " revision: 0x%x queue_id: %u ring_size: %u\n"
568 " ridx: %u cridx: %u\n"
569 " sq_head: %u sq_tail: %u cq_sq_head: %u\n"
570 " cq_head: %u cqs_completed: %u cqe_vld: %u\n"
571 " submitted: %" PRIu64 " completed: %" PRIu64 " errors: %"
572 PRIu64 " qfulls: %" PRIu64 "\n",
573 hw->revision, hw->queue_id,
574 hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0,
576 hw->sq_head, hw->sq_tail, hw->cq_sq_head,
577 hw->cq_head, hw->cqs_completed, hw->cqe_vld,
578 hw->submitted, hw->completed, hw->errors, hw->qfulls);
579 hisi_dma_dump_queue(hw, f);
580 hisi_dma_dump_common(hw, f);
586 hisi_dma_copy(void *dev_private, uint16_t vchan,
587 rte_iova_t src, rte_iova_t dst,
588 uint32_t length, uint64_t flags)
590 struct hisi_dma_dev *hw = dev_private;
591 struct hisi_dma_sqe *sqe = &hw->sqe[hw->sq_tail];
595 if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) {
600 sqe->dw0 = rte_cpu_to_le_32(SQE_OPCODE_M2M);
603 sqe->length = rte_cpu_to_le_32(length);
604 sqe->src_addr = rte_cpu_to_le_64(src);
605 sqe->dst_addr = rte_cpu_to_le_64(dst);
606 hw->sq_tail = (hw->sq_tail + 1) & hw->sq_depth_mask;
609 if (flags & RTE_DMA_OP_FLAG_FENCE)
610 sqe->dw0 |= rte_cpu_to_le_32(SQE_FENCE_FLAG);
611 if (flags & RTE_DMA_OP_FLAG_SUBMIT)
612 rte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);
618 hisi_dma_submit(void *dev_private, uint16_t vchan)
620 struct hisi_dma_dev *hw = dev_private;
623 rte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);
629 hisi_dma_scan_cq(struct hisi_dma_dev *hw)
631 volatile struct hisi_dma_cqe *cqe;
632 uint16_t csq_head = hw->cq_sq_head;
633 uint16_t cq_head = hw->cq_head;
638 cqe = &hw->cqe[cq_head];
640 misc = rte_le_to_cpu_64(misc);
641 if (FIELD_GET(CQE_VALID_B, misc) != hw->cqe_vld)
644 csq_head = FIELD_GET(CQE_SQ_HEAD_MASK, misc);
645 if (unlikely(misc & CQE_STATUS_MASK))
646 hw->status[csq_head] = FIELD_GET(CQE_STATUS_MASK,
651 if (cq_head == hw->cq_depth) {
652 hw->cqe_vld = !hw->cqe_vld;
660 hw->cq_head = cq_head;
661 hw->cq_sq_head = (csq_head + 1) & hw->sq_depth_mask;
662 hw->cqs_completed += count;
663 if (hw->cqs_completed >= HISI_DMA_CQ_RESERVED) {
664 rte_write32(rte_cpu_to_le_32(cq_head), hw->cq_head_reg);
665 hw->cqs_completed = 0;
669 static inline uint16_t
670 hisi_dma_calc_cpls(struct hisi_dma_dev *hw, const uint16_t nb_cpls)
674 if (hw->cq_sq_head >= hw->sq_head)
675 cpl_num = hw->cq_sq_head - hw->sq_head;
677 cpl_num = hw->sq_depth_mask + 1 - hw->sq_head + hw->cq_sq_head;
679 if (cpl_num > nb_cpls)
686 hisi_dma_completed(void *dev_private,
687 uint16_t vchan, const uint16_t nb_cpls,
688 uint16_t *last_idx, bool *has_error)
690 struct hisi_dma_dev *hw = dev_private;
691 uint16_t sq_head = hw->sq_head;
695 hisi_dma_scan_cq(hw);
697 cpl_num = hisi_dma_calc_cpls(hw, nb_cpls);
698 for (i = 0; i < cpl_num; i++) {
699 if (hw->status[sq_head]) {
703 sq_head = (sq_head + 1) & hw->sq_depth_mask;
707 *last_idx = hw->cridx - 1;
708 hw->sq_head = sq_head;
715 static enum rte_dma_status_code
716 hisi_dma_convert_status(uint16_t status)
719 case HISI_DMA_STATUS_SUCCESS:
720 return RTE_DMA_STATUS_SUCCESSFUL;
721 case HISI_DMA_STATUS_INVALID_OPCODE:
722 return RTE_DMA_STATUS_INVALID_OPCODE;
723 case HISI_DMA_STATUS_INVALID_LENGTH:
724 return RTE_DMA_STATUS_INVALID_LENGTH;
725 case HISI_DMA_STATUS_USER_ABORT:
726 return RTE_DMA_STATUS_USER_ABORT;
727 case HISI_DMA_STATUS_REMOTE_READ_ERROR:
728 case HISI_DMA_STATUS_AXI_READ_ERROR:
729 return RTE_DMA_STATUS_BUS_READ_ERROR;
730 case HISI_DMA_STATUS_AXI_WRITE_ERROR:
731 return RTE_DMA_STATUS_BUS_WRITE_ERROR;
732 case HISI_DMA_STATUS_DATA_POISON:
733 case HISI_DMA_STATUS_REMOTE_DATA_POISION:
734 return RTE_DMA_STATUS_DATA_POISION;
735 case HISI_DMA_STATUS_SQE_READ_ERROR:
736 case HISI_DMA_STATUS_SQE_READ_POISION:
737 return RTE_DMA_STATUS_DESCRIPTOR_READ_ERROR;
738 case HISI_DMA_STATUS_LINK_DOWN_ERROR:
739 return RTE_DMA_STATUS_DEV_LINK_ERROR;
741 return RTE_DMA_STATUS_ERROR_UNKNOWN;
746 hisi_dma_completed_status(void *dev_private,
747 uint16_t vchan, const uint16_t nb_cpls,
748 uint16_t *last_idx, enum rte_dma_status_code *status)
750 struct hisi_dma_dev *hw = dev_private;
751 uint16_t sq_head = hw->sq_head;
755 hisi_dma_scan_cq(hw);
757 cpl_num = hisi_dma_calc_cpls(hw, nb_cpls);
758 for (i = 0; i < cpl_num; i++) {
759 status[i] = hisi_dma_convert_status(hw->status[sq_head]);
760 hw->errors += !!status[i];
761 hw->status[sq_head] = HISI_DMA_STATUS_SUCCESS;
762 sq_head = (sq_head + 1) & hw->sq_depth_mask;
764 if (likely(cpl_num > 0)) {
765 hw->cridx += cpl_num;
766 *last_idx = hw->cridx - 1;
767 hw->sq_head = sq_head;
769 hw->completed += cpl_num;
775 hisi_dma_burst_capacity(const void *dev_private, uint16_t vchan)
777 const struct hisi_dma_dev *hw = dev_private;
778 uint16_t sq_head = hw->sq_head;
779 uint16_t sq_tail = hw->sq_tail;
783 return (sq_tail >= sq_head) ? hw->sq_depth_mask - sq_tail + sq_head :
784 sq_head - 1 - sq_tail;
788 hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,
789 char *name, size_t size)
791 memset(name, 0, size);
792 (void)snprintf(name, size, "%x:%x.%x",
793 pci_dev->addr.bus, pci_dev->addr.devid,
794 pci_dev->addr.function);
798 hisi_dma_gen_dev_name(const struct rte_pci_device *pci_dev,
799 uint8_t queue_id, char *name, size_t size)
801 memset(name, 0, size);
802 (void)snprintf(name, size, "%x:%x.%x-ch%u",
803 pci_dev->addr.bus, pci_dev->addr.devid,
804 pci_dev->addr.function, queue_id);
808 * Hardware queue state machine:
810 * ----------- dmadev_create ------------------
811 * | Unknown | ---------------> | IDLE |
812 * ----------- ------------------
822 static const struct rte_dma_dev_ops hisi_dmadev_ops = {
823 .dev_info_get = hisi_dma_info_get,
824 .dev_configure = hisi_dma_configure,
825 .dev_start = hisi_dma_start,
826 .dev_stop = hisi_dma_stop,
827 .dev_close = hisi_dma_close,
828 .vchan_setup = hisi_dma_vchan_setup,
829 .stats_get = hisi_dma_stats_get,
830 .stats_reset = hisi_dma_stats_reset,
831 .dev_dump = hisi_dma_dump,
835 hisi_dma_create(struct rte_pci_device *pci_dev, uint8_t queue_id,
838 #define REG_PCI_BAR_INDEX 2
840 char name[RTE_DEV_NAME_MAX_LEN];
841 struct rte_dma_dev *dev;
842 struct hisi_dma_dev *hw;
845 hisi_dma_gen_dev_name(pci_dev, queue_id, name, sizeof(name));
846 dev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
849 HISI_DMA_LOG(ERR, "%s allocate dmadev fail!", name);
853 dev->device = &pci_dev->device;
854 dev->dev_ops = &hisi_dmadev_ops;
855 dev->fp_obj->dev_private = dev->data->dev_private;
856 dev->fp_obj->copy = hisi_dma_copy;
857 dev->fp_obj->submit = hisi_dma_submit;
858 dev->fp_obj->completed = hisi_dma_completed;
859 dev->fp_obj->completed_status = hisi_dma_completed_status;
860 dev->fp_obj->burst_capacity = hisi_dma_burst_capacity;
862 hw = dev->data->dev_private;
863 hw->data = dev->data;
864 hw->revision = revision;
865 hw->reg_layout = hisi_dma_reg_layout(revision);
866 hw->io_base = pci_dev->mem_resource[REG_PCI_BAR_INDEX].addr;
867 hw->queue_id = queue_id;
868 hw->sq_tail_reg = hisi_dma_queue_regaddr(hw,
869 HISI_DMA_QUEUE_SQ_TAIL_REG);
870 hw->cq_head_reg = hisi_dma_queue_regaddr(hw,
871 HISI_DMA_QUEUE_CQ_HEAD_REG);
873 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
874 ret = hisi_dma_reset_hw(hw);
876 HISI_DMA_LOG(ERR, "%s init device fail!", name);
877 (void)rte_dma_pmd_release(name);
882 dev->state = RTE_DMA_DEV_READY;
883 HISI_DMA_LOG(DEBUG, "%s create dmadev success!", name);
889 hisi_dma_check_revision(struct rte_pci_device *pci_dev, const char *name,
890 uint8_t *out_revision)
895 ret = rte_pci_read_config(pci_dev, &revision, 1,
896 HISI_DMA_PCI_REVISION_ID_REG);
898 HISI_DMA_LOG(ERR, "%s read PCI revision failed!", name);
901 if (hisi_dma_reg_layout(revision) == HISI_DMA_REG_LAYOUT_INVALID) {
902 HISI_DMA_LOG(ERR, "%s revision: 0x%x not supported!",
907 *out_revision = revision;
912 hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
913 struct rte_pci_device *pci_dev)
915 char name[RTE_DEV_NAME_MAX_LEN] = { 0 };
920 hisi_dma_gen_pci_device_name(pci_dev, name, sizeof(name));
922 if (pci_dev->mem_resource[2].addr == NULL) {
923 HISI_DMA_LOG(ERR, "%s BAR2 is NULL!\n", name);
927 ret = hisi_dma_check_revision(pci_dev, name, &revision);
930 HISI_DMA_LOG(DEBUG, "%s read PCI revision: 0x%x", name, revision);
932 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
933 hisi_dma_init_gbl(pci_dev->mem_resource[2].addr, revision);
935 for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
936 ret = hisi_dma_create(pci_dev, i, revision);
938 HISI_DMA_LOG(ERR, "%s create dmadev %u failed!",
948 hisi_dma_remove(struct rte_pci_device *pci_dev)
950 char name[RTE_DEV_NAME_MAX_LEN];
954 for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
955 hisi_dma_gen_dev_name(pci_dev, i, name, sizeof(name));
956 ret = rte_dma_pmd_release(name);
964 static const struct rte_pci_id pci_id_hisi_dma_map[] = {
965 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HISI_DMA_DEVICE_ID) },
966 { .vendor_id = 0, }, /* sentinel */
969 static struct rte_pci_driver hisi_dma_pmd_drv = {
970 .id_table = pci_id_hisi_dma_map,
971 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
972 .probe = hisi_dma_probe,
973 .remove = hisi_dma_remove,
976 RTE_PMD_REGISTER_PCI(dma_hisilicon, hisi_dma_pmd_drv);
977 RTE_PMD_REGISTER_PCI_TABLE(dma_hisilicon, pci_id_hisi_dma_map);
978 RTE_PMD_REGISTER_KMOD_DEP(dma_hisilicon, "vfio-pci");