drivers/dma/hisilicon/hisi_dmadev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 HiSilicon Limited
   3  */
   4
   5 #include <inttypes.h>
   6 #include <string.h>
   7
   8 #include <rte_bus_pci.h>
   9 #include <rte_cycles.h>
  10 #include <rte_eal.h>
  11 #include <rte_io.h>
  12 #include <rte_log.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memzone.h>
  15 #include <rte_pci.h>
  16 #include <rte_dmadev_pmd.h>
  17
  18 #include "hisi_dmadev.h"
  19
  20 RTE_LOG_REGISTER_DEFAULT(hisi_dma_logtype, INFO);
  21 #define HISI_DMA_LOG(level, fmt, args...) \
  22                 rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
  23                 "%s(): " fmt "\n", __func__, ##args)
  24 #define HISI_DMA_LOG_RAW(hw, level, fmt, args...) \
  25                 rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
  26                 "%s %s(): " fmt "\n", (hw)->data->dev_name, \
  27                 __func__, ##args)
  28 #define HISI_DMA_DEBUG(hw, fmt, args...) \
  29                 HISI_DMA_LOG_RAW(hw, DEBUG, fmt, ## args)
  30 #define HISI_DMA_INFO(hw, fmt, args...) \
  31                 HISI_DMA_LOG_RAW(hw, INFO, fmt, ## args)
  32 #define HISI_DMA_WARN(hw, fmt, args...) \
  33                 HISI_DMA_LOG_RAW(hw, WARNING, fmt, ## args)
  34 #define HISI_DMA_ERR(hw, fmt, args...) \
  35                 HISI_DMA_LOG_RAW(hw, ERR, fmt, ## args)
  36
  37 static uint32_t
  38 hisi_dma_queue_base(struct hisi_dma_dev *hw)
  39 {
  40         if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)
  41                 return HISI_DMA_HIP08_QUEUE_BASE;
  42         else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
  43                 return HISI_DMA_HIP09_QUEUE_BASE;
  44         else
  45                 return 0;
  46 }
  47
  48 static volatile void *
  49 hisi_dma_queue_regaddr(struct hisi_dma_dev *hw, uint32_t qoff)
  50 {
  51         uint32_t off = hisi_dma_queue_base(hw) +
  52                         hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
  53         return (volatile void *)((char *)hw->io_base + off);
  54 }
  55
  56 static void
  57 hisi_dma_write_reg(void *base, uint32_t off, uint32_t val)
  58 {
  59         rte_write32(rte_cpu_to_le_32(val),
  60                     (volatile void *)((char *)base + off));
  61 }
  62
  63 static void
  64 hisi_dma_write_dev(struct hisi_dma_dev *hw, uint32_t off, uint32_t val)
  65 {
  66         hisi_dma_write_reg(hw->io_base, off, val);
  67 }
  68
  69 static void
  70 hisi_dma_write_queue(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t val)
  71 {
  72         uint32_t off = hisi_dma_queue_base(hw) +
  73                         hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
  74         hisi_dma_write_dev(hw, off, val);
  75 }
  76
  77 static uint32_t
  78 hisi_dma_read_reg(void *base, uint32_t off)
  79 {
  80         uint32_t val = rte_read32((volatile void *)((char *)base + off));
  81         return rte_le_to_cpu_32(val);
  82 }
  83
  84 static uint32_t
  85 hisi_dma_read_dev(struct hisi_dma_dev *hw, uint32_t off)
  86 {
  87         return hisi_dma_read_reg(hw->io_base, off);
  88 }
  89
  90 static uint32_t
  91 hisi_dma_read_queue(struct hisi_dma_dev *hw, uint32_t qoff)
  92 {
  93         uint32_t off = hisi_dma_queue_base(hw) +
  94                         hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
  95         return hisi_dma_read_dev(hw, off);
  96 }
  97
  98 static void
  99 hisi_dma_update_bit(struct hisi_dma_dev *hw, uint32_t off, uint32_t pos,
 100                     bool set)
 101 {
 102         uint32_t tmp = hisi_dma_read_dev(hw, off);
 103         uint32_t mask = 1u << pos;
 104         tmp = set ? tmp | mask : tmp & ~mask;
 105         hisi_dma_write_dev(hw, off, tmp);
 106 }
 107
 108 static void
 109 hisi_dma_update_queue_bit(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t pos,
 110                           bool set)
 111 {
 112         uint32_t tmp = hisi_dma_read_queue(hw, qoff);
 113         uint32_t mask = 1u << pos;
 114         tmp = set ? tmp | mask : tmp & ~mask;
 115         hisi_dma_write_queue(hw, qoff, tmp);
 116 }
 117
 118 static void
 119 hisi_dma_update_queue_mbit(struct hisi_dma_dev *hw, uint32_t qoff,
 120                            uint32_t mask, bool set)
 121 {
 122         uint32_t tmp = hisi_dma_read_queue(hw, qoff);
 123         tmp = set ? tmp | mask : tmp & ~mask;
 124         hisi_dma_write_queue(hw, qoff, tmp);
 125 }
 126
 127 #define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) ({ \
 128         uint32_t timeout = 0; \
 129         while (timeout++ <= (timeout_us)) { \
 130                 (val) = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); \
 131                 if (cond) \
 132                         break; \
 133                 rte_delay_us(sleep_us); \
 134         } \
 135         (cond) ? 0 : -ETIME; \
 136 })
 137
 138 static int
 139 hisi_dma_reset_hw(struct hisi_dma_dev *hw)
 140 {
 141 #define POLL_SLEEP_US   100
 142 #define POLL_TIMEOUT_US 10000
 143
 144         uint32_t tmp;
 145         int ret;
 146
 147         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 148                                   HISI_DMA_QUEUE_CTRL0_PAUSE_B, true);
 149         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 150                                   HISI_DMA_QUEUE_CTRL0_EN_B, false);
 151
 152         ret = hisi_dma_poll_hw_state(hw, tmp,
 153                 FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) != HISI_DMA_STATE_RUN,
 154                 POLL_SLEEP_US, POLL_TIMEOUT_US);
 155         if (ret) {
 156                 HISI_DMA_ERR(hw, "disable dma timeout!");
 157                 return ret;
 158         }
 159
 160         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
 161                                   HISI_DMA_QUEUE_CTRL1_RESET_B, true);
 162         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
 163         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
 164         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 165                                   HISI_DMA_QUEUE_CTRL0_PAUSE_B, false);
 166
 167         ret = hisi_dma_poll_hw_state(hw, tmp,
 168                 FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) == HISI_DMA_STATE_IDLE,
 169                 POLL_SLEEP_US, POLL_TIMEOUT_US);
 170         if (ret) {
 171                 HISI_DMA_ERR(hw, "reset dma timeout!");
 172                 return ret;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static void
 179 hisi_dma_init_common(struct hisi_dma_dev *hw)
 180 {
 181         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_L_REG,
 182                              lower_32_bits(hw->sqe_iova));
 183         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_H_REG,
 184                              upper_32_bits(hw->sqe_iova));
 185         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_BASE_L_REG,
 186                              lower_32_bits(hw->cqe_iova));
 187         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_BASE_H_REG,
 188                              upper_32_bits(hw->cqe_iova));
 189         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_DEPTH_REG,
 190                              hw->sq_depth_mask);
 191         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_DEPTH_REG, hw->cq_depth - 1);
 192         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
 193         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
 194         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM0_REG, 0);
 195         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM1_REG, 0);
 196         hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM2_REG, 0);
 197 }
 198
 199 static void
 200 hisi_dma_init_hw(struct hisi_dma_dev *hw)
 201 {
 202         hisi_dma_init_common(hw);
 203
 204         if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
 205                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG,
 206                                      0);
 207                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM4_REG,
 208                                      0);
 209                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM5_REG,
 210                                      0);
 211                 hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM6_REG,
 212                                      0);
 213                 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 214                                 HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B, false);
 215                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
 216                                 HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
 217                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
 218                                 HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
 219         } else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) {
 220                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 221                                 HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false);
 222                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
 223                                 HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
 224                 hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
 225                                 HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
 226                 hisi_dma_update_queue_mbit(hw,
 227                                 HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG,
 228                                 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
 229                 hisi_dma_update_queue_mbit(hw,
 230                                 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG,
 231                                 HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
 232                 hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
 233                                 HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true);
 234                 hisi_dma_update_bit(hw,
 235                                 HISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id),
 236                                 HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B,
 237                                 true);
 238         }
 239 }
 240
 241 static void
 242 hisi_dma_init_gbl(void *pci_bar, uint8_t revision)
 243 {
 244         struct hisi_dma_dev hw;
 245
 246         memset(&hw, 0, sizeof(hw));
 247         hw.io_base = pci_bar;
 248
 249         if (revision == HISI_DMA_REVISION_HIP08B)
 250                 hisi_dma_update_bit(&hw, HISI_DMA_HIP08_MODE_REG,
 251                                     HISI_DMA_HIP08_MODE_SEL_B, true);
 252 }
 253
 254 static uint8_t
 255 hisi_dma_reg_layout(uint8_t revision)
 256 {
 257         if (revision == HISI_DMA_REVISION_HIP08B)
 258                 return HISI_DMA_REG_LAYOUT_HIP08;
 259         else if (revision >= HISI_DMA_REVISION_HIP09A)
 260                 return HISI_DMA_REG_LAYOUT_HIP09;
 261         else
 262                 return HISI_DMA_REG_LAYOUT_INVALID;
 263 }
 264
 265 static void
 266 hisi_dma_zero_iomem(struct hisi_dma_dev *hw)
 267 {
 268         memset(hw->iomz->addr, 0, hw->iomz_sz);
 269 }
 270
 271 static int
 272 hisi_dma_alloc_iomem(struct hisi_dma_dev *hw, uint16_t ring_size,
 273                      const char *dev_name)
 274 {
 275         uint32_t sq_size = sizeof(struct hisi_dma_sqe) * ring_size;
 276         uint32_t cq_size = sizeof(struct hisi_dma_cqe) *
 277                            (ring_size + HISI_DMA_CQ_RESERVED);
 278         uint32_t status_size = sizeof(uint16_t) * ring_size;
 279         char mz_name[RTE_MEMZONE_NAMESIZE];
 280         const struct rte_memzone *iomz;
 281         uint32_t total_size;
 282
 283         sq_size = RTE_CACHE_LINE_ROUNDUP(sq_size);
 284         cq_size = RTE_CACHE_LINE_ROUNDUP(cq_size);
 285         status_size = RTE_CACHE_LINE_ROUNDUP(status_size);
 286         total_size = sq_size + cq_size + status_size;
 287
 288         (void)snprintf(mz_name, sizeof(mz_name), "hisi_dma:%s", dev_name);
 289         iomz = rte_memzone_reserve(mz_name, total_size, hw->data->numa_node,
 290                                    RTE_MEMZONE_IOVA_CONTIG);
 291         if (iomz == NULL) {
 292                 HISI_DMA_ERR(hw, "malloc %s iomem fail!", mz_name);
 293                 return -ENOMEM;
 294         }
 295
 296         hw->iomz = iomz;
 297         hw->iomz_sz = total_size;
 298         hw->sqe = iomz->addr;
 299         hw->cqe = (void *)((char *)iomz->addr + sq_size);
 300         hw->status = (void *)((char *)iomz->addr + sq_size + cq_size);
 301         hw->sqe_iova = iomz->iova;
 302         hw->cqe_iova = iomz->iova + sq_size;
 303         hw->sq_depth_mask = ring_size - 1;
 304         hw->cq_depth = ring_size + HISI_DMA_CQ_RESERVED;
 305         hisi_dma_zero_iomem(hw);
 306
 307         return 0;
 308 }
 309
 310 static void
 311 hisi_dma_free_iomem(struct hisi_dma_dev *hw)
 312 {
 313         if (hw->iomz != NULL)
 314                 rte_memzone_free(hw->iomz);
 315
 316         hw->iomz = NULL;
 317         hw->sqe = NULL;
 318         hw->cqe = NULL;
 319         hw->status = NULL;
 320         hw->sqe_iova = 0;
 321         hw->cqe_iova = 0;
 322         hw->sq_depth_mask = 0;
 323         hw->cq_depth = 0;
 324 }
 325
 326 static int
 327 hisi_dma_info_get(const struct rte_dma_dev *dev,
 328                   struct rte_dma_info *dev_info,
 329                   uint32_t info_sz)
 330 {
 331         RTE_SET_USED(dev);
 332         RTE_SET_USED(info_sz);
 333
 334         dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
 335                              RTE_DMA_CAPA_OPS_COPY;
 336         dev_info->max_vchans = 1;
 337         dev_info->max_desc = HISI_DMA_MAX_DESC_NUM;
 338         dev_info->min_desc = HISI_DMA_MIN_DESC_NUM;
 339
 340         return 0;
 341 }
 342
 343 static int
 344 hisi_dma_configure(struct rte_dma_dev *dev,
 345                    const struct rte_dma_conf *conf,
 346                    uint32_t conf_sz)
 347 {
 348         RTE_SET_USED(dev);
 349         RTE_SET_USED(conf);
 350         RTE_SET_USED(conf_sz);
 351         return 0;
 352 }
 353
 354 static int
 355 hisi_dma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
 356                      const struct rte_dma_vchan_conf *conf,
 357                      uint32_t conf_sz)
 358 {
 359         struct hisi_dma_dev *hw = dev->data->dev_private;
 360         int ret;
 361
 362         RTE_SET_USED(vchan);
 363         RTE_SET_USED(conf_sz);
 364
 365         if (!rte_is_power_of_2(conf->nb_desc)) {
 366                 HISI_DMA_ERR(hw, "Number of desc must be power of 2!");
 367                 return -EINVAL;
 368         }
 369
 370         hisi_dma_free_iomem(hw);
 371         ret = hisi_dma_alloc_iomem(hw, conf->nb_desc, dev->data->dev_name);
 372         if (ret)
 373                 return ret;
 374
 375         return 0;
 376 }
 377
 378 static int
 379 hisi_dma_start(struct rte_dma_dev *dev)
 380 {
 381         struct hisi_dma_dev *hw = dev->data->dev_private;
 382
 383         if (hw->iomz == NULL) {
 384                 HISI_DMA_ERR(hw, "Vchan was not setup, start fail!\n");
 385                 return -EINVAL;
 386         }
 387
 388         /* Reset the dmadev to a known state, include:
 389          *   1) zero iomem, also include status fields.
 390          *   2) init hardware register.
 391          *   3) init index values to zero.
 392          *   4) init running statistics.
 393          */
 394         hisi_dma_zero_iomem(hw);
 395         hisi_dma_init_hw(hw);
 396         hw->ridx = 0;
 397         hw->cridx = 0;
 398         hw->sq_head = 0;
 399         hw->sq_tail = 0;
 400         hw->cq_sq_head = 0;
 401         hw->cq_head = 0;
 402         hw->cqs_completed = 0;
 403         hw->cqe_vld = 1;
 404         hw->submitted = 0;
 405         hw->completed = 0;
 406         hw->errors = 0;
 407
 408         hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
 409                                   HISI_DMA_QUEUE_CTRL0_EN_B, true);
 410
 411         return 0;
 412 }
 413
 414 static int
 415 hisi_dma_stop(struct rte_dma_dev *dev)
 416 {
 417         return hisi_dma_reset_hw(dev->data->dev_private);
 418 }
 419
 420 static int
 421 hisi_dma_close(struct rte_dma_dev *dev)
 422 {
 423         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 424                 /* The dmadev already stopped */
 425                 hisi_dma_free_iomem(dev->data->dev_private);
 426         }
 427         return 0;
 428 }
 429
 430 static int
 431 hisi_dma_stats_get(const struct rte_dma_dev *dev, uint16_t vchan,
 432                    struct rte_dma_stats *stats,
 433                    uint32_t stats_sz)
 434 {
 435         struct hisi_dma_dev *hw = dev->data->dev_private;
 436
 437         RTE_SET_USED(vchan);
 438         RTE_SET_USED(stats_sz);
 439         stats->submitted = hw->submitted;
 440         stats->completed = hw->completed;
 441         stats->errors = hw->errors;
 442
 443         return 0;
 444 }
 445
 446 static int
 447 hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
 448 {
 449         struct hisi_dma_dev *hw = dev->data->dev_private;
 450
 451         RTE_SET_USED(vchan);
 452         hw->submitted = 0;
 453         hw->completed = 0;
 454         hw->errors = 0;
 455
 456         return 0;
 457 }
 458
 459 static void
 460 hisi_dma_get_dump_range(struct hisi_dma_dev *hw, uint32_t *start, uint32_t *end)
 461 {
 462         if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
 463                 *start = HISI_DMA_HIP08_DUMP_START_REG;
 464                 *end = HISI_DMA_HIP08_DUMP_END_REG;
 465         } else {
 466                 *start = 0;
 467                 *end = 0;
 468         }
 469 }
 470
 471 static void
 472 hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
 473 {
 474 #define DUMP_REGNUM_PER_LINE    4
 475
 476         uint32_t start, end;
 477         uint32_t cnt, i;
 478
 479         hisi_dma_get_dump_range(hw, &start, &end);
 480
 481         (void)fprintf(f, "    common-register:\n");
 482
 483         cnt = 0;
 484         for (i = start; i <= end; i += sizeof(uint32_t)) {
 485                 if (cnt % DUMP_REGNUM_PER_LINE == 0)
 486                         (void)fprintf(f, "      [%4x]:", i);
 487                 (void)fprintf(f, " 0x%08x", hisi_dma_read_dev(hw, i));
 488                 cnt++;
 489                 if (cnt % DUMP_REGNUM_PER_LINE == 0)
 490                         (void)fprintf(f, "\n");
 491         }
 492         if (cnt % DUMP_REGNUM_PER_LINE)
 493                 (void)fprintf(f, "\n");
 494 }
 495
 496 static void
 497 hisi_dma_dump_read_queue(struct hisi_dma_dev *hw, uint32_t qoff,
 498                          char *buffer, int max_sz)
 499 {
 500         memset(buffer, 0, max_sz);
 501
 502         /* Address-related registers are not printed for security reasons. */
 503         if (qoff == HISI_DMA_QUEUE_SQ_BASE_L_REG ||
 504             qoff == HISI_DMA_QUEUE_SQ_BASE_H_REG ||
 505             qoff == HISI_DMA_QUEUE_CQ_BASE_L_REG ||
 506             qoff == HISI_DMA_QUEUE_CQ_BASE_H_REG) {
 507                 (void)snprintf(buffer, max_sz, "**********");
 508                 return;
 509         }
 510
 511         (void)snprintf(buffer, max_sz, "0x%08x", hisi_dma_read_queue(hw, qoff));
 512 }
 513
 514 static void
 515 hisi_dma_dump_queue(struct hisi_dma_dev *hw, FILE *f)
 516 {
 517 #define REG_FMT_LEN     32
 518         char buf[REG_FMT_LEN] = { 0 };
 519         uint32_t i;
 520
 521         (void)fprintf(f, "    queue-register:\n");
 522         for (i = 0; i < HISI_DMA_QUEUE_REGION_SIZE; ) {
 523                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 524                 (void)fprintf(f, "      [%2x]: %s", i, buf);
 525                 i += sizeof(uint32_t);
 526                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 527                 (void)fprintf(f, " %s", buf);
 528                 i += sizeof(uint32_t);
 529                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 530                 (void)fprintf(f, " %s", buf);
 531                 i += sizeof(uint32_t);
 532                 hisi_dma_dump_read_queue(hw, i, buf, sizeof(buf));
 533                 (void)fprintf(f, " %s\n", buf);
 534                 i += sizeof(uint32_t);
 535         }
 536 }
 537
 538 static int
 539 hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
 540 {
 541         struct hisi_dma_dev *hw = dev->data->dev_private;
 542
 543         (void)fprintf(f,
 544                 "    revision: 0x%x queue_id: %u ring_size: %u\n"
 545                 "    ridx: %u cridx: %u\n"
 546                 "    sq_head: %u sq_tail: %u cq_sq_head: %u\n"
 547                 "    cq_head: %u cqs_completed: %u cqe_vld: %u\n"
 548                 "    submitted: %" PRIu64 " completed: %" PRIu64 " errors %"
 549                 PRIu64"\n",
 550                 hw->revision, hw->queue_id,
 551                 hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0,
 552                 hw->ridx, hw->cridx,
 553                 hw->sq_head, hw->sq_tail, hw->cq_sq_head,
 554                 hw->cq_head, hw->cqs_completed, hw->cqe_vld,
 555                 hw->submitted, hw->completed, hw->errors);
 556         hisi_dma_dump_queue(hw, f);
 557         hisi_dma_dump_common(hw, f);
 558
 559         return 0;
 560 }
 561
 562 static int
 563 hisi_dma_copy(void *dev_private, uint16_t vchan,
 564                  rte_iova_t src, rte_iova_t dst,
 565                  uint32_t length, uint64_t flags)
 566 {
 567         struct hisi_dma_dev *hw = dev_private;
 568         struct hisi_dma_sqe *sqe = &hw->sqe[hw->sq_tail];
 569
 570         RTE_SET_USED(vchan);
 571
 572         if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head)
 573                 return -ENOSPC;
 574
 575         sqe->dw0 = rte_cpu_to_le_32(SQE_OPCODE_M2M);
 576         sqe->dw1 = 0;
 577         sqe->dw2 = 0;
 578         sqe->length = rte_cpu_to_le_32(length);
 579         sqe->src_addr = rte_cpu_to_le_64(src);
 580         sqe->dst_addr = rte_cpu_to_le_64(dst);
 581         hw->sq_tail = (hw->sq_tail + 1) & hw->sq_depth_mask;
 582         hw->submitted++;
 583
 584         if (flags & RTE_DMA_OP_FLAG_FENCE)
 585                 sqe->dw0 |= rte_cpu_to_le_32(SQE_FENCE_FLAG);
 586         if (flags & RTE_DMA_OP_FLAG_SUBMIT)
 587                 rte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);
 588
 589         return hw->ridx++;
 590 }
 591
 592 static int
 593 hisi_dma_submit(void *dev_private, uint16_t vchan)
 594 {
 595         struct hisi_dma_dev *hw = dev_private;
 596
 597         RTE_SET_USED(vchan);
 598         rte_write32(rte_cpu_to_le_32(hw->sq_tail), hw->sq_tail_reg);
 599
 600         return 0;
 601 }
 602
 603 static inline void
 604 hisi_dma_scan_cq(struct hisi_dma_dev *hw)
 605 {
 606         volatile struct hisi_dma_cqe *cqe;
 607         uint16_t csq_head = hw->cq_sq_head;
 608         uint16_t cq_head = hw->cq_head;
 609         uint16_t count = 0;
 610         uint64_t misc;
 611
 612         while (true) {
 613                 cqe = &hw->cqe[cq_head];
 614                 misc = cqe->misc;
 615                 misc = rte_le_to_cpu_64(misc);
 616                 if (FIELD_GET(CQE_VALID_B, misc) != hw->cqe_vld)
 617                         break;
 618
 619                 csq_head = FIELD_GET(CQE_SQ_HEAD_MASK, misc);
 620                 if (unlikely(misc & CQE_STATUS_MASK))
 621                         hw->status[csq_head] = FIELD_GET(CQE_STATUS_MASK,
 622                                                          misc);
 623
 624                 count++;
 625                 cq_head++;
 626                 if (cq_head == hw->cq_depth) {
 627                         hw->cqe_vld = !hw->cqe_vld;
 628                         cq_head = 0;
 629                 }
 630         }
 631
 632         if (count == 0)
 633                 return;
 634
 635         hw->cq_head = cq_head;
 636         hw->cq_sq_head = (csq_head + 1) & hw->sq_depth_mask;
 637         hw->cqs_completed += count;
 638         if (hw->cqs_completed >= HISI_DMA_CQ_RESERVED) {
 639                 rte_write32(rte_cpu_to_le_32(cq_head), hw->cq_head_reg);
 640                 hw->cqs_completed = 0;
 641         }
 642 }
 643
 644 static inline uint16_t
 645 hisi_dma_calc_cpls(struct hisi_dma_dev *hw, const uint16_t nb_cpls)
 646 {
 647         uint16_t cpl_num;
 648
 649         if (hw->cq_sq_head >= hw->sq_head)
 650                 cpl_num = hw->cq_sq_head - hw->sq_head;
 651         else
 652                 cpl_num = hw->sq_depth_mask + 1 - hw->sq_head + hw->cq_sq_head;
 653
 654         if (cpl_num > nb_cpls)
 655                 cpl_num = nb_cpls;
 656
 657         return cpl_num;
 658 }
 659
 660 static uint16_t
 661 hisi_dma_completed(void *dev_private,
 662                    uint16_t vchan, const uint16_t nb_cpls,
 663                    uint16_t *last_idx, bool *has_error)
 664 {
 665         struct hisi_dma_dev *hw = dev_private;
 666         uint16_t sq_head = hw->sq_head;
 667         uint16_t cpl_num, i;
 668
 669         RTE_SET_USED(vchan);
 670         hisi_dma_scan_cq(hw);
 671
 672         cpl_num = hisi_dma_calc_cpls(hw, nb_cpls);
 673         for (i = 0; i < cpl_num; i++) {
 674                 if (hw->status[sq_head]) {
 675                         *has_error = true;
 676                         break;
 677                 }
 678                 sq_head = (sq_head + 1) & hw->sq_depth_mask;
 679         }
 680         if (i > 0) {
 681                 hw->cridx += i;
 682                 *last_idx = hw->cridx - 1;
 683                 hw->sq_head = sq_head;
 684         }
 685         hw->completed += i;
 686
 687         return i;
 688 }
 689
 690 static enum rte_dma_status_code
 691 hisi_dma_convert_status(uint16_t status)
 692 {
 693         switch (status) {
 694         case HISI_DMA_STATUS_SUCCESS:
 695                 return RTE_DMA_STATUS_SUCCESSFUL;
 696         case HISI_DMA_STATUS_INVALID_OPCODE:
 697                 return RTE_DMA_STATUS_INVALID_OPCODE;
 698         case HISI_DMA_STATUS_INVALID_LENGTH:
 699                 return RTE_DMA_STATUS_INVALID_LENGTH;
 700         case HISI_DMA_STATUS_USER_ABORT:
 701                 return RTE_DMA_STATUS_USER_ABORT;
 702         case HISI_DMA_STATUS_REMOTE_READ_ERROR:
 703         case HISI_DMA_STATUS_AXI_READ_ERROR:
 704                 return RTE_DMA_STATUS_BUS_READ_ERROR;
 705         case HISI_DMA_STATUS_AXI_WRITE_ERROR:
 706                 return RTE_DMA_STATUS_BUS_WRITE_ERROR;
 707         case HISI_DMA_STATUS_DATA_POISON:
 708         case HISI_DMA_STATUS_REMOTE_DATA_POISION:
 709                 return RTE_DMA_STATUS_DATA_POISION;
 710         case HISI_DMA_STATUS_SQE_READ_ERROR:
 711         case HISI_DMA_STATUS_SQE_READ_POISION:
 712                 return RTE_DMA_STATUS_DESCRIPTOR_READ_ERROR;
 713         case HISI_DMA_STATUS_LINK_DOWN_ERROR:
 714                 return RTE_DMA_STATUS_DEV_LINK_ERROR;
 715         default:
 716                 return RTE_DMA_STATUS_ERROR_UNKNOWN;
 717         }
 718 }
 719
 720 static uint16_t
 721 hisi_dma_completed_status(void *dev_private,
 722                           uint16_t vchan, const uint16_t nb_cpls,
 723                           uint16_t *last_idx, enum rte_dma_status_code *status)
 724 {
 725         struct hisi_dma_dev *hw = dev_private;
 726         uint16_t sq_head = hw->sq_head;
 727         uint16_t cpl_num, i;
 728
 729         RTE_SET_USED(vchan);
 730         hisi_dma_scan_cq(hw);
 731
 732         cpl_num = hisi_dma_calc_cpls(hw, nb_cpls);
 733         for (i = 0; i < cpl_num; i++) {
 734                 status[i] = hisi_dma_convert_status(hw->status[sq_head]);
 735                 hw->errors += !!status[i];
 736                 hw->status[sq_head] = HISI_DMA_STATUS_SUCCESS;
 737                 sq_head = (sq_head + 1) & hw->sq_depth_mask;
 738         }
 739         if (likely(cpl_num > 0)) {
 740                 hw->cridx += cpl_num;
 741                 *last_idx = hw->cridx - 1;
 742                 hw->sq_head = sq_head;
 743         }
 744         hw->completed += cpl_num;
 745
 746         return cpl_num;
 747 }
 748
 749 static uint16_t
 750 hisi_dma_burst_capacity(const void *dev_private, uint16_t vchan)
 751 {
 752         const struct hisi_dma_dev *hw = dev_private;
 753         uint16_t sq_head = hw->sq_head;
 754         uint16_t sq_tail = hw->sq_tail;
 755
 756         RTE_SET_USED(vchan);
 757
 758         return (sq_tail >= sq_head) ? hw->sq_depth_mask - sq_tail + sq_head :
 759                                       sq_head - 1 - sq_tail;
 760 }
 761
 762 static void
 763 hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,
 764                              char *name, size_t size)
 765 {
 766         memset(name, 0, size);
 767         (void)snprintf(name, size, "%x:%x.%x",
 768                  pci_dev->addr.bus, pci_dev->addr.devid,
 769                  pci_dev->addr.function);
 770 }
 771
 772 static void
 773 hisi_dma_gen_dev_name(const struct rte_pci_device *pci_dev,
 774                       uint8_t queue_id, char *name, size_t size)
 775 {
 776         memset(name, 0, size);
 777         (void)snprintf(name, size, "%x:%x.%x-ch%u",
 778                  pci_dev->addr.bus, pci_dev->addr.devid,
 779                  pci_dev->addr.function, queue_id);
 780 }
 781
 782 /**
 783  * Hardware queue state machine:
 784  *
 785  *   -----------  dmadev_create   ------------------
 786  *   | Unknown | ---------------> |      IDLE      |
 787  *   -----------                  ------------------
 788  *                                   ^          |
 789  *                                   |          |dev_start
 790  *                           dev_stop|          |
 791  *                                   |          v
 792  *                                ------------------
 793  *                                |      RUN       |
 794  *                                ------------------
 795  *
 796  */
 797 static const struct rte_dma_dev_ops hisi_dmadev_ops = {
 798         .dev_info_get     = hisi_dma_info_get,
 799         .dev_configure    = hisi_dma_configure,
 800         .dev_start        = hisi_dma_start,
 801         .dev_stop         = hisi_dma_stop,
 802         .dev_close        = hisi_dma_close,
 803         .vchan_setup      = hisi_dma_vchan_setup,
 804         .stats_get        = hisi_dma_stats_get,
 805         .stats_reset      = hisi_dma_stats_reset,
 806         .dev_dump         = hisi_dma_dump,
 807 };
 808
 809 static int
 810 hisi_dma_create(struct rte_pci_device *pci_dev, uint8_t queue_id,
 811                 uint8_t revision)
 812 {
 813 #define REG_PCI_BAR_INDEX       2
 814
 815         char name[RTE_DEV_NAME_MAX_LEN];
 816         struct rte_dma_dev *dev;
 817         struct hisi_dma_dev *hw;
 818         int ret;
 819
 820         hisi_dma_gen_dev_name(pci_dev, queue_id, name, sizeof(name));
 821         dev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
 822                                    sizeof(*hw));
 823         if (dev == NULL) {
 824                 HISI_DMA_LOG(ERR, "%s allocate dmadev fail!", name);
 825                 return -EINVAL;
 826         }
 827
 828         dev->device = &pci_dev->device;
 829         dev->dev_ops = &hisi_dmadev_ops;
 830         dev->fp_obj->dev_private = dev->data->dev_private;
 831         dev->fp_obj->copy = hisi_dma_copy;
 832         dev->fp_obj->submit = hisi_dma_submit;
 833         dev->fp_obj->completed = hisi_dma_completed;
 834         dev->fp_obj->completed_status = hisi_dma_completed_status;
 835         dev->fp_obj->burst_capacity = hisi_dma_burst_capacity;
 836
 837         hw = dev->data->dev_private;
 838         hw->data = dev->data;
 839         hw->revision = revision;
 840         hw->reg_layout = hisi_dma_reg_layout(revision);
 841         hw->io_base = pci_dev->mem_resource[REG_PCI_BAR_INDEX].addr;
 842         hw->queue_id = queue_id;
 843         hw->sq_tail_reg = hisi_dma_queue_regaddr(hw,
 844                                                  HISI_DMA_QUEUE_SQ_TAIL_REG);
 845         hw->cq_head_reg = hisi_dma_queue_regaddr(hw,
 846                                                  HISI_DMA_QUEUE_CQ_HEAD_REG);
 847
 848         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 849                 ret = hisi_dma_reset_hw(hw);
 850                 if (ret) {
 851                         HISI_DMA_LOG(ERR, "%s init device fail!", name);
 852                         (void)rte_dma_pmd_release(name);
 853                         return -EIO;
 854                 }
 855         }
 856
 857         dev->state = RTE_DMA_DEV_READY;
 858         HISI_DMA_LOG(DEBUG, "%s create dmadev success!", name);
 859
 860         return 0;
 861 }
 862
 863 static int
 864 hisi_dma_check_revision(struct rte_pci_device *pci_dev, const char *name,
 865                         uint8_t *out_revision)
 866 {
 867         uint8_t revision;
 868         int ret;
 869
 870         ret = rte_pci_read_config(pci_dev, &revision, 1,
 871                                   HISI_DMA_PCI_REVISION_ID_REG);
 872         if (ret != 1) {
 873                 HISI_DMA_LOG(ERR, "%s read PCI revision failed!", name);
 874                 return -EINVAL;
 875         }
 876         if (hisi_dma_reg_layout(revision) == HISI_DMA_REG_LAYOUT_INVALID) {
 877                 HISI_DMA_LOG(ERR, "%s revision: 0x%x not supported!",
 878                              name, revision);
 879                 return -EINVAL;
 880         }
 881
 882         *out_revision = revision;
 883         return 0;
 884 }
 885
 886 static int
 887 hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
 888                struct rte_pci_device *pci_dev)
 889 {
 890         char name[RTE_DEV_NAME_MAX_LEN] = { 0 };
 891         uint8_t revision;
 892         uint8_t i;
 893         int ret;
 894
 895         hisi_dma_gen_pci_device_name(pci_dev, name, sizeof(name));
 896
 897         if (pci_dev->mem_resource[2].addr == NULL) {
 898                 HISI_DMA_LOG(ERR, "%s BAR2 is NULL!\n", name);
 899                 return -ENODEV;
 900         }
 901
 902         ret = hisi_dma_check_revision(pci_dev, name, &revision);
 903         if (ret)
 904                 return ret;
 905         HISI_DMA_LOG(DEBUG, "%s read PCI revision: 0x%x", name, revision);
 906
 907         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 908                 hisi_dma_init_gbl(pci_dev->mem_resource[2].addr, revision);
 909
 910         for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
 911                 ret = hisi_dma_create(pci_dev, i, revision);
 912                 if (ret) {
 913                         HISI_DMA_LOG(ERR, "%s create dmadev %u failed!",
 914                                      name, i);
 915                         break;
 916                 }
 917         }
 918
 919         return ret;
 920 }
 921
 922 static int
 923 hisi_dma_remove(struct rte_pci_device *pci_dev)
 924 {
 925         char name[RTE_DEV_NAME_MAX_LEN];
 926         uint8_t i;
 927         int ret;
 928
 929         for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
 930                 hisi_dma_gen_dev_name(pci_dev, i, name, sizeof(name));
 931                 ret = rte_dma_pmd_release(name);
 932                 if (ret)
 933                         return ret;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static const struct rte_pci_id pci_id_hisi_dma_map[] = {
 940         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HISI_DMA_DEVICE_ID) },
 941         { .vendor_id = 0, }, /* sentinel */
 942 };
 943
 944 static struct rte_pci_driver hisi_dma_pmd_drv = {
 945         .id_table  = pci_id_hisi_dma_map,
 946         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 947         .probe     = hisi_dma_probe,
 948         .remove    = hisi_dma_remove,
 949 };
 950
 951 RTE_PMD_REGISTER_PCI(dma_hisilicon, hisi_dma_pmd_drv);
 952 RTE_PMD_REGISTER_PCI_TABLE(dma_hisilicon, pci_id_hisi_dma_map);
 953 RTE_PMD_REGISTER_KMOD_DEP(dma_hisilicon, "vfio-pci");