drivers/dma/hisilicon/hisi_dmadev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2021 HiSilicon Limited
   3  */
   4
   5 #ifndef HISI_DMADEV_H
   6 #define HISI_DMADEV_H
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10
  11 #define BIT(x)  (1ul << (x))
  12 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  13 #define GENMASK(h, l) \
  14                 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
  15 #define BF_SHF(x) (__builtin_ffsll(x) - 1)
  16 #define FIELD_GET(mask, reg) \
  17                 ((typeof(mask))(((reg) & (mask)) >> BF_SHF(mask)))
  18
  19 #define PCI_VENDOR_ID_HUAWEI                    0x19e5
  20 #define HISI_DMA_DEVICE_ID                      0xA122
  21 #define HISI_DMA_PCI_REVISION_ID_REG            0x08
  22 #define HISI_DMA_REVISION_HIP08B                0x21
  23
  24 #define HISI_DMA_MAX_HW_QUEUES                  4
  25
  26 /**
  27  * The HIP08B(HiSilicon IP08) and later Chip(e.g. HiSilicon IP09) are DMA iEPs,
  28  * they have the same pci device id but with different pci revision.
  29  * Unfortunately, they have different register layouts, so the layout
  30  * enumerations are defined.
  31  */
  32 enum {
  33         HISI_DMA_REG_LAYOUT_INVALID = 0,
  34         HISI_DMA_REG_LAYOUT_HIP08
  35 };
  36
  37 /**
  38  * Hardware PCI bar register MAP:
  39  *
  40  *     --------------
  41  *     | Misc-reg-0 |
  42  *     |            |
  43  *     --------------   -> Queue base
  44  *     |            |
  45  *     | Queue-0    |
  46  *     |            |
  47  *     --------------   ---
  48  *     |            |    ^
  49  *     | Queue-1    |   Queue region
  50  *     |            |    v
  51  *     --------------   ---
  52  *     | ...        |
  53  *     | Queue-x    |
  54  *     | ...        |
  55  *     --------------
  56  *     | Misc-reg-1 |
  57  *     --------------
  58  *
  59  * As described above, a single queue register is continuous and occupies the
  60  * length of queue-region. The global offset for a single queue register is
  61  * calculated by:
  62  *     offset = queue-base + (queue-id * queue-region) + reg-offset-in-region.
  63  *
  64  * The first part of queue region is basically the same for HIP08 and later chip
  65  * register layouts, therefore, HISI_QUEUE_* registers are defined for it.
  66  */
  67 #define HISI_DMA_QUEUE_SQ_BASE_L_REG            0x0
  68 #define HISI_DMA_QUEUE_SQ_BASE_H_REG            0x4
  69 #define HISI_DMA_QUEUE_SQ_DEPTH_REG             0x8
  70 #define HISI_DMA_QUEUE_SQ_TAIL_REG              0xC
  71 #define HISI_DMA_QUEUE_CQ_BASE_L_REG            0x10
  72 #define HISI_DMA_QUEUE_CQ_BASE_H_REG            0x14
  73 #define HISI_DMA_QUEUE_CQ_DEPTH_REG             0x18
  74 #define HISI_DMA_QUEUE_CQ_HEAD_REG              0x1C
  75 #define HISI_DMA_QUEUE_CTRL0_REG                0x20
  76 #define HISI_DMA_QUEUE_CTRL0_EN_B               0
  77 #define HISI_DMA_QUEUE_CTRL0_PAUSE_B            4
  78 #define HISI_DMA_QUEUE_CTRL1_REG                0x24
  79 #define HISI_DMA_QUEUE_CTRL1_RESET_B            0
  80 #define HISI_DMA_QUEUE_FSM_REG                  0x30
  81 #define HISI_DMA_QUEUE_FSM_STS_M                GENMASK(3, 0)
  82 #define HISI_DMA_QUEUE_INT_STATUS_REG           0x40
  83 #define HISI_DMA_QUEUE_ERR_INT_NUM0_REG         0x84
  84 #define HISI_DMA_QUEUE_ERR_INT_NUM1_REG         0x88
  85 #define HISI_DMA_QUEUE_ERR_INT_NUM2_REG         0x8C
  86 #define HISI_DMA_QUEUE_REGION_SIZE              0x100
  87
  88 /**
  89  * HiSilicon IP08 DMA register and field define:
  90  */
  91 #define HISI_DMA_HIP08_QUEUE_BASE                       0x0
  92 #define HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B          2
  93 #define HISI_DMA_HIP08_QUEUE_INT_MASK_REG               0x44
  94 #define HISI_DMA_HIP08_QUEUE_INT_MASK_M                 GENMASK(14, 0)
  95 #define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG           0x90
  96 #define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM4_REG           0x94
  97 #define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM5_REG           0x98
  98 #define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM6_REG           0x48
  99 #define HISI_DMA_HIP08_MODE_REG                         0x217C
 100 #define HISI_DMA_HIP08_MODE_SEL_B                       0
 101 #define HISI_DMA_HIP08_DUMP_START_REG                   0x2000
 102 #define HISI_DMA_HIP08_DUMP_END_REG                     0x2280
 103
 104 /**
 105  * In fact, there are multiple states, but it need to pay attention to
 106  * the following two states for the driver:
 107  */
 108 enum {
 109         HISI_DMA_STATE_IDLE = 0,
 110         HISI_DMA_STATE_RUN,
 111 };
 112
 113 struct hisi_dma_dev {
 114         struct rte_dma_dev_data *data;
 115         uint8_t revision; /**< PCI revision. */
 116         uint8_t reg_layout; /**< hardware register layout. */
 117         void *io_base;
 118         uint8_t queue_id; /**< hardware DMA queue index. */
 119 };
 120
 121 #endif /* HISI_DMADEV_H */