drivers/dma/ioat/ioat_hw_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2021 Intel Corporation
   3  */
   4
   5 #ifndef IOAT_HW_DEFS_H
   6 #define IOAT_HW_DEFS_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #include <stdint.h>
  13
  14 #define IOAT_PCI_CHANERR_INT_OFFSET     0x180
  15
  16 #define IOAT_VER_3_0    0x30
  17 #define IOAT_VER_3_3    0x33
  18 #define IOAT_VER_3_4    0x34
  19
  20 #define IOAT_VENDOR_ID          0x8086
  21 #define IOAT_DEVICE_ID_SKX      0x2021
  22 #define IOAT_DEVICE_ID_BDX0     0x6f20
  23 #define IOAT_DEVICE_ID_BDX1     0x6f21
  24 #define IOAT_DEVICE_ID_BDX2     0x6f22
  25 #define IOAT_DEVICE_ID_BDX3     0x6f23
  26 #define IOAT_DEVICE_ID_BDX4     0x6f24
  27 #define IOAT_DEVICE_ID_BDX5     0x6f25
  28 #define IOAT_DEVICE_ID_BDX6     0x6f26
  29 #define IOAT_DEVICE_ID_BDX7     0x6f27
  30 #define IOAT_DEVICE_ID_BDXE     0x6f2E
  31 #define IOAT_DEVICE_ID_BDXF     0x6f2F
  32 #define IOAT_DEVICE_ID_ICX      0x0b00
  33
  34 #define IOAT_COMP_UPDATE_SHIFT  3
  35 #define IOAT_CMD_OP_SHIFT       24
  36
  37 /* DMA Channel Registers */
  38 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK             0xF000
  39 #define IOAT_CHANCTRL_COMPL_DCA_EN                      0x0200
  40 #define IOAT_CHANCTRL_CHANNEL_IN_USE                    0x0100
  41 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL     0x0020
  42 #define IOAT_CHANCTRL_ERR_INT_EN                        0x0010
  43 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN                  0x0008
  44 #define IOAT_CHANCTRL_ERR_COMPLETION_EN                 0x0004
  45 #define IOAT_CHANCTRL_INT_REARM                         0x0001
  46
  47 /* DMA Channel Capabilities */
  48 #define IOAT_DMACAP_PB          (1 << 0)
  49 #define IOAT_DMACAP_DCA         (1 << 4)
  50 #define IOAT_DMACAP_BFILL       (1 << 6)
  51 #define IOAT_DMACAP_XOR         (1 << 8)
  52 #define IOAT_DMACAP_PQ          (1 << 9)
  53 #define IOAT_DMACAP_DMA_DIF     (1 << 10)
  54
  55 struct ioat_registers {
  56         uint8_t         chancnt;
  57         uint8_t         xfercap;
  58         uint8_t         genctrl;
  59         uint8_t         intrctrl;
  60         uint32_t        attnstatus;
  61         uint8_t         cbver;          /* 0x08 */
  62         uint8_t         reserved4[0x3]; /* 0x09 */
  63         uint16_t        intrdelay;      /* 0x0C */
  64         uint16_t        cs_status;      /* 0x0E */
  65         uint32_t        dmacapability;  /* 0x10 */
  66         uint8_t         reserved5[0x6C]; /* 0x14 */
  67         uint16_t        chanctrl;       /* 0x80 */
  68         uint8_t         reserved6[0x2]; /* 0x82 */
  69         uint8_t         chancmd;        /* 0x84 */
  70         uint8_t         reserved3[1];   /* 0x85 */
  71         uint16_t        dmacount;       /* 0x86 */
  72         uint64_t        chansts;        /* 0x88 */
  73         uint64_t        chainaddr;      /* 0x90 */
  74         uint64_t        chancmp;        /* 0x98 */
  75         uint8_t         reserved2[0x8]; /* 0xA0 */
  76         uint32_t        chanerr;        /* 0xA8 */
  77         uint32_t        chanerrmask;    /* 0xAC */
  78 } __rte_packed;
  79
  80 #define IOAT_CHANCMD_RESET      0x20
  81 #define IOAT_CHANCMD_SUSPEND    0x04
  82
  83 #define IOAT_CHANSTS_STATUS     0x7ULL
  84 #define IOAT_CHANSTS_ACTIVE     0x0
  85 #define IOAT_CHANSTS_IDLE       0x1
  86 #define IOAT_CHANSTS_SUSPENDED  0x2
  87 #define IOAT_CHANSTS_HALTED     0x3
  88 #define IOAT_CHANSTS_ARMED      0x4
  89
  90 #define IOAT_CHANERR_INVALID_SRC_ADDR_MASK              (1 << 0)
  91 #define IOAT_CHANERR_INVALID_DST_ADDR_MASK              (1 << 1)
  92 #define IOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK         (1 << 8)
  93 #define IOAT_CHANERR_INVALID_LENGTH_MASK                (1 << 10)
  94
  95 const char *chansts_readable[] = {
  96         "ACTIVE",       /* 0x0 */
  97         "IDLE",         /* 0x1 */
  98         "SUSPENDED",    /* 0x2 */
  99         "HALTED",       /* 0x3 */
 100         "ARMED"         /* 0x4 */
 101 };
 102
 103 #define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
 104 #define IOAT_CHANSTS_SOFT_ERROR         0x10ULL
 105
 106 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK  (~0x3FULL)
 107
 108 #define IOAT_CHANCMP_ALIGN      8 /* CHANCMP address must be 64-bit aligned */
 109
 110 struct ioat_dma_hw_desc {
 111         uint32_t size;
 112         union {
 113                 uint32_t control_raw;
 114                 struct {
 115                         uint32_t int_enable: 1;
 116                         uint32_t src_snoop_disable: 1;
 117                         uint32_t dest_snoop_disable: 1;
 118                         uint32_t completion_update: 1;
 119                         uint32_t fence: 1;
 120                         uint32_t null: 1;
 121                         uint32_t src_page_break: 1;
 122                         uint32_t dest_page_break: 1;
 123                         uint32_t bundle: 1;
 124                         uint32_t dest_dca: 1;
 125                         uint32_t hint: 1;
 126                         uint32_t reserved: 13;
 127 #define IOAT_OP_COPY 0x00
 128                         uint32_t op: 8;
 129                 } control;
 130         } u;
 131         uint64_t src_addr;
 132         uint64_t dest_addr;
 133         uint64_t next;
 134         uint64_t reserved;
 135         uint64_t reserved2;
 136         uint64_t user1;
 137         uint64_t user2;
 138 };
 139
 140 struct ioat_fill_hw_desc {
 141         uint32_t size;
 142         union {
 143                 uint32_t control_raw;
 144                 struct {
 145                         uint32_t int_enable: 1;
 146                         uint32_t reserved: 1;
 147                         uint32_t dest_snoop_disable: 1;
 148                         uint32_t completion_update: 1;
 149                         uint32_t fence: 1;
 150                         uint32_t reserved2: 2;
 151                         uint32_t dest_page_break: 1;
 152                         uint32_t bundle: 1;
 153                         uint32_t reserved3: 15;
 154 #define IOAT_OP_FILL 0x01
 155                         uint32_t op: 8;
 156                 } control;
 157         } u;
 158         uint64_t src_data;
 159         uint64_t dest_addr;
 160         uint64_t next;
 161         uint64_t reserved;
 162         uint64_t next_dest_addr;
 163         uint64_t user1;
 164         uint64_t user2;
 165 };
 166
 167 struct ioat_xor_hw_desc {
 168         uint32_t size;
 169         union {
 170                 uint32_t control_raw;
 171                 struct {
 172                         uint32_t int_enable: 1;
 173                         uint32_t src_snoop_disable: 1;
 174                         uint32_t dest_snoop_disable: 1;
 175                         uint32_t completion_update: 1;
 176                         uint32_t fence: 1;
 177                         uint32_t src_count: 3;
 178                         uint32_t bundle: 1;
 179                         uint32_t dest_dca: 1;
 180                         uint32_t hint: 1;
 181                         uint32_t reserved: 13;
 182 #define IOAT_OP_XOR 0x87
 183 #define IOAT_OP_XOR_VAL 0x88
 184                         uint32_t op: 8;
 185                 } control;
 186         } u;
 187         uint64_t src_addr;
 188         uint64_t dest_addr;
 189         uint64_t next;
 190         uint64_t src_addr2;
 191         uint64_t src_addr3;
 192         uint64_t src_addr4;
 193         uint64_t src_addr5;
 194 };
 195
 196 struct ioat_xor_ext_hw_desc {
 197         uint64_t src_addr6;
 198         uint64_t src_addr7;
 199         uint64_t src_addr8;
 200         uint64_t next;
 201         uint64_t reserved[4];
 202 };
 203
 204 struct ioat_pq_hw_desc {
 205         uint32_t size;
 206         union {
 207                 uint32_t control_raw;
 208                 struct {
 209                         uint32_t int_enable: 1;
 210                         uint32_t src_snoop_disable: 1;
 211                         uint32_t dest_snoop_disable: 1;
 212                         uint32_t completion_update: 1;
 213                         uint32_t fence: 1;
 214                         uint32_t src_count: 3;
 215                         uint32_t bundle: 1;
 216                         uint32_t dest_dca: 1;
 217                         uint32_t hint: 1;
 218                         uint32_t p_disable: 1;
 219                         uint32_t q_disable: 1;
 220                         uint32_t reserved: 11;
 221 #define IOAT_OP_PQ 0x89
 222 #define IOAT_OP_PQ_VAL 0x8a
 223                         uint32_t op: 8;
 224                 } control;
 225         } u;
 226         uint64_t src_addr;
 227         uint64_t p_addr;
 228         uint64_t next;
 229         uint64_t src_addr2;
 230         uint64_t src_addr3;
 231         uint8_t  coef[8];
 232         uint64_t q_addr;
 233 };
 234
 235 struct ioat_pq_ext_hw_desc {
 236         uint64_t src_addr4;
 237         uint64_t src_addr5;
 238         uint64_t src_addr6;
 239         uint64_t next;
 240         uint64_t src_addr7;
 241         uint64_t src_addr8;
 242         uint64_t reserved[2];
 243 };
 244
 245 struct ioat_pq_update_hw_desc {
 246         uint32_t size;
 247         union {
 248                 uint32_t control_raw;
 249                 struct {
 250                         uint32_t int_enable: 1;
 251                         uint32_t src_snoop_disable: 1;
 252                         uint32_t dest_snoop_disable: 1;
 253                         uint32_t completion_update: 1;
 254                         uint32_t fence: 1;
 255                         uint32_t src_cnt: 3;
 256                         uint32_t bundle: 1;
 257                         uint32_t dest_dca: 1;
 258                         uint32_t hint: 1;
 259                         uint32_t p_disable: 1;
 260                         uint32_t q_disable: 1;
 261                         uint32_t reserved: 3;
 262                         uint32_t coef: 8;
 263 #define IOAT_OP_PQ_UP 0x8b
 264                         uint32_t op: 8;
 265                 } control;
 266         } u;
 267         uint64_t src_addr;
 268         uint64_t p_addr;
 269         uint64_t next;
 270         uint64_t src_addr2;
 271         uint64_t p_src;
 272         uint64_t q_src;
 273         uint64_t q_addr;
 274 };
 275
 276 union ioat_hw_desc {
 277         struct ioat_dma_hw_desc dma;
 278         struct ioat_fill_hw_desc fill;
 279         struct ioat_xor_hw_desc xor_desc;
 280         struct ioat_xor_ext_hw_desc xor_ext;
 281         struct ioat_pq_hw_desc pq;
 282         struct ioat_pq_ext_hw_desc pq_ext;
 283         struct ioat_pq_update_hw_desc pq_update;
 284 };
 285
 286 #define GENSTS_DEV_STATE_MASK 0x03
 287 #define CMDSTATUS_ACTIVE_SHIFT 31
 288 #define CMDSTATUS_ACTIVE_MASK (1 << 31)
 289 #define CMDSTATUS_ERR_MASK 0xFF
 290
 291 #ifdef __cplusplus
 292 }
 293 #endif
 294
 295 #endif /* IOAT_HW_DEFS_H */