drivers/dma/ioat/ioat_hw_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2021 Intel Corporation
   3  */
   4
   5 #ifndef IOAT_HW_DEFS_H
   6 #define IOAT_HW_DEFS_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #include <stdint.h>
  13
  14 #define IOAT_PCI_CHANERR_INT_OFFSET     0x180
  15
  16 #define IOAT_VER_3_0    0x30
  17 #define IOAT_VER_3_3    0x33
  18
  19 #define IOAT_VENDOR_ID          0x8086
  20 #define IOAT_DEVICE_ID_SKX      0x2021
  21 #define IOAT_DEVICE_ID_BDX0     0x6f20
  22 #define IOAT_DEVICE_ID_BDX1     0x6f21
  23 #define IOAT_DEVICE_ID_BDX2     0x6f22
  24 #define IOAT_DEVICE_ID_BDX3     0x6f23
  25 #define IOAT_DEVICE_ID_BDX4     0x6f24
  26 #define IOAT_DEVICE_ID_BDX5     0x6f25
  27 #define IOAT_DEVICE_ID_BDX6     0x6f26
  28 #define IOAT_DEVICE_ID_BDX7     0x6f27
  29 #define IOAT_DEVICE_ID_BDXE     0x6f2E
  30 #define IOAT_DEVICE_ID_BDXF     0x6f2F
  31 #define IOAT_DEVICE_ID_ICX      0x0b00
  32
  33 #define IOAT_COMP_UPDATE_SHIFT  3
  34 #define IOAT_CMD_OP_SHIFT       24
  35
  36 /* DMA Channel Registers */
  37 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK             0xF000
  38 #define IOAT_CHANCTRL_COMPL_DCA_EN                      0x0200
  39 #define IOAT_CHANCTRL_CHANNEL_IN_USE                    0x0100
  40 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL     0x0020
  41 #define IOAT_CHANCTRL_ERR_INT_EN                        0x0010
  42 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN                  0x0008
  43 #define IOAT_CHANCTRL_ERR_COMPLETION_EN                 0x0004
  44 #define IOAT_CHANCTRL_INT_REARM                         0x0001
  45
  46 struct ioat_registers {
  47         uint8_t         chancnt;
  48         uint8_t         xfercap;
  49         uint8_t         genctrl;
  50         uint8_t         intrctrl;
  51         uint32_t        attnstatus;
  52         uint8_t         cbver;          /* 0x08 */
  53         uint8_t         reserved4[0x3]; /* 0x09 */
  54         uint16_t        intrdelay;      /* 0x0C */
  55         uint16_t        cs_status;      /* 0x0E */
  56         uint32_t        dmacapability;  /* 0x10 */
  57         uint8_t         reserved5[0x6C]; /* 0x14 */
  58         uint16_t        chanctrl;       /* 0x80 */
  59         uint8_t         reserved6[0x2]; /* 0x82 */
  60         uint8_t         chancmd;        /* 0x84 */
  61         uint8_t         reserved3[1];   /* 0x85 */
  62         uint16_t        dmacount;       /* 0x86 */
  63         uint64_t        chansts;        /* 0x88 */
  64         uint64_t        chainaddr;      /* 0x90 */
  65         uint64_t        chancmp;        /* 0x98 */
  66         uint8_t         reserved2[0x8]; /* 0xA0 */
  67         uint32_t        chanerr;        /* 0xA8 */
  68         uint32_t        chanerrmask;    /* 0xAC */
  69 } __rte_packed;
  70
  71 #define IOAT_CHANCMD_RESET      0x20
  72 #define IOAT_CHANCMD_SUSPEND    0x04
  73
  74 #define IOAT_CHANCMP_ALIGN      8 /* CHANCMP address must be 64-bit aligned */
  75
  76 #ifdef __cplusplus
  77 }
  78 #endif
  79
  80 #endif /* IOAT_HW_DEFS_H */