1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2021 Intel Corporation
14 #define IOAT_PCI_CHANERR_INT_OFFSET 0x180
16 #define IOAT_VER_3_0 0x30
17 #define IOAT_VER_3_3 0x33
18 #define IOAT_VER_3_4 0x34
20 #define IOAT_VENDOR_ID 0x8086
21 #define IOAT_DEVICE_ID_SKX 0x2021
22 #define IOAT_DEVICE_ID_BDX0 0x6f20
23 #define IOAT_DEVICE_ID_BDX1 0x6f21
24 #define IOAT_DEVICE_ID_BDX2 0x6f22
25 #define IOAT_DEVICE_ID_BDX3 0x6f23
26 #define IOAT_DEVICE_ID_BDX4 0x6f24
27 #define IOAT_DEVICE_ID_BDX5 0x6f25
28 #define IOAT_DEVICE_ID_BDX6 0x6f26
29 #define IOAT_DEVICE_ID_BDX7 0x6f27
30 #define IOAT_DEVICE_ID_BDXE 0x6f2E
31 #define IOAT_DEVICE_ID_BDXF 0x6f2F
32 #define IOAT_DEVICE_ID_ICX 0x0b00
34 #define IOAT_COMP_UPDATE_SHIFT 3
35 #define IOAT_CMD_OP_SHIFT 24
37 /* DMA Channel Registers */
38 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
39 #define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
40 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
41 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
42 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010
43 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
44 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
45 #define IOAT_CHANCTRL_INT_REARM 0x0001
47 /* DMA Channel Capabilities */
48 #define IOAT_DMACAP_PB (1 << 0)
49 #define IOAT_DMACAP_DCA (1 << 4)
50 #define IOAT_DMACAP_BFILL (1 << 6)
51 #define IOAT_DMACAP_XOR (1 << 8)
52 #define IOAT_DMACAP_PQ (1 << 9)
53 #define IOAT_DMACAP_DMA_DIF (1 << 10)
55 struct ioat_registers {
61 uint8_t cbver; /* 0x08 */
62 uint8_t reserved4[0x3]; /* 0x09 */
63 uint16_t intrdelay; /* 0x0C */
64 uint16_t cs_status; /* 0x0E */
65 uint32_t dmacapability; /* 0x10 */
66 uint8_t reserved5[0x6C]; /* 0x14 */
67 uint16_t chanctrl; /* 0x80 */
68 uint8_t reserved6[0x2]; /* 0x82 */
69 uint8_t chancmd; /* 0x84 */
70 uint8_t reserved3[1]; /* 0x85 */
71 uint16_t dmacount; /* 0x86 */
72 uint64_t chansts; /* 0x88 */
73 uint64_t chainaddr; /* 0x90 */
74 uint64_t chancmp; /* 0x98 */
75 uint8_t reserved2[0x8]; /* 0xA0 */
76 uint32_t chanerr; /* 0xA8 */
77 uint32_t chanerrmask; /* 0xAC */
80 #define IOAT_CHANCMD_RESET 0x20
81 #define IOAT_CHANCMD_SUSPEND 0x04
83 #define IOAT_CHANSTS_STATUS 0x7ULL
84 #define IOAT_CHANSTS_ACTIVE 0x0
85 #define IOAT_CHANSTS_IDLE 0x1
86 #define IOAT_CHANSTS_SUSPENDED 0x2
87 #define IOAT_CHANSTS_HALTED 0x3
88 #define IOAT_CHANSTS_ARMED 0x4
90 #define IOAT_CHANERR_INVALID_SRC_ADDR_MASK (1 << 0)
91 #define IOAT_CHANERR_INVALID_DST_ADDR_MASK (1 << 1)
92 #define IOAT_CHANERR_DESCRIPTOR_READ_ERROR_MASK (1 << 8)
93 #define IOAT_CHANERR_INVALID_LENGTH_MASK (1 << 10)
95 const char *chansts_readable[] = {
98 "SUSPENDED", /* 0x2 */
103 #define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
104 #define IOAT_CHANSTS_SOFT_ERROR 0x10ULL
106 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL)
108 #define IOAT_CHANCMP_ALIGN 8 /* CHANCMP address must be 64-bit aligned */
110 struct ioat_dma_hw_desc {
113 uint32_t control_raw;
115 uint32_t int_enable: 1;
116 uint32_t src_snoop_disable: 1;
117 uint32_t dest_snoop_disable: 1;
118 uint32_t completion_update: 1;
121 uint32_t src_page_break: 1;
122 uint32_t dest_page_break: 1;
124 uint32_t dest_dca: 1;
126 uint32_t reserved: 13;
127 #define IOAT_OP_COPY 0x00
140 struct ioat_fill_hw_desc {
143 uint32_t control_raw;
145 uint32_t int_enable: 1;
146 uint32_t reserved: 1;
147 uint32_t dest_snoop_disable: 1;
148 uint32_t completion_update: 1;
150 uint32_t reserved2: 2;
151 uint32_t dest_page_break: 1;
153 uint32_t reserved3: 15;
154 #define IOAT_OP_FILL 0x01
162 uint64_t next_dest_addr;
167 struct ioat_xor_hw_desc {
170 uint32_t control_raw;
172 uint32_t int_enable: 1;
173 uint32_t src_snoop_disable: 1;
174 uint32_t dest_snoop_disable: 1;
175 uint32_t completion_update: 1;
177 uint32_t src_count: 3;
179 uint32_t dest_dca: 1;
181 uint32_t reserved: 13;
182 #define IOAT_OP_XOR 0x87
183 #define IOAT_OP_XOR_VAL 0x88
196 struct ioat_xor_ext_hw_desc {
201 uint64_t reserved[4];
204 struct ioat_pq_hw_desc {
207 uint32_t control_raw;
209 uint32_t int_enable: 1;
210 uint32_t src_snoop_disable: 1;
211 uint32_t dest_snoop_disable: 1;
212 uint32_t completion_update: 1;
214 uint32_t src_count: 3;
216 uint32_t dest_dca: 1;
218 uint32_t p_disable: 1;
219 uint32_t q_disable: 1;
220 uint32_t reserved: 11;
221 #define IOAT_OP_PQ 0x89
222 #define IOAT_OP_PQ_VAL 0x8a
235 struct ioat_pq_ext_hw_desc {
242 uint64_t reserved[2];
245 struct ioat_pq_update_hw_desc {
248 uint32_t control_raw;
250 uint32_t int_enable: 1;
251 uint32_t src_snoop_disable: 1;
252 uint32_t dest_snoop_disable: 1;
253 uint32_t completion_update: 1;
257 uint32_t dest_dca: 1;
259 uint32_t p_disable: 1;
260 uint32_t q_disable: 1;
261 uint32_t reserved: 3;
263 #define IOAT_OP_PQ_UP 0x8b
277 struct ioat_dma_hw_desc dma;
278 struct ioat_fill_hw_desc fill;
279 struct ioat_xor_hw_desc xor_desc;
280 struct ioat_xor_ext_hw_desc xor_ext;
281 struct ioat_pq_hw_desc pq;
282 struct ioat_pq_ext_hw_desc pq_ext;
283 struct ioat_pq_update_hw_desc pq_update;
286 #define GENSTS_DEV_STATE_MASK 0x03
287 #define CMDSTATUS_ACTIVE_SHIFT 31
288 #define CMDSTATUS_ACTIVE_MASK (1 << 31)
289 #define CMDSTATUS_ERR_MASK 0xFF
295 #endif /* IOAT_HW_DEFS_H */