drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 static uint32_t
  10 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  11 {
  12         uint32_t wdata = BIT(16) | 1;
  13
  14         switch (dev->gw_mode) {
  15         case CN10K_GW_MODE_NONE:
  16         default:
  17                 break;
  18         case CN10K_GW_MODE_PREF:
  19                 wdata |= BIT(19);
  20                 break;
  21         case CN10K_GW_MODE_PREF_WFE:
  22                 wdata |= BIT(20) | BIT(19);
  23                 break;
  24         }
  25
  26         return wdata;
  27 }
  28
  29 static void *
  30 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  31 {
  32         struct cnxk_sso_evdev *dev = arg;
  33         struct cn10k_sso_hws *ws;
  34
  35         /* Allocate event port memory */
  36         ws = rte_zmalloc("cn10k_ws",
  37                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  38                          RTE_CACHE_LINE_SIZE);
  39         if (ws == NULL) {
  40                 plt_err("Failed to alloc memory for port=%d", port_id);
  41                 return NULL;
  42         }
  43
  44         /* First cache line is reserved for cookie */
  45         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  46         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  47         ws->hws_id = port_id;
  48         ws->swtag_req = 0;
  49         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  50         ws->lmt_base = dev->sso.lmt_base;
  51
  52         return ws;
  53 }
  54
  55 static int
  56 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  57 {
  58         struct cnxk_sso_evdev *dev = arg;
  59         struct cn10k_sso_hws *ws = port;
  60
  61         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  62 }
  63
  64 static int
  65 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  66 {
  67         struct cnxk_sso_evdev *dev = arg;
  68         struct cn10k_sso_hws *ws = port;
  69
  70         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  71 }
  72
  73 static void
  74 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
  75 {
  76         struct cnxk_sso_evdev *dev = arg;
  77         struct cn10k_sso_hws *ws = hws;
  78         uint64_t val;
  79
  80         rte_memcpy(ws->grps_base, grps_base,
  81                    sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
  82         ws->fc_mem = dev->fc_mem;
  83         ws->xaq_lmt = dev->xaq_lmt;
  84
  85         /* Set get_work timeout for HWS */
  86         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
  87         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  88 }
  89
  90 static void
  91 cn10k_sso_hws_release(void *arg, void *hws)
  92 {
  93         struct cnxk_sso_evdev *dev = arg;
  94         struct cn10k_sso_hws *ws = hws;
  95         int i;
  96
  97         for (i = 0; i < dev->nb_event_queues; i++)
  98                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
  99         memset(ws, 0, sizeof(*ws));
 100 }
 101
 102 static void
 103 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 104                            cnxk_handle_event_t fn, void *arg)
 105 {
 106         struct cn10k_sso_hws *ws = hws;
 107         uint64_t cq_ds_cnt = 1;
 108         uint64_t aq_cnt = 1;
 109         uint64_t ds_cnt = 1;
 110         struct rte_event ev;
 111         uint64_t val, req;
 112
 113         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 114
 115         req = queue_id;     /* GGRP ID */
 116         req |= BIT_ULL(18); /* Grouped */
 117         req |= BIT_ULL(16); /* WAIT */
 118
 119         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 120         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 121         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 122         cq_ds_cnt &= 0x3FFF3FFF0000;
 123
 124         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 125                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 126                 cn10k_sso_hws_get_work_empty(ws, &ev);
 127                 if (fn != NULL && ev.u64 != 0)
 128                         fn(arg, ev);
 129                 if (ev.sched_type != SSO_TT_EMPTY)
 130                         cnxk_sso_hws_swtag_flush(
 131                                 ws->base + SSOW_LF_GWS_WQE0,
 132                                 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
 133                 do {
 134                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 135                 } while (val & BIT_ULL(56));
 136                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 137                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 138                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 139                 /* Extract cq and ds count */
 140                 cq_ds_cnt &= 0x3FFF3FFF0000;
 141         }
 142
 143         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 144         rte_mb();
 145 }
 146
 147 static void
 148 cn10k_sso_hws_reset(void *arg, void *hws)
 149 {
 150         struct cnxk_sso_evdev *dev = arg;
 151         struct cn10k_sso_hws *ws = hws;
 152         uintptr_t base = ws->base;
 153         uint64_t pend_state;
 154         union {
 155                 __uint128_t wdata;
 156                 uint64_t u64[2];
 157         } gw;
 158         uint8_t pend_tt;
 159
 160         /* Wait till getwork/swtp/waitw/desched completes. */
 161         do {
 162                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 163         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 164                                BIT_ULL(56) | BIT_ULL(54)));
 165         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 166         if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 167                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 168                         cnxk_sso_hws_swtag_untag(base +
 169                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 170                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 171         }
 172
 173         /* Wait for desched to complete. */
 174         do {
 175                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 176         } while (pend_state & BIT_ULL(58));
 177
 178         switch (dev->gw_mode) {
 179         case CN10K_GW_MODE_PREF:
 180                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 181                         ;
 182                 break;
 183         case CN10K_GW_MODE_PREF_WFE:
 184                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
 185                        SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
 186                         continue;
 187                 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 188                 break;
 189         case CN10K_GW_MODE_NONE:
 190         default:
 191                 break;
 192         }
 193
 194         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 195             SSO_TT_EMPTY) {
 196                 plt_write64(BIT_ULL(16) | 1,
 197                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 198                 do {
 199                         roc_load_pair(gw.u64[0], gw.u64[1],
 200                                       ws->base + SSOW_LF_GWS_WQE0);
 201                 } while (gw.u64[0] & BIT_ULL(63));
 202                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 203                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 204                         if (pend_tt == SSO_TT_ATOMIC ||
 205                             pend_tt == SSO_TT_ORDERED)
 206                                 cnxk_sso_hws_swtag_untag(
 207                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 208                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 209                 }
 210         }
 211
 212         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 213         rte_mb();
 214 }
 215
 216 static void
 217 cn10k_sso_set_rsrc(void *arg)
 218 {
 219         struct cnxk_sso_evdev *dev = arg;
 220
 221         dev->max_event_ports = dev->sso.max_hws;
 222         dev->max_event_queues =
 223                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 224                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 225                               dev->sso.max_hwgrp;
 226 }
 227
 228 static int
 229 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 230 {
 231         struct cnxk_sso_evdev *dev = arg;
 232
 233         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 234 }
 235
 236 static void
 237 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 238 {
 239         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 240
 241         event_dev->enqueue = cn10k_sso_hws_enq;
 242         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 243         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 244         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 245
 246         event_dev->dequeue = cn10k_sso_hws_deq;
 247         event_dev->dequeue_burst = cn10k_sso_hws_deq_burst;
 248         if (dev->is_timeout_deq) {
 249                 event_dev->dequeue = cn10k_sso_hws_tmo_deq;
 250                 event_dev->dequeue_burst = cn10k_sso_hws_tmo_deq_burst;
 251         }
 252 }
 253
 254 static void
 255 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 256                    struct rte_event_dev_info *dev_info)
 257 {
 258         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 259
 260         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 261         cnxk_sso_info_get(dev, dev_info);
 262 }
 263
 264 static int
 265 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 266 {
 267         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 268         int rc;
 269
 270         rc = cnxk_sso_dev_validate(event_dev);
 271         if (rc < 0) {
 272                 plt_err("Invalid event device configuration");
 273                 return -EINVAL;
 274         }
 275
 276         roc_sso_rsrc_fini(&dev->sso);
 277
 278         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 279                                  dev->nb_event_queues);
 280         if (rc < 0) {
 281                 plt_err("Failed to initialize SSO resources");
 282                 return -ENODEV;
 283         }
 284
 285         rc = cnxk_sso_xaq_allocate(dev);
 286         if (rc < 0)
 287                 goto cnxk_rsrc_fini;
 288
 289         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 290                                     cn10k_sso_hws_setup);
 291         if (rc < 0)
 292                 goto cnxk_rsrc_fini;
 293
 294         /* Restore any prior port-queue mapping. */
 295         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 296
 297         dev->configured = 1;
 298         rte_mb();
 299
 300         return 0;
 301 cnxk_rsrc_fini:
 302         roc_sso_rsrc_fini(&dev->sso);
 303         dev->nb_event_ports = 0;
 304         return rc;
 305 }
 306
 307 static int
 308 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 309                      const struct rte_event_port_conf *port_conf)
 310 {
 311
 312         RTE_SET_USED(port_conf);
 313         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 314 }
 315
 316 static void
 317 cn10k_sso_port_release(void *port)
 318 {
 319         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 320         struct cnxk_sso_evdev *dev;
 321
 322         if (port == NULL)
 323                 return;
 324
 325         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 326         if (!gws_cookie->configured)
 327                 goto free;
 328
 329         cn10k_sso_hws_release(dev, port);
 330         memset(gws_cookie, 0, sizeof(*gws_cookie));
 331 free:
 332         rte_free(gws_cookie);
 333 }
 334
 335 static int
 336 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 337                     const uint8_t queues[], const uint8_t priorities[],
 338                     uint16_t nb_links)
 339 {
 340         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 341         uint16_t hwgrp_ids[nb_links];
 342         uint16_t link;
 343
 344         RTE_SET_USED(priorities);
 345         for (link = 0; link < nb_links; link++)
 346                 hwgrp_ids[link] = queues[link];
 347         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 348
 349         return (int)nb_links;
 350 }
 351
 352 static int
 353 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 354                       uint8_t queues[], uint16_t nb_unlinks)
 355 {
 356         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 357         uint16_t hwgrp_ids[nb_unlinks];
 358         uint16_t unlink;
 359
 360         for (unlink = 0; unlink < nb_unlinks; unlink++)
 361                 hwgrp_ids[unlink] = queues[unlink];
 362         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 363
 364         return (int)nb_unlinks;
 365 }
 366
 367 static int
 368 cn10k_sso_start(struct rte_eventdev *event_dev)
 369 {
 370         int rc;
 371
 372         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 373                             cn10k_sso_hws_flush_events);
 374         if (rc < 0)
 375                 return rc;
 376         cn10k_sso_fp_fns_set(event_dev);
 377
 378         return rc;
 379 }
 380
 381 static void
 382 cn10k_sso_stop(struct rte_eventdev *event_dev)
 383 {
 384         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 385                       cn10k_sso_hws_flush_events);
 386 }
 387
 388 static int
 389 cn10k_sso_close(struct rte_eventdev *event_dev)
 390 {
 391         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 392 }
 393
 394 static int
 395 cn10k_sso_selftest(void)
 396 {
 397         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 398 }
 399
 400 static int
 401 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 402                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 403 {
 404         int rc;
 405
 406         RTE_SET_USED(event_dev);
 407         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 408         if (rc)
 409                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 410         else
 411                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 412                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 413                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
 414
 415         return 0;
 416 }
 417
 418 static void
 419 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 420                        void *tstmp_info)
 421 {
 422         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 423         int i;
 424
 425         for (i = 0; i < dev->nb_event_ports; i++) {
 426                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 427                 ws->lookup_mem = lookup_mem;
 428                 ws->tstamp = tstmp_info;
 429         }
 430 }
 431
 432 static int
 433 cn10k_sso_rx_adapter_queue_add(
 434         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 435         int32_t rx_queue_id,
 436         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 437 {
 438         struct cn10k_eth_rxq *rxq;
 439         void *lookup_mem;
 440         void *tstmp_info;
 441         int rc;
 442
 443         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 444         if (rc)
 445                 return -EINVAL;
 446
 447         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 448                                            queue_conf);
 449         if (rc)
 450                 return -EINVAL;
 451         rxq = eth_dev->data->rx_queues[0];
 452         lookup_mem = rxq->lookup_mem;
 453         tstmp_info = rxq->tstamp;
 454         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 455         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 456
 457         return 0;
 458 }
 459
 460 static int
 461 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 462                                const struct rte_eth_dev *eth_dev,
 463                                int32_t rx_queue_id)
 464 {
 465         int rc;
 466
 467         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 468         if (rc)
 469                 return -EINVAL;
 470
 471         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 472 }
 473
 474 static struct rte_eventdev_ops cn10k_sso_dev_ops = {
 475         .dev_infos_get = cn10k_sso_info_get,
 476         .dev_configure = cn10k_sso_dev_configure,
 477         .queue_def_conf = cnxk_sso_queue_def_conf,
 478         .queue_setup = cnxk_sso_queue_setup,
 479         .queue_release = cnxk_sso_queue_release,
 480         .port_def_conf = cnxk_sso_port_def_conf,
 481         .port_setup = cn10k_sso_port_setup,
 482         .port_release = cn10k_sso_port_release,
 483         .port_link = cn10k_sso_port_link,
 484         .port_unlink = cn10k_sso_port_unlink,
 485         .timeout_ticks = cnxk_sso_timeout_ticks,
 486
 487         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 488         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 489         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 490         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 491         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 492
 493         .timer_adapter_caps_get = cnxk_tim_caps_get,
 494
 495         .dump = cnxk_sso_dump,
 496         .dev_start = cn10k_sso_start,
 497         .dev_stop = cn10k_sso_stop,
 498         .dev_close = cn10k_sso_close,
 499         .dev_selftest = cn10k_sso_selftest,
 500 };
 501
 502 static int
 503 cn10k_sso_init(struct rte_eventdev *event_dev)
 504 {
 505         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 506         int rc;
 507
 508         if (RTE_CACHE_LINE_SIZE != 64) {
 509                 plt_err("Driver not compiled for CN9K");
 510                 return -EFAULT;
 511         }
 512
 513         rc = roc_plt_init();
 514         if (rc < 0) {
 515                 plt_err("Failed to initialize platform model");
 516                 return rc;
 517         }
 518
 519         event_dev->dev_ops = &cn10k_sso_dev_ops;
 520         /* For secondary processes, the primary has done all the work */
 521         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 522                 cn10k_sso_fp_fns_set(event_dev);
 523                 return 0;
 524         }
 525
 526         rc = cnxk_sso_init(event_dev);
 527         if (rc < 0)
 528                 return rc;
 529
 530         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 531         if (!dev->max_event_ports || !dev->max_event_queues) {
 532                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 533                         dev->max_event_queues, dev->max_event_ports);
 534                 cnxk_sso_fini(event_dev);
 535                 return -ENODEV;
 536         }
 537
 538         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 539                     event_dev->data->name, dev->max_event_queues,
 540                     dev->max_event_ports);
 541
 542         return 0;
 543 }
 544
 545 static int
 546 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 547 {
 548         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 549                                        sizeof(struct cnxk_sso_evdev),
 550                                        cn10k_sso_init);
 551 }
 552
 553 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 554         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 555         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 556         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 557         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 558         {
 559                 .vendor_id = 0,
 560         },
 561 };
 562
 563 static struct rte_pci_driver cn10k_pci_sso = {
 564         .id_table = cn10k_pci_sso_map,
 565         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 566         .probe = cn10k_sso_probe,
 567         .remove = cnxk_sso_remove,
 568 };
 569
 570 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 571 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 572 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 573 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 574                               CNXK_SSO_GGRP_QOS "=<string>"
 575                               CNXK_SSO_FORCE_BP "=1"
 576                               CN10K_SSO_GW_MODE "=<int>"
 577                               CNXK_TIM_DISABLE_NPA "=1"
 578                               CNXK_TIM_CHNK_SLOTS "=<int>"
 579                               CNXK_TIM_RINGS_LMT "=<int>"
 580                               CNXK_TIM_STATS_ENA "=1");