drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)                           \
  10         deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
  11
  12 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)                           \
  13         enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
  14
  15 static uint32_t
  16 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  17 {
  18         uint32_t wdata = BIT(16) | 1;
  19
  20         switch (dev->gw_mode) {
  21         case CN10K_GW_MODE_NONE:
  22         default:
  23                 break;
  24         case CN10K_GW_MODE_PREF:
  25                 wdata |= BIT(19);
  26                 break;
  27         case CN10K_GW_MODE_PREF_WFE:
  28                 wdata |= BIT(20) | BIT(19);
  29                 break;
  30         }
  31
  32         return wdata;
  33 }
  34
  35 static void *
  36 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  37 {
  38         struct cnxk_sso_evdev *dev = arg;
  39         struct cn10k_sso_hws *ws;
  40
  41         /* Allocate event port memory */
  42         ws = rte_zmalloc("cn10k_ws",
  43                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  44                          RTE_CACHE_LINE_SIZE);
  45         if (ws == NULL) {
  46                 plt_err("Failed to alloc memory for port=%d", port_id);
  47                 return NULL;
  48         }
  49
  50         /* First cache line is reserved for cookie */
  51         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  52         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  53         ws->hws_id = port_id;
  54         ws->swtag_req = 0;
  55         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  56         ws->lmt_base = dev->sso.lmt_base;
  57
  58         return ws;
  59 }
  60
  61 static int
  62 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  63 {
  64         struct cnxk_sso_evdev *dev = arg;
  65         struct cn10k_sso_hws *ws = port;
  66
  67         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  68 }
  69
  70 static int
  71 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  72 {
  73         struct cnxk_sso_evdev *dev = arg;
  74         struct cn10k_sso_hws *ws = port;
  75
  76         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  77 }
  78
  79 static void
  80 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base)
  81 {
  82         struct cnxk_sso_evdev *dev = arg;
  83         struct cn10k_sso_hws *ws = hws;
  84         uint64_t val;
  85
  86         ws->grp_base = grp_base;
  87         ws->fc_mem = (uint64_t *)dev->fc_iova;
  88         ws->xaq_lmt = dev->xaq_lmt;
  89
  90         /* Set get_work timeout for HWS */
  91         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
  92         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  93 }
  94
  95 static void
  96 cn10k_sso_hws_release(void *arg, void *hws)
  97 {
  98         struct cnxk_sso_evdev *dev = arg;
  99         struct cn10k_sso_hws *ws = hws;
 100         int i;
 101
 102         for (i = 0; i < dev->nb_event_queues; i++)
 103                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
 104         memset(ws, 0, sizeof(*ws));
 105 }
 106
 107 static void
 108 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 109                            cnxk_handle_event_t fn, void *arg)
 110 {
 111         struct cn10k_sso_hws *ws = hws;
 112         uint64_t cq_ds_cnt = 1;
 113         uint64_t aq_cnt = 1;
 114         uint64_t ds_cnt = 1;
 115         struct rte_event ev;
 116         uint64_t val, req;
 117
 118         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 119
 120         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 121         req = queue_id;     /* GGRP ID */
 122         req |= BIT_ULL(18); /* Grouped */
 123         req |= BIT_ULL(16); /* WAIT */
 124
 125         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 126         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 127         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 128         cq_ds_cnt &= 0x3FFF3FFF0000;
 129
 130         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 131                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 132                 cn10k_sso_hws_get_work_empty(ws, &ev);
 133                 if (fn != NULL && ev.u64 != 0)
 134                         fn(arg, ev);
 135                 if (ev.sched_type != SSO_TT_EMPTY)
 136                         cnxk_sso_hws_swtag_flush(
 137                                 ws->base + SSOW_LF_GWS_WQE0,
 138                                 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
 139                 do {
 140                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 141                 } while (val & BIT_ULL(56));
 142                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 143                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 144                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 145                 /* Extract cq and ds count */
 146                 cq_ds_cnt &= 0x3FFF3FFF0000;
 147         }
 148
 149         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 150         rte_mb();
 151 }
 152
 153 static void
 154 cn10k_sso_hws_reset(void *arg, void *hws)
 155 {
 156         struct cnxk_sso_evdev *dev = arg;
 157         struct cn10k_sso_hws *ws = hws;
 158         uintptr_t base = ws->base;
 159         uint64_t pend_state;
 160         union {
 161                 __uint128_t wdata;
 162                 uint64_t u64[2];
 163         } gw;
 164         uint8_t pend_tt;
 165
 166         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 167         /* Wait till getwork/swtp/waitw/desched completes. */
 168         do {
 169                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 170         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 171                                BIT_ULL(56) | BIT_ULL(54)));
 172         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 173         if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 174                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 175                         cnxk_sso_hws_swtag_untag(base +
 176                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 177                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 178         }
 179
 180         /* Wait for desched to complete. */
 181         do {
 182                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 183         } while (pend_state & BIT_ULL(58));
 184
 185         switch (dev->gw_mode) {
 186         case CN10K_GW_MODE_PREF:
 187                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 188                         ;
 189                 break;
 190         case CN10K_GW_MODE_PREF_WFE:
 191                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
 192                        SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
 193                         continue;
 194                 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 195                 break;
 196         case CN10K_GW_MODE_NONE:
 197         default:
 198                 break;
 199         }
 200
 201         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 202             SSO_TT_EMPTY) {
 203                 plt_write64(BIT_ULL(16) | 1,
 204                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 205                 do {
 206                         roc_load_pair(gw.u64[0], gw.u64[1],
 207                                       ws->base + SSOW_LF_GWS_WQE0);
 208                 } while (gw.u64[0] & BIT_ULL(63));
 209                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 210                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 211                         if (pend_tt == SSO_TT_ATOMIC ||
 212                             pend_tt == SSO_TT_ORDERED)
 213                                 cnxk_sso_hws_swtag_untag(
 214                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 215                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 216                 }
 217         }
 218
 219         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 220         rte_mb();
 221 }
 222
 223 static void
 224 cn10k_sso_set_rsrc(void *arg)
 225 {
 226         struct cnxk_sso_evdev *dev = arg;
 227
 228         dev->max_event_ports = dev->sso.max_hws;
 229         dev->max_event_queues =
 230                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 231                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 232                               dev->sso.max_hwgrp;
 233 }
 234
 235 static int
 236 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 237 {
 238         struct cnxk_sso_evdev *dev = arg;
 239
 240         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 241 }
 242
 243 static int
 244 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
 245 {
 246         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 247         int i;
 248
 249         if (dev->tx_adptr_data == NULL)
 250                 return 0;
 251
 252         for (i = 0; i < dev->nb_event_ports; i++) {
 253                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 254                 void *ws_cookie;
 255
 256                 ws_cookie = cnxk_sso_hws_get_cookie(ws);
 257                 ws_cookie = rte_realloc_socket(
 258                         ws_cookie,
 259                         sizeof(struct cnxk_sso_hws_cookie) +
 260                                 sizeof(struct cn10k_sso_hws) +
 261                                 dev->tx_adptr_data_sz,
 262                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 263                 if (ws_cookie == NULL)
 264                         return -ENOMEM;
 265                 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
 266                 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
 267                        dev->tx_adptr_data_sz);
 268                 event_dev->data->ports[i] = ws;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static void
 275 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 276 {
 277         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 278         const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = {
 279 #define R(name, flags)[flags] = cn10k_sso_hws_deq_##name,
 280                 NIX_RX_FASTPATH_MODES
 281 #undef R
 282         };
 283
 284         const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = {
 285 #define R(name, flags)[flags] = cn10k_sso_hws_deq_burst_##name,
 286                 NIX_RX_FASTPATH_MODES
 287 #undef R
 288         };
 289
 290         const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = {
 291 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_##name,
 292                 NIX_RX_FASTPATH_MODES
 293 #undef R
 294         };
 295
 296         const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = {
 297 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_burst_##name,
 298                 NIX_RX_FASTPATH_MODES
 299 #undef R
 300         };
 301
 302         const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = {
 303 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_##name,
 304                 NIX_RX_FASTPATH_MODES
 305 #undef R
 306         };
 307
 308         const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 309 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_burst_##name,
 310                 NIX_RX_FASTPATH_MODES
 311 #undef R
 312         };
 313
 314         const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = {
 315 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_##name,
 316                 NIX_RX_FASTPATH_MODES
 317 #undef R
 318         };
 319
 320         const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = {
 321 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_burst_##name,
 322                 NIX_RX_FASTPATH_MODES
 323 #undef R
 324         };
 325
 326         const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = {
 327 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_##name,
 328
 329                 NIX_RX_FASTPATH_MODES
 330 #undef R
 331         };
 332
 333         const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 334 #define R(name, flags)[flags] = cn10k_sso_hws_deq_seg_burst_##name,
 335                         NIX_RX_FASTPATH_MODES
 336 #undef R
 337         };
 338
 339         const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = {
 340 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_##name,
 341                 NIX_RX_FASTPATH_MODES
 342 #undef R
 343         };
 344
 345         const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 346 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 347                 NIX_RX_FASTPATH_MODES
 348 #undef R
 349         };
 350
 351         const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 352 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_##name,
 353                 NIX_RX_FASTPATH_MODES
 354 #undef R
 355         };
 356
 357         const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 358 #define R(name, flags)[flags] = cn10k_sso_hws_deq_ca_seg_burst_##name,
 359                 NIX_RX_FASTPATH_MODES
 360 #undef R
 361         };
 362
 363         const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = {
 364 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_##name,
 365                 NIX_RX_FASTPATH_MODES
 366 #undef R
 367         };
 368
 369         const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = {
 370 #define R(name, flags)[flags] = cn10k_sso_hws_deq_tmo_ca_seg_burst_##name,
 371                 NIX_RX_FASTPATH_MODES
 372 #undef R
 373         };
 374
 375         /* Tx modes */
 376         const event_tx_adapter_enqueue_t
 377                 sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = {
 378 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_##name,
 379                         NIX_TX_FASTPATH_MODES
 380 #undef T
 381                 };
 382
 383         const event_tx_adapter_enqueue_t
 384                 sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = {
 385 #define T(name, sz, flags)[flags] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
 386                         NIX_TX_FASTPATH_MODES
 387 #undef T
 388                 };
 389
 390         event_dev->enqueue = cn10k_sso_hws_enq;
 391         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 392         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 393         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 394         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 395                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 396                                        sso_hws_deq_seg);
 397                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 398                                        sso_hws_deq_seg_burst);
 399                 if (dev->is_timeout_deq) {
 400                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 401                                                sso_hws_deq_tmo_seg);
 402                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 403                                                sso_hws_deq_tmo_seg_burst);
 404                 }
 405                 if (dev->is_ca_internal_port) {
 406                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 407                                                sso_hws_deq_ca_seg);
 408                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 409                                                sso_hws_deq_ca_seg_burst);
 410                 }
 411                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 412                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 413                                                sso_hws_deq_tmo_ca_seg);
 414                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 415                                                sso_hws_deq_tmo_ca_seg_burst);
 416                 }
 417         } else {
 418                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
 419                 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 420                                        sso_hws_deq_burst);
 421                 if (dev->is_timeout_deq) {
 422                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 423                                                sso_hws_deq_tmo);
 424                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 425                                                sso_hws_deq_tmo_burst);
 426                 }
 427                 if (dev->is_ca_internal_port) {
 428                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 429                                                sso_hws_deq_ca);
 430                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 431                                                sso_hws_deq_ca_burst);
 432                 }
 433                 if (dev->is_timeout_deq && dev->is_ca_internal_port) {
 434                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
 435                                                sso_hws_deq_tmo_ca);
 436                         CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
 437                                                sso_hws_deq_tmo_ca_burst);
 438                 }
 439         }
 440         event_dev->ca_enqueue = cn10k_sso_hws_ca_enq;
 441
 442         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
 443                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 444                                        sso_hws_tx_adptr_enq_seg);
 445         else
 446                 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
 447                                        sso_hws_tx_adptr_enq);
 448
 449         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 450 }
 451
 452 static void
 453 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 454                    struct rte_event_dev_info *dev_info)
 455 {
 456         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 457
 458         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 459         cnxk_sso_info_get(dev, dev_info);
 460 }
 461
 462 static int
 463 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 464 {
 465         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 466         int rc;
 467
 468         rc = cnxk_sso_dev_validate(event_dev);
 469         if (rc < 0) {
 470                 plt_err("Invalid event device configuration");
 471                 return -EINVAL;
 472         }
 473
 474         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 475                                  dev->nb_event_queues);
 476         if (rc < 0) {
 477                 plt_err("Failed to initialize SSO resources");
 478                 return -ENODEV;
 479         }
 480
 481         rc = cnxk_sso_xaq_allocate(dev);
 482         if (rc < 0)
 483                 goto cnxk_rsrc_fini;
 484
 485         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 486                                     cn10k_sso_hws_setup);
 487         if (rc < 0)
 488                 goto cnxk_rsrc_fini;
 489
 490         /* Restore any prior port-queue mapping. */
 491         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 492
 493         dev->configured = 1;
 494         rte_mb();
 495
 496         return 0;
 497 cnxk_rsrc_fini:
 498         roc_sso_rsrc_fini(&dev->sso);
 499         dev->nb_event_ports = 0;
 500         return rc;
 501 }
 502
 503 static int
 504 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 505                      const struct rte_event_port_conf *port_conf)
 506 {
 507
 508         RTE_SET_USED(port_conf);
 509         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 510 }
 511
 512 static void
 513 cn10k_sso_port_release(void *port)
 514 {
 515         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 516         struct cnxk_sso_evdev *dev;
 517
 518         if (port == NULL)
 519                 return;
 520
 521         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 522         if (!gws_cookie->configured)
 523                 goto free;
 524
 525         cn10k_sso_hws_release(dev, port);
 526         memset(gws_cookie, 0, sizeof(*gws_cookie));
 527 free:
 528         rte_free(gws_cookie);
 529 }
 530
 531 static int
 532 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 533                     const uint8_t queues[], const uint8_t priorities[],
 534                     uint16_t nb_links)
 535 {
 536         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 537         uint16_t hwgrp_ids[nb_links];
 538         uint16_t link;
 539
 540         RTE_SET_USED(priorities);
 541         for (link = 0; link < nb_links; link++)
 542                 hwgrp_ids[link] = queues[link];
 543         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 544
 545         return (int)nb_links;
 546 }
 547
 548 static int
 549 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 550                       uint8_t queues[], uint16_t nb_unlinks)
 551 {
 552         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 553         uint16_t hwgrp_ids[nb_unlinks];
 554         uint16_t unlink;
 555
 556         for (unlink = 0; unlink < nb_unlinks; unlink++)
 557                 hwgrp_ids[unlink] = queues[unlink];
 558         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 559
 560         return (int)nb_unlinks;
 561 }
 562
 563 static int
 564 cn10k_sso_start(struct rte_eventdev *event_dev)
 565 {
 566         int rc;
 567
 568         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 569         if (rc < 0)
 570                 return rc;
 571
 572         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 573                             cn10k_sso_hws_flush_events);
 574         if (rc < 0)
 575                 return rc;
 576         cn10k_sso_fp_fns_set(event_dev);
 577
 578         return rc;
 579 }
 580
 581 static void
 582 cn10k_sso_stop(struct rte_eventdev *event_dev)
 583 {
 584         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 585                       cn10k_sso_hws_flush_events);
 586 }
 587
 588 static int
 589 cn10k_sso_close(struct rte_eventdev *event_dev)
 590 {
 591         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 592 }
 593
 594 static int
 595 cn10k_sso_selftest(void)
 596 {
 597         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 598 }
 599
 600 static int
 601 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 602                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 603 {
 604         int rc;
 605
 606         RTE_SET_USED(event_dev);
 607         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 608         if (rc)
 609                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 610         else
 611                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 612                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 613                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
 614                         RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
 615
 616         return 0;
 617 }
 618
 619 static void
 620 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 621                        void *tstmp_info)
 622 {
 623         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 624         int i;
 625
 626         for (i = 0; i < dev->nb_event_ports; i++) {
 627                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 628                 ws->lookup_mem = lookup_mem;
 629                 ws->tstamp = tstmp_info;
 630         }
 631 }
 632
 633 static int
 634 cn10k_sso_rx_adapter_queue_add(
 635         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 636         int32_t rx_queue_id,
 637         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 638 {
 639         struct cn10k_eth_rxq *rxq;
 640         void *lookup_mem;
 641         void *tstmp_info;
 642         int rc;
 643
 644         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 645         if (rc)
 646                 return -EINVAL;
 647
 648         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 649                                            queue_conf);
 650         if (rc)
 651                 return -EINVAL;
 652         rxq = eth_dev->data->rx_queues[0];
 653         lookup_mem = rxq->lookup_mem;
 654         tstmp_info = rxq->tstamp;
 655         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 656         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 657
 658         return 0;
 659 }
 660
 661 static int
 662 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 663                                const struct rte_eth_dev *eth_dev,
 664                                int32_t rx_queue_id)
 665 {
 666         int rc;
 667
 668         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 669         if (rc)
 670                 return -EINVAL;
 671
 672         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 673 }
 674
 675 static int
 676 cn10k_sso_rx_adapter_vector_limits(
 677         const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
 678         struct rte_event_eth_rx_adapter_vector_limits *limits)
 679 {
 680         struct cnxk_eth_dev *cnxk_eth_dev;
 681         int ret;
 682
 683         RTE_SET_USED(dev);
 684         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 685         if (ret)
 686                 return -ENOTSUP;
 687
 688         cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
 689         limits->log2_sz = true;
 690         limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
 691         limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
 692         limits->min_timeout_ns =
 693                 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
 694         limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
 695
 696         return 0;
 697 }
 698
 699 static int
 700 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
 701                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 702 {
 703         int ret;
 704
 705         RTE_SET_USED(dev);
 706         ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 707         if (ret)
 708                 *caps = 0;
 709         else
 710                 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
 711                         RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
 712
 713         return 0;
 714 }
 715
 716 static int
 717 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
 718                                const struct rte_eth_dev *eth_dev,
 719                                int32_t tx_queue_id)
 720 {
 721         struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
 722         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 723         uint64_t tx_offloads;
 724         int rc;
 725
 726         RTE_SET_USED(id);
 727         rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
 728         if (rc < 0)
 729                 return rc;
 730
 731         /* Can't enable tstamp if all the ports don't have it enabled. */
 732         tx_offloads = cnxk_eth_dev->tx_offload_flags;
 733         if (dev->tx_adptr_configured) {
 734                 uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 735                 uint8_t tstmp_ena =
 736                         !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F);
 737
 738                 if (tstmp_ena && !tstmp_req)
 739                         dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 740                 else if (!tstmp_ena && tstmp_req)
 741                         tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F);
 742         }
 743
 744         dev->tx_offloads |= tx_offloads;
 745         rc = cn10k_sso_updt_tx_adptr_data(event_dev);
 746         if (rc < 0)
 747                 return rc;
 748         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 749         dev->tx_adptr_configured = 1;
 750
 751         return 0;
 752 }
 753
 754 static int
 755 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
 756                                const struct rte_eth_dev *eth_dev,
 757                                int32_t tx_queue_id)
 758 {
 759         int rc;
 760
 761         RTE_SET_USED(id);
 762         rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
 763         if (rc < 0)
 764                 return rc;
 765         return cn10k_sso_updt_tx_adptr_data(event_dev);
 766 }
 767
 768 static int
 769 cn10k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,
 770                               const struct rte_cryptodev *cdev, uint32_t *caps)
 771 {
 772         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 773         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 774
 775         *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |
 776                 RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;
 777
 778         return 0;
 779 }
 780
 781 static int
 782 cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev,
 783                             const struct rte_cryptodev *cdev,
 784                             int32_t queue_pair_id,
 785                             const struct rte_event *event)
 786 {
 787         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 788
 789         RTE_SET_USED(event);
 790
 791         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 792         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 793
 794         dev->is_ca_internal_port = 1;
 795         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 796
 797         return cnxk_crypto_adapter_qp_add(event_dev, cdev, queue_pair_id);
 798 }
 799
 800 static int
 801 cn10k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev,
 802                             const struct rte_cryptodev *cdev,
 803                             int32_t queue_pair_id)
 804 {
 805         CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k");
 806         CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k");
 807
 808         return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id);
 809 }
 810
 811 static struct eventdev_ops cn10k_sso_dev_ops = {
 812         .dev_infos_get = cn10k_sso_info_get,
 813         .dev_configure = cn10k_sso_dev_configure,
 814         .queue_def_conf = cnxk_sso_queue_def_conf,
 815         .queue_setup = cnxk_sso_queue_setup,
 816         .queue_release = cnxk_sso_queue_release,
 817         .port_def_conf = cnxk_sso_port_def_conf,
 818         .port_setup = cn10k_sso_port_setup,
 819         .port_release = cn10k_sso_port_release,
 820         .port_link = cn10k_sso_port_link,
 821         .port_unlink = cn10k_sso_port_unlink,
 822         .timeout_ticks = cnxk_sso_timeout_ticks,
 823
 824         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 825         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 826         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 827         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 828         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 829
 830         .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
 831
 832         .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
 833         .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
 834         .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
 835
 836         .timer_adapter_caps_get = cnxk_tim_caps_get,
 837
 838         .crypto_adapter_caps_get = cn10k_crypto_adapter_caps_get,
 839         .crypto_adapter_queue_pair_add = cn10k_crypto_adapter_qp_add,
 840         .crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
 841
 842         .dump = cnxk_sso_dump,
 843         .dev_start = cn10k_sso_start,
 844         .dev_stop = cn10k_sso_stop,
 845         .dev_close = cn10k_sso_close,
 846         .dev_selftest = cn10k_sso_selftest,
 847 };
 848
 849 static int
 850 cn10k_sso_init(struct rte_eventdev *event_dev)
 851 {
 852         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 853         int rc;
 854
 855         if (RTE_CACHE_LINE_SIZE != 64) {
 856                 plt_err("Driver not compiled for CN10K");
 857                 return -EFAULT;
 858         }
 859
 860         rc = roc_plt_init();
 861         if (rc < 0) {
 862                 plt_err("Failed to initialize platform model");
 863                 return rc;
 864         }
 865
 866         event_dev->dev_ops = &cn10k_sso_dev_ops;
 867         /* For secondary processes, the primary has done all the work */
 868         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 869                 cn10k_sso_fp_fns_set(event_dev);
 870                 return 0;
 871         }
 872
 873         rc = cnxk_sso_init(event_dev);
 874         if (rc < 0)
 875                 return rc;
 876
 877         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 878         if (!dev->max_event_ports || !dev->max_event_queues) {
 879                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 880                         dev->max_event_queues, dev->max_event_ports);
 881                 cnxk_sso_fini(event_dev);
 882                 return -ENODEV;
 883         }
 884
 885         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 886                     event_dev->data->name, dev->max_event_queues,
 887                     dev->max_event_ports);
 888
 889         return 0;
 890 }
 891
 892 static int
 893 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 894 {
 895         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 896                                        sizeof(struct cnxk_sso_evdev),
 897                                        cn10k_sso_init);
 898 }
 899
 900 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 901         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 902         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 903         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 904         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 905         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 906         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 907         {
 908                 .vendor_id = 0,
 909         },
 910 };
 911
 912 static struct rte_pci_driver cn10k_pci_sso = {
 913         .id_table = cn10k_pci_sso_map,
 914         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 915         .probe = cn10k_sso_probe,
 916         .remove = cnxk_sso_remove,
 917 };
 918
 919 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 920 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 921 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 922 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 923                               CNXK_SSO_GGRP_QOS "=<string>"
 924                               CNXK_SSO_FORCE_BP "=1"
 925                               CN10K_SSO_GW_MODE "=<int>"
 926                               CNXK_TIM_DISABLE_NPA "=1"
 927                               CNXK_TIM_CHNK_SLOTS "=<int>"
 928                               CNXK_TIM_RINGS_LMT "=<int>"
 929                               CNXK_TIM_STATS_ENA "=1"
 930                               CNXK_TIM_EXT_CLK "=<string>");