drivers/event/cnxk/cn10k_eventdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cn10k_worker.h"
   6 #include "cnxk_eventdev.h"
   7 #include "cnxk_worker.h"
   8
   9 static uint32_t
  10 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
  11 {
  12         uint32_t wdata = BIT(16) | 1;
  13
  14         switch (dev->gw_mode) {
  15         case CN10K_GW_MODE_NONE:
  16         default:
  17                 break;
  18         case CN10K_GW_MODE_PREF:
  19                 wdata |= BIT(19);
  20                 break;
  21         case CN10K_GW_MODE_PREF_WFE:
  22                 wdata |= BIT(20) | BIT(19);
  23                 break;
  24         }
  25
  26         return wdata;
  27 }
  28
  29 static void *
  30 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
  31 {
  32         struct cnxk_sso_evdev *dev = arg;
  33         struct cn10k_sso_hws *ws;
  34
  35         /* Allocate event port memory */
  36         ws = rte_zmalloc("cn10k_ws",
  37                          sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
  38                          RTE_CACHE_LINE_SIZE);
  39         if (ws == NULL) {
  40                 plt_err("Failed to alloc memory for port=%d", port_id);
  41                 return NULL;
  42         }
  43
  44         /* First cache line is reserved for cookie */
  45         ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
  46         ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
  47         ws->hws_id = port_id;
  48         ws->swtag_req = 0;
  49         ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
  50         ws->lmt_base = dev->sso.lmt_base;
  51
  52         return ws;
  53 }
  54
  55 static int
  56 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  57 {
  58         struct cnxk_sso_evdev *dev = arg;
  59         struct cn10k_sso_hws *ws = port;
  60
  61         return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
  62 }
  63
  64 static int
  65 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
  66 {
  67         struct cnxk_sso_evdev *dev = arg;
  68         struct cn10k_sso_hws *ws = port;
  69
  70         return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
  71 }
  72
  73 static void
  74 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
  75 {
  76         struct cnxk_sso_evdev *dev = arg;
  77         struct cn10k_sso_hws *ws = hws;
  78         uint64_t val;
  79
  80         rte_memcpy(ws->grps_base, grps_base,
  81                    sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
  82         ws->fc_mem = dev->fc_mem;
  83         ws->xaq_lmt = dev->xaq_lmt;
  84
  85         /* Set get_work timeout for HWS */
  86         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
  87         plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
  88 }
  89
  90 static void
  91 cn10k_sso_hws_release(void *arg, void *hws)
  92 {
  93         struct cnxk_sso_evdev *dev = arg;
  94         struct cn10k_sso_hws *ws = hws;
  95         int i;
  96
  97         for (i = 0; i < dev->nb_event_queues; i++)
  98                 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
  99         memset(ws, 0, sizeof(*ws));
 100 }
 101
 102 static void
 103 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
 104                            cnxk_handle_event_t fn, void *arg)
 105 {
 106         struct cn10k_sso_hws *ws = hws;
 107         uint64_t cq_ds_cnt = 1;
 108         uint64_t aq_cnt = 1;
 109         uint64_t ds_cnt = 1;
 110         struct rte_event ev;
 111         uint64_t val, req;
 112
 113         plt_write64(0, base + SSO_LF_GGRP_QCTL);
 114
 115         req = queue_id;     /* GGRP ID */
 116         req |= BIT_ULL(18); /* Grouped */
 117         req |= BIT_ULL(16); /* WAIT */
 118
 119         aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 120         ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 121         cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 122         cq_ds_cnt &= 0x3FFF3FFF0000;
 123
 124         while (aq_cnt || cq_ds_cnt || ds_cnt) {
 125                 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 126                 cn10k_sso_hws_get_work_empty(ws, &ev);
 127                 if (fn != NULL && ev.u64 != 0)
 128                         fn(arg, ev);
 129                 if (ev.sched_type != SSO_TT_EMPTY)
 130                         cnxk_sso_hws_swtag_flush(
 131                                 ws->base + SSOW_LF_GWS_WQE0,
 132                                 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
 133                 do {
 134                         val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
 135                 } while (val & BIT_ULL(56));
 136                 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
 137                 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
 138                 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
 139                 /* Extract cq and ds count */
 140                 cq_ds_cnt &= 0x3FFF3FFF0000;
 141         }
 142
 143         plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
 144         rte_mb();
 145 }
 146
 147 static void
 148 cn10k_sso_hws_reset(void *arg, void *hws)
 149 {
 150         struct cnxk_sso_evdev *dev = arg;
 151         struct cn10k_sso_hws *ws = hws;
 152         uintptr_t base = ws->base;
 153         uint64_t pend_state;
 154         union {
 155                 __uint128_t wdata;
 156                 uint64_t u64[2];
 157         } gw;
 158         uint8_t pend_tt;
 159
 160         /* Wait till getwork/swtp/waitw/desched completes. */
 161         do {
 162                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 163         } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
 164                                BIT_ULL(56) | BIT_ULL(54)));
 165         pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 166         if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 167                 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
 168                         cnxk_sso_hws_swtag_untag(base +
 169                                                  SSOW_LF_GWS_OP_SWTAG_UNTAG);
 170                 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 171         }
 172
 173         /* Wait for desched to complete. */
 174         do {
 175                 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
 176         } while (pend_state & BIT_ULL(58));
 177
 178         switch (dev->gw_mode) {
 179         case CN10K_GW_MODE_PREF:
 180                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
 181                         ;
 182                 break;
 183         case CN10K_GW_MODE_PREF_WFE:
 184                 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
 185                        SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
 186                         continue;
 187                 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 188                 break;
 189         case CN10K_GW_MODE_NONE:
 190         default:
 191                 break;
 192         }
 193
 194         if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
 195             SSO_TT_EMPTY) {
 196                 plt_write64(BIT_ULL(16) | 1,
 197                             ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 198                 do {
 199                         roc_load_pair(gw.u64[0], gw.u64[1],
 200                                       ws->base + SSOW_LF_GWS_WQE0);
 201                 } while (gw.u64[0] & BIT_ULL(63));
 202                 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
 203                 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
 204                         if (pend_tt == SSO_TT_ATOMIC ||
 205                             pend_tt == SSO_TT_ORDERED)
 206                                 cnxk_sso_hws_swtag_untag(
 207                                         base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
 208                         plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
 209                 }
 210         }
 211
 212         plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
 213         rte_mb();
 214 }
 215
 216 static void
 217 cn10k_sso_set_rsrc(void *arg)
 218 {
 219         struct cnxk_sso_evdev *dev = arg;
 220
 221         dev->max_event_ports = dev->sso.max_hws;
 222         dev->max_event_queues =
 223                 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
 224                               RTE_EVENT_MAX_QUEUES_PER_DEV :
 225                               dev->sso.max_hwgrp;
 226 }
 227
 228 static int
 229 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
 230 {
 231         struct cnxk_sso_evdev *dev = arg;
 232
 233         return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
 234 }
 235
 236 static void
 237 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
 238 {
 239         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 240         const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {
 241 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 242         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,
 243                 NIX_RX_FASTPATH_MODES
 244 #undef R
 245         };
 246
 247         const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {
 248 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 249         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,
 250                 NIX_RX_FASTPATH_MODES
 251 #undef R
 252         };
 253
 254         const event_dequeue_t sso_hws_tmo_deq[2][2][2][2][2][2] = {
 255 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 256         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,
 257                 NIX_RX_FASTPATH_MODES
 258 #undef R
 259         };
 260
 261         const event_dequeue_burst_t sso_hws_tmo_deq_burst[2][2][2][2][2][2] = {
 262 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 263         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,
 264                 NIX_RX_FASTPATH_MODES
 265 #undef R
 266         };
 267
 268         const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
 269 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 270         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
 271                 NIX_RX_FASTPATH_MODES
 272 #undef R
 273         };
 274
 275         const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {
 276 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 277         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,
 278                 NIX_RX_FASTPATH_MODES
 279 #undef R
 280         };
 281
 282         const event_dequeue_t sso_hws_tmo_deq_seg[2][2][2][2][2][2] = {
 283 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 284         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,
 285                 NIX_RX_FASTPATH_MODES
 286 #undef R
 287         };
 288
 289         const event_dequeue_burst_t
 290                 sso_hws_tmo_deq_seg_burst[2][2][2][2][2][2] = {
 291 #define R(name, f5, f4, f3, f2, f1, f0, flags)                                 \
 292         [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
 293                         NIX_RX_FASTPATH_MODES
 294 #undef R
 295                 };
 296
 297         event_dev->enqueue = cn10k_sso_hws_enq;
 298         event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
 299         event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
 300         event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
 301         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 302                 event_dev->dequeue = sso_hws_deq_seg
 303                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 304                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 305                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 306                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 307                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 308                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 309                 event_dev->dequeue_burst = sso_hws_deq_seg_burst
 310                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 311                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 312                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 313                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 314                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 315                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 316                 if (dev->is_timeout_deq) {
 317                         event_dev->dequeue = sso_hws_tmo_deq_seg
 318                                 [!!(dev->rx_offloads &
 319                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 320                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 321                                 [!!(dev->rx_offloads &
 322                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 323                                 [!!(dev->rx_offloads &
 324                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 325                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 326                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 327                         event_dev->dequeue_burst = sso_hws_tmo_deq_seg_burst
 328                                 [!!(dev->rx_offloads &
 329                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 330                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 331                                 [!!(dev->rx_offloads &
 332                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 333                                 [!!(dev->rx_offloads &
 334                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 335                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 336                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 337                 }
 338         } else {
 339                 event_dev->dequeue = sso_hws_deq
 340                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 341                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 342                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 343                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 344                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 345                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 346                 event_dev->dequeue_burst = sso_hws_deq_burst
 347                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 348                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 349                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 350                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 351                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 352                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 353                 if (dev->is_timeout_deq) {
 354                         event_dev->dequeue = sso_hws_tmo_deq
 355                                 [!!(dev->rx_offloads &
 356                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 357                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 358                                 [!!(dev->rx_offloads &
 359                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 360                                 [!!(dev->rx_offloads &
 361                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 362                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 363                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 364                         event_dev->dequeue_burst = sso_hws_tmo_deq_burst
 365                                 [!!(dev->rx_offloads &
 366                                     NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 367                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 368                                 [!!(dev->rx_offloads &
 369                                     NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 370                                 [!!(dev->rx_offloads &
 371                                     NIX_RX_OFFLOAD_CHECKSUM_F)]
 372                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 373                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 374                 }
 375         }
 376 }
 377
 378 static void
 379 cn10k_sso_info_get(struct rte_eventdev *event_dev,
 380                    struct rte_event_dev_info *dev_info)
 381 {
 382         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 383
 384         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
 385         cnxk_sso_info_get(dev, dev_info);
 386 }
 387
 388 static int
 389 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
 390 {
 391         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 392         int rc;
 393
 394         rc = cnxk_sso_dev_validate(event_dev);
 395         if (rc < 0) {
 396                 plt_err("Invalid event device configuration");
 397                 return -EINVAL;
 398         }
 399
 400         roc_sso_rsrc_fini(&dev->sso);
 401
 402         rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
 403                                  dev->nb_event_queues);
 404         if (rc < 0) {
 405                 plt_err("Failed to initialize SSO resources");
 406                 return -ENODEV;
 407         }
 408
 409         rc = cnxk_sso_xaq_allocate(dev);
 410         if (rc < 0)
 411                 goto cnxk_rsrc_fini;
 412
 413         rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
 414                                     cn10k_sso_hws_setup);
 415         if (rc < 0)
 416                 goto cnxk_rsrc_fini;
 417
 418         /* Restore any prior port-queue mapping. */
 419         cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
 420
 421         dev->configured = 1;
 422         rte_mb();
 423
 424         return 0;
 425 cnxk_rsrc_fini:
 426         roc_sso_rsrc_fini(&dev->sso);
 427         dev->nb_event_ports = 0;
 428         return rc;
 429 }
 430
 431 static int
 432 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 433                      const struct rte_event_port_conf *port_conf)
 434 {
 435
 436         RTE_SET_USED(port_conf);
 437         return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
 438 }
 439
 440 static void
 441 cn10k_sso_port_release(void *port)
 442 {
 443         struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
 444         struct cnxk_sso_evdev *dev;
 445
 446         if (port == NULL)
 447                 return;
 448
 449         dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
 450         if (!gws_cookie->configured)
 451                 goto free;
 452
 453         cn10k_sso_hws_release(dev, port);
 454         memset(gws_cookie, 0, sizeof(*gws_cookie));
 455 free:
 456         rte_free(gws_cookie);
 457 }
 458
 459 static int
 460 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
 461                     const uint8_t queues[], const uint8_t priorities[],
 462                     uint16_t nb_links)
 463 {
 464         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 465         uint16_t hwgrp_ids[nb_links];
 466         uint16_t link;
 467
 468         RTE_SET_USED(priorities);
 469         for (link = 0; link < nb_links; link++)
 470                 hwgrp_ids[link] = queues[link];
 471         nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
 472
 473         return (int)nb_links;
 474 }
 475
 476 static int
 477 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 478                       uint8_t queues[], uint16_t nb_unlinks)
 479 {
 480         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 481         uint16_t hwgrp_ids[nb_unlinks];
 482         uint16_t unlink;
 483
 484         for (unlink = 0; unlink < nb_unlinks; unlink++)
 485                 hwgrp_ids[unlink] = queues[unlink];
 486         nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
 487
 488         return (int)nb_unlinks;
 489 }
 490
 491 static int
 492 cn10k_sso_start(struct rte_eventdev *event_dev)
 493 {
 494         int rc;
 495
 496         rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
 497                             cn10k_sso_hws_flush_events);
 498         if (rc < 0)
 499                 return rc;
 500         cn10k_sso_fp_fns_set(event_dev);
 501
 502         return rc;
 503 }
 504
 505 static void
 506 cn10k_sso_stop(struct rte_eventdev *event_dev)
 507 {
 508         cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
 509                       cn10k_sso_hws_flush_events);
 510 }
 511
 512 static int
 513 cn10k_sso_close(struct rte_eventdev *event_dev)
 514 {
 515         return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
 516 }
 517
 518 static int
 519 cn10k_sso_selftest(void)
 520 {
 521         return cnxk_sso_selftest(RTE_STR(event_cn10k));
 522 }
 523
 524 static int
 525 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
 526                               const struct rte_eth_dev *eth_dev, uint32_t *caps)
 527 {
 528         int rc;
 529
 530         RTE_SET_USED(event_dev);
 531         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
 532         if (rc)
 533                 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
 534         else
 535                 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
 536                         RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
 537                         RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;
 538
 539         return 0;
 540 }
 541
 542 static void
 543 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
 544                        void *tstmp_info)
 545 {
 546         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 547         int i;
 548
 549         for (i = 0; i < dev->nb_event_ports; i++) {
 550                 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
 551                 ws->lookup_mem = lookup_mem;
 552                 ws->tstamp = tstmp_info;
 553         }
 554 }
 555
 556 static int
 557 cn10k_sso_rx_adapter_queue_add(
 558         const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
 559         int32_t rx_queue_id,
 560         const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 561 {
 562         struct cn10k_eth_rxq *rxq;
 563         void *lookup_mem;
 564         void *tstmp_info;
 565         int rc;
 566
 567         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 568         if (rc)
 569                 return -EINVAL;
 570
 571         rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
 572                                            queue_conf);
 573         if (rc)
 574                 return -EINVAL;
 575         rxq = eth_dev->data->rx_queues[0];
 576         lookup_mem = rxq->lookup_mem;
 577         tstmp_info = rxq->tstamp;
 578         cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
 579         cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
 580
 581         return 0;
 582 }
 583
 584 static int
 585 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
 586                                const struct rte_eth_dev *eth_dev,
 587                                int32_t rx_queue_id)
 588 {
 589         int rc;
 590
 591         rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
 592         if (rc)
 593                 return -EINVAL;
 594
 595         return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
 596 }
 597
 598 static struct rte_eventdev_ops cn10k_sso_dev_ops = {
 599         .dev_infos_get = cn10k_sso_info_get,
 600         .dev_configure = cn10k_sso_dev_configure,
 601         .queue_def_conf = cnxk_sso_queue_def_conf,
 602         .queue_setup = cnxk_sso_queue_setup,
 603         .queue_release = cnxk_sso_queue_release,
 604         .port_def_conf = cnxk_sso_port_def_conf,
 605         .port_setup = cn10k_sso_port_setup,
 606         .port_release = cn10k_sso_port_release,
 607         .port_link = cn10k_sso_port_link,
 608         .port_unlink = cn10k_sso_port_unlink,
 609         .timeout_ticks = cnxk_sso_timeout_ticks,
 610
 611         .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
 612         .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
 613         .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
 614         .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
 615         .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
 616
 617         .timer_adapter_caps_get = cnxk_tim_caps_get,
 618
 619         .dump = cnxk_sso_dump,
 620         .dev_start = cn10k_sso_start,
 621         .dev_stop = cn10k_sso_stop,
 622         .dev_close = cn10k_sso_close,
 623         .dev_selftest = cn10k_sso_selftest,
 624 };
 625
 626 static int
 627 cn10k_sso_init(struct rte_eventdev *event_dev)
 628 {
 629         struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
 630         int rc;
 631
 632         if (RTE_CACHE_LINE_SIZE != 64) {
 633                 plt_err("Driver not compiled for CN9K");
 634                 return -EFAULT;
 635         }
 636
 637         rc = roc_plt_init();
 638         if (rc < 0) {
 639                 plt_err("Failed to initialize platform model");
 640                 return rc;
 641         }
 642
 643         event_dev->dev_ops = &cn10k_sso_dev_ops;
 644         /* For secondary processes, the primary has done all the work */
 645         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 646                 cn10k_sso_fp_fns_set(event_dev);
 647                 return 0;
 648         }
 649
 650         rc = cnxk_sso_init(event_dev);
 651         if (rc < 0)
 652                 return rc;
 653
 654         cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
 655         if (!dev->max_event_ports || !dev->max_event_queues) {
 656                 plt_err("Not enough eventdev resource queues=%d ports=%d",
 657                         dev->max_event_queues, dev->max_event_ports);
 658                 cnxk_sso_fini(event_dev);
 659                 return -ENODEV;
 660         }
 661
 662         plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
 663                     event_dev->data->name, dev->max_event_queues,
 664                     dev->max_event_ports);
 665
 666         return 0;
 667 }
 668
 669 static int
 670 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 671 {
 672         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
 673                                        sizeof(struct cnxk_sso_evdev),
 674                                        cn10k_sso_init);
 675 }
 676
 677 static const struct rte_pci_id cn10k_pci_sso_map[] = {
 678         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 679         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
 680         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 681         CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
 682         {
 683                 .vendor_id = 0,
 684         },
 685 };
 686
 687 static struct rte_pci_driver cn10k_pci_sso = {
 688         .id_table = cn10k_pci_sso_map,
 689         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
 690         .probe = cn10k_sso_probe,
 691         .remove = cnxk_sso_remove,
 692 };
 693
 694 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
 695 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
 696 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
 697 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
 698                               CNXK_SSO_GGRP_QOS "=<string>"
 699                               CNXK_SSO_FORCE_BP "=1"
 700                               CN10K_SSO_GW_MODE "=<int>"
 701                               CNXK_TIM_DISABLE_NPA "=1"
 702                               CNXK_TIM_CHNK_SLOTS "=<int>"
 703                               CNXK_TIM_RINGS_LMT "=<int>"
 704                               CNXK_TIM_STATS_ENA "=1");